mirror of
https://github.com/Dark98/Ender-3_V3_KE_Klipper.git
synced 2026-07-02 16:49:04 +00:00
update for open source
This commit is contained in:
liyongjie
@@ -0,0 +1,6 @@
|
||||
*.o
|
||||
bossac/bin/
|
||||
bossac/obj/
|
||||
hidflash/hid-flash
|
||||
hub-ctrl/hub-ctrl
|
||||
rp2040_flash/rp2040_flash
|
||||
+154
@@ -0,0 +1,154 @@
|
||||
This directory contains external library code.
|
||||
|
||||
The cmsis directory contains code from:
|
||||
https://github.com/ARM-software/CMSIS_5
|
||||
version 5.7.0 (a65b7c9a3e6502127fdb80eb288d8cbdf251a6f4). Contents
|
||||
taken from the CMSIS/Core/Include/ directory.
|
||||
|
||||
The sam3x directory contains code from the
|
||||
Atmel.SAM3X_DFP.1.0.50.atpack zip file found at:
|
||||
http://packs.download.atmel.com/
|
||||
version 1.0.50 (extracted on 20180725).
|
||||
|
||||
The sam4e directory contains code from the
|
||||
Atmel.SAM4E_DFP.1.1.57.atpack zip file found at:
|
||||
http://packs.download.atmel.com/
|
||||
version 1.1.57 (extracted on 20180806). It has been modified to fix
|
||||
some AFEC register RW accesses. See sam4e.patch for the modifications.
|
||||
|
||||
The sam4s directory contains code from the
|
||||
Atmel.SAM4S_DFP.1.0.56.atpack zip file found at:
|
||||
http://packs.download.atmel.com/
|
||||
version 1.0.56 (extracted on 20181220).
|
||||
|
||||
The samd21 directory contains code from the
|
||||
Atmel.SAMD21_DFP.1.3.304.atpack zip file found at:
|
||||
http://packs.download.atmel.com/
|
||||
version 1.3.304 (extracted on 20180725).
|
||||
|
||||
The samd51 directory contains code from the
|
||||
Atmel.SAMD51_DFP.1.1.96.atpack zip file found at:
|
||||
http://packs.download.atmel.com/
|
||||
version 1.1.96 (extracted on 20190110).
|
||||
|
||||
The same51 directory contains code from the
|
||||
Atmel.SAME51_DFP.1.1.139.atpack zip file found at:
|
||||
http://packs.download.atmel.com/
|
||||
version 1.1.139 (extracted on 20220929).
|
||||
|
||||
The same54 directory contains code from the
|
||||
Atmel.SAME54_DFP.1.1.134.atpack zip file found at:
|
||||
http://packs.download.atmel.com/
|
||||
version 1.1.134 (extracted on 20221005).
|
||||
|
||||
The same70b directory contains code from the
|
||||
Atmel.SAME70_DFP.2.4.166.atpack zip file found at:
|
||||
http://packs.download.atmel.com/
|
||||
version 2.4.166 (extracted on 20210809).
|
||||
|
||||
The lpc176x directory contains code from the mbed project:
|
||||
https://github.com/ARMmbed/mbed-os
|
||||
version mbed-os-5.8.3 (c05d72c3c005fbb7e92c3994c32bda45218ae7fe).
|
||||
Contents taken from the targets/TARGET_NXP/TARGET_LPC176X/ directory.
|
||||
It has been modified to set the appropriate clock speeds on the
|
||||
LPC1768 and LPC1769. See lpc176x.patch for the modifications.
|
||||
|
||||
The stm32f0 directory contains code from:
|
||||
https://github.com/STMicroelectronics/STM32CubeF0
|
||||
version v1.10.1 (d0c380d668c67dcdd4e44f656be27045ce4006a6). Contents
|
||||
taken from the Drivers/CMSIS/Device/ST/STM32F0xx/ directory.
|
||||
|
||||
The stm32f1 directory contains code from:
|
||||
https://github.com/STMicroelectronics/STM32CubeF1
|
||||
version v1.8.0 (441b2cbdc25aa50437a59c4bffe22b88e78942c9). Contents
|
||||
taken from the Drivers/CMSIS/Device/ST/STM32F1xx/ directory.
|
||||
|
||||
The stm32f2 directory contains code from:
|
||||
https://github.com/STMicroelectronics/STM32CubeF2
|
||||
version v1.9.0 (42fc8bf966c04ef814bb0620dcd3e036e038b4a2). Contents
|
||||
taken from the Drivers/CMSIS/Device/ST/STM32F2xx/ directory.
|
||||
|
||||
The stm32f4 directory contains code from:
|
||||
https://github.com/STMicroelectronics/STM32CubeF4
|
||||
version v1.24.1 (b5abca20c9676b04f8d2885a668a9b653ee65705). Contents
|
||||
taken from the Drivers/CMSIS/Device/ST/STM32F4xx/ directory.
|
||||
|
||||
The stm32g0 directory contains code from:
|
||||
https://github.com/STMicroelectronics/STM32CubeG0
|
||||
version v1.4.1 (5cb06333a6a43cefbe145f10a5aa98d3cc4cffee). Contents
|
||||
taken from the Drivers/CMSIS/Device/ST/STM32G0xx/ directory.
|
||||
|
||||
The stm32g4 directory contains code from:
|
||||
https://github.com/STMicroelectronics/STM32CubeG4
|
||||
version v1.4.0 (e762fe2ce800cf6c18a1868a3aabc7e9351751bd). Contents
|
||||
taken from the Drivers/CMSIS/Device/ST/STM32G4xx/ directory.
|
||||
|
||||
The stm32l4 directory contains code from:
|
||||
https://github.com/STMicroelectronics/STM32CubeL4
|
||||
version v1.17.0 (5e1553e07706491bd11f4edd304e093b6e4b83a4). Contents
|
||||
taken from the Drivers/CMSIS/Device/ST/STM32L4xx/ directory.
|
||||
|
||||
The stm32h7 directory contains code from:
|
||||
https://github.com/STMicroelectronics/STM32CubeH7
|
||||
version v1.9.0 (ccb11556044540590ca6e45056e6b65cdca2deb2). Contents
|
||||
taken from the Drivers/CMSIS/Device/ST/STM32H7xx/ directory.
|
||||
|
||||
The rp2040 directory contains code from the pico sdk:
|
||||
https://github.com/raspberrypi/pico-sdk.git
|
||||
version 1.2.0 (bfcbefafc5d2a210551a4d9d80b4303d4ae0adf7). It has been
|
||||
modified so that it can build outside of the pico sdk. See
|
||||
rp2040.patch for the modifications.
|
||||
|
||||
The rp2040_flash directory contains a light-weight bootsel flash tool.
|
||||
It uses C part of the the `picoboot_connection` directory found in:
|
||||
https://github.com/raspberrypi/picotool.git
|
||||
version v1.1.0 (55fd880c3dc029b961fc1a0967a6cfdc0af02721).
|
||||
|
||||
The hub-ctrl directory contains code from:
|
||||
https://github.com/codazoda/hub-ctrl.c/
|
||||
revision 42095e522859059e8a5f4ec05c1e3def01a870a9.
|
||||
|
||||
The bossac directory contains code from:
|
||||
https://github.com/shumatech/BOSSA
|
||||
version 1.9 (b176eeef918fc810045c832348590595120187b4).
|
||||
|
||||
The hidflash directory contains code from:
|
||||
https://github.com/Serasidis/STM32_HID_Bootloader
|
||||
version 2.2.2 (2ab7927a27b7b78ef730782ea5f9b5d2c8f34671). It has been
|
||||
modified to work with Klipper - see hidflash/README for the
|
||||
details. See changes.diff for the modifications.
|
||||
|
||||
The pru_rpmsg directory contains code from:
|
||||
https://github.com/dinuxbg/pru-gcc-examples
|
||||
revision 425a42d82006cf0aa24be27b483d2f6a41607489. The code is taken
|
||||
from the repo's hc-sr04-range-sensor directory. It has been modified
|
||||
so that the IEP definitions compile correctly. See pru_rpmsg.patch for
|
||||
the modifications.
|
||||
|
||||
The fast-hash directory contains code from:
|
||||
https://github.com/ztanml/fast-hash
|
||||
revision ae3bb53c199fe75619e940b5b6a3584ede99c5fc
|
||||
|
||||
The kconfiglib directory contains code from:
|
||||
https://github.com/ulfalizer/Kconfiglib.git
|
||||
version v14.1.0 (061e71f7d78cb057762d88de088055361863deff). It has
|
||||
been modified to always emit symbols and to simplify the "menuconfig"
|
||||
screens. See kconfiglib.patch for the modifications.
|
||||
|
||||
The fatfs directory contains code from:
|
||||
http://elm-chan.org/fsw/ff/00index_e.html
|
||||
version R0.14a (extracted 20210116). The configuration (ffconf.h)
|
||||
has been modfied to enable the US code page (437) and enable label
|
||||
support. The file "diskio.c" in the original archive is not included
|
||||
as it is only serves as an example for how to implement the media api
|
||||
callbacks.
|
||||
|
||||
The canboot directory contains code from:
|
||||
https://github.com/Arksine/CanBoot
|
||||
revision 870200826561b150137913d42fd7edc6515229ff. The Python module,
|
||||
flash_can.py, is taken from the repo's scripts directory. It may be
|
||||
used to upload firmware to devices flashed with the CanBoot bootloader.
|
||||
|
||||
The can2040 directory contains code from:
|
||||
https://github.com/KevinOConnor/can2040
|
||||
revision 177b0073fe6f19281ee7f7fdbe9599e32d1b4b8b.
|
||||
@@ -0,0 +1,24 @@
|
||||
Copyright (c) 2011-2016, ShumaTech
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
* Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
* Neither the name of the <organization> nor the
|
||||
names of its contributors may be used to endorse or promote products
|
||||
derived from this software without specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
@@ -0,0 +1,347 @@
|
||||
.DEFAULT_GOAL := all
|
||||
|
||||
#
|
||||
# Version
|
||||
#
|
||||
VERSION=1.9
|
||||
WXVERSION=3.0
|
||||
|
||||
#
|
||||
# Source files
|
||||
#
|
||||
COMMON_SRCS=Samba.cpp Flash.cpp D5xNvmFlash.cpp D2xNvmFlash.cpp EfcFlash.cpp EefcFlash.cpp Applet.cpp WordCopyApplet.cpp Flasher.cpp Device.cpp
|
||||
APPLET_SRCS=WordCopyArm.asm
|
||||
BOSSA_SRCS=BossaForm.cpp BossaWindow.cpp BossaAbout.cpp BossaApp.cpp BossaBitmaps.cpp BossaInfo.cpp BossaThread.cpp BossaProgress.cpp
|
||||
BOSSA_BMPS=BossaLogo.bmp BossaIcon.bmp ShumaTechLogo.bmp
|
||||
BOSSAC_SRCS=bossac.cpp CmdOpts.cpp
|
||||
BOSSASH_SRCS=bossash.cpp Shell.cpp Command.cpp
|
||||
|
||||
#
|
||||
# Build directories
|
||||
#
|
||||
BINDIR=bin
|
||||
OBJDIR=obj
|
||||
SRCDIR=src
|
||||
RESDIR=res
|
||||
INSTALLDIR=install
|
||||
|
||||
#
|
||||
# Determine OS
|
||||
#
|
||||
OS:=$(shell uname -s | cut -c -7)
|
||||
|
||||
#
|
||||
# Windows rules
|
||||
#
|
||||
ifeq ($(OS),MINGW32)
|
||||
# Use wxWindows development branch to work around font scaling issues on Windows
|
||||
WXVERSION=3.1
|
||||
EXE=.exe
|
||||
COMMON_SRCS+=WinSerialPort.cpp WinPortFactory.cpp
|
||||
COMMON_LDFLAGS=-Wl,--enable-auto-import -static -static-libstdc++ -static-libgcc
|
||||
COMMON_LIBS=-ltermcap -Wl,--as-needed -lsetupapi
|
||||
BOSSA_RC=BossaRes.rc
|
||||
WIXDIR="C:\Program Files (x86)\WiX Toolset v3.10\bin"
|
||||
CODE_SIGN=$(INSTALLDIR)\\code_sign.p12
|
||||
TIMESTAMP=http://timestamp.comodoca.com/authenticode
|
||||
SIGNTOOL="C:\Program Files (x86)\Windows Kits\10\bin\x64\signtool.exe"
|
||||
INF2CAT="C:\Program Files (x86)\Windows Kits\10\bin\x86\Inf2Cat.exe"
|
||||
|
||||
define bossa_msi
|
||||
$(OBJDIR)\\bossa-$(1)-$(VERSION).wixobj: $(INSTALLDIR)\\bossa.wxs
|
||||
$(WIXDIR)\\candle.exe -dVersion=$(VERSION) -arch $(1) -out $$@ -ext $(WIXDIR)\\WixUIExtension.dll -ext $(WIXDIR)\\WixDifxAppExtension.dll $$<
|
||||
|
||||
$(BINDIR)\\bossa-$(1)-$(VERSION).msi: $(OBJDIR)\\bossa-$(1)-$(VERSION).wixobj
|
||||
$(WIXDIR)\\light.exe -cultures:null -out $$@ -pdbout $(OBJDIR)\\bossa.wixpdb -sice:ICE57 -ext $(WIXDIR)\\WixUIExtension.dll -ext $(WIXDIR)\\WixDifxAppExtension.dll $(WIXDIR)\\difxapp_$(1).wixlib $$<
|
||||
$$(Q)read -p "Password:" -rs PASSWORD; \
|
||||
cmd /C '$(SIGNTOOL) sign /v /fd sha256 /f $(CODE_SIGN) -t $(TIMESTAMP) /p '$$$$PASSWORD' $$@'
|
||||
endef
|
||||
|
||||
$(eval $(call bossa_msi,x86))
|
||||
$(eval $(call bossa_msi,x64))
|
||||
|
||||
$(INSTALLDIR)\\bossa.cat: $(INSTALLDIR)\\bossa.inf
|
||||
export TMP=$$(mktemp -d); \
|
||||
cp $< $$TMP; \
|
||||
cmd /C '$(INF2CAT) /v /driver:'$$(cygpath -w $$TMP)' /os:XP_X86,Vista_X86,Vista_X64,7_X86,7_X64,8_X86,8_X64,6_3_X86,6_3_X64,10_x86,10_x64'; \
|
||||
mv $$TMP/bossa.cat $@; \
|
||||
rm -rf $$TMP; \
|
||||
read -p "Password:" -rs PASSWORD; \
|
||||
cmd /C '$(SIGNTOOL) sign /v /fd sha256 /f $(CODE_SIGN) -t $(TIMESTAMP) /p '$$PASSWORD' $@'
|
||||
|
||||
bossa.cat: $(INSTALLDIR)\\bossa.cat
|
||||
|
||||
install32: $(BINDIR)\\bossa-x86-$(VERSION).msi
|
||||
install64: $(BINDIR)\\bossa-x64-$(VERSION).msi
|
||||
.PHONY: install
|
||||
install: strip install32 install64
|
||||
|
||||
endif
|
||||
|
||||
#
|
||||
# Linux rules
|
||||
#
|
||||
ifeq ($(OS),Linux)
|
||||
COMMON_SRCS+=PosixSerialPort.cpp LinuxPortFactory.cpp
|
||||
COMMON_LIBS=-Wl,--as-needed
|
||||
COMMON_CXXFLAGS=-std=c++11
|
||||
WX_LIBS+=-lX11
|
||||
|
||||
MACHINE:=$(shell uname -m)
|
||||
|
||||
install: strip
|
||||
tar cvzf $(BINDIR)/bossa-$(MACHINE)-$(VERSION).tgz -C $(BINDIR) bossa$(EXE) bossac$(EXE) bossash$(EXE)
|
||||
endif
|
||||
|
||||
#
|
||||
# OS X rules
|
||||
#
|
||||
ifeq ($(OS),Darwin)
|
||||
COMMON_SRCS+=PosixSerialPort.cpp OSXPortFactory.cpp
|
||||
COMMON_CXXFLAGS=-arch x86_64 -mmacosx-version-min=10.9
|
||||
COMMON_LDFLAGS=-arch x86_64 -mmacosx-version-min=10.9
|
||||
APP=BOSSA.app
|
||||
DMG=bossa-$(VERSION).dmg
|
||||
VOLUME=BOSSA
|
||||
BACKGROUND=$(INSTALLDIR)/background.png
|
||||
.PHONY: install
|
||||
app:
|
||||
mkdir -p $(BINDIR)/$(APP)/Contents/MacOS
|
||||
mkdir -p $(BINDIR)/$(APP)/Contents/Resources
|
||||
cp -f $(INSTALLDIR)/Info.plist $(BINDIR)/$(APP)/Contents
|
||||
echo -n "APPL????" > $(BINDIR)/$(APP)/Contents/PkgInfo
|
||||
ln -f $(BINDIR)/bossa $(BINDIR)/$(APP)/Contents/MacOS/bossa
|
||||
cp -f $(RESDIR)/BossaIcon.icns $(BINDIR)/$(APP)/Contents/Resources
|
||||
install: strip app
|
||||
hdiutil create -ov -megabytes 5 -fs HFS+ -volname $(VOLUME) $(BINDIR)/$(DMG)
|
||||
hdiutil attach -noautoopen $(BINDIR)/$(DMG)
|
||||
cp -R $(BINDIR)/$(APP) /Volumes/$(VOLUME)/
|
||||
cp $(BINDIR)/bossac$(EXE) /Volumes/$(VOLUME)/
|
||||
cp $(BINDIR)/bossash$(EXE) /Volumes/$(VOLUME)/
|
||||
ln -s /Applications /Volumes/$(VOLUME)/Applications
|
||||
ln -s /usr/local/bin /Volumes/$(VOLUME)/bin
|
||||
mkdir /Volumes/$(VOLUME)/.background
|
||||
cp $(BACKGROUND) /Volumes/$(VOLUME)/.background
|
||||
osascript < $(INSTALLDIR)/dmgwin.osa
|
||||
hdiutil detach /Volumes/$(VOLUME)/
|
||||
hdiutil convert -format UDBZ -o $(BINDIR)/tmp$(DMG) $(BINDIR)/$(DMG)
|
||||
mv -f $(BINDIR)/tmp$(DMG) $(BINDIR)/$(DMG)
|
||||
endif
|
||||
|
||||
#
|
||||
# OpenBSD rules
|
||||
# (This is likely to work without changes, but not tested, on other BSDs)
|
||||
#
|
||||
ifeq ($(OS),OpenBSD)
|
||||
|
||||
COMMON_SRCS+=PosixSerialPort.cpp BSDPortFactory.cpp
|
||||
|
||||
# This is only needed for bossash, but we can't add it to BOSSASH_LIBS here
|
||||
# because that one is redefined later.
|
||||
COMMON_LIBS+=-ltermcap
|
||||
|
||||
# As of 5.7, OpenBSD packages WxWidgets 2.8
|
||||
# bossa builds, runs, and appears to play nicely with this version,
|
||||
# but fails to do anything useful on systems that don't have hardware
|
||||
# serial ports because of USB detection problems.
|
||||
# (The SAM's USB programming port doesn't get recognized as a ucom
|
||||
# device, and a USB serial adaptor attached to the UART gets detected
|
||||
# by bossa as a USB interface and doesn't fall back to the serial
|
||||
# programming protocol.)
|
||||
WXVERSION=2.8
|
||||
|
||||
endif
|
||||
|
||||
ifeq (${OS},FreeBSD)
|
||||
|
||||
# This is only needed for bossash, but we can't add it to BOSSASH_LIBS here
|
||||
# because that one is redefined later.
|
||||
COMMON_SRCS+=PosixSerialPort.cpp BSDPortFactory.cpp
|
||||
|
||||
endif
|
||||
|
||||
#
|
||||
# Object files
|
||||
#
|
||||
COMMON_OBJS=$(foreach src,$(COMMON_SRCS),$(OBJDIR)/$(src:%.cpp=%.o))
|
||||
APPLET_OBJS=$(foreach src,$(APPLET_SRCS),$(OBJDIR)/$(src:%.asm=%.o))
|
||||
BOSSA_OBJS=$(APPLET_OBJS) $(COMMON_OBJS) $(foreach src,$(BOSSA_SRCS),$(OBJDIR)/$(src:%.cpp=%.o))
|
||||
ifdef BOSSA_RC
|
||||
BOSSA_OBJS+=$(OBJDIR)/$(BOSSA_RC:%.rc=%.o)
|
||||
endif
|
||||
BOSSAC_OBJS=$(APPLET_OBJS) $(COMMON_OBJS) $(foreach src,$(BOSSAC_SRCS),$(OBJDIR)/$(src:%.cpp=%.o))
|
||||
BOSSASH_OBJS=$(APPLET_OBJS) $(COMMON_OBJS) $(foreach src,$(BOSSASH_SRCS),$(OBJDIR)/$(src:%.cpp=%.o))
|
||||
|
||||
#
|
||||
# Dependencies
|
||||
#
|
||||
DEPENDS=$(COMMON_SRCS:%.cpp=$(OBJDIR)/%.d)
|
||||
DEPENDS+=$(APPLET_SRCS:%.asm=$(OBJDIR)/%.d)
|
||||
DEPENDS+=$(BOSSA_SRCS:%.cpp=$(OBJDIR)/%.d)
|
||||
DEPENDS+=$(BOSSAC_SRCS:%.cpp=$(OBJDIR)/%.d)
|
||||
DEPENDS+=$(BOSSASH_SRCS:%.cpp=$(OBJDIR)/%.d)
|
||||
|
||||
#
|
||||
# Tools
|
||||
#
|
||||
Q?=@
|
||||
CXX?=g++
|
||||
ARM=arm-none-eabi-
|
||||
ARMAS=$(ARM)as
|
||||
ARMOBJCOPY=$(ARM)objcopy
|
||||
|
||||
#
|
||||
# CXX Flags
|
||||
#
|
||||
# COMMON_CXXFLAGS+=-Wall -Werror -MT $@ -MD -MP -MF $(@:%.o=%.d) -DVERSION=\"$(VERSION)\" -g -O2
|
||||
COMMON_CXXFLAGS+=-Wall -MT $@ -MD -MP -MF $(@:%.o=%.d) -DVERSION=\"$(VERSION)\" -g -O2 $(CXXFLAGS)
|
||||
WX_CXXFLAGS:=$(shell wx-config --cxxflags --version=$(WXVERSION)) -DWX_PRECOMP -Wno-ctor-dtor-privacy -O2 -fno-strict-aliasing
|
||||
BOSSA_CXXFLAGS=$(COMMON_CXXFLAGS) $(WX_CXXFLAGS)
|
||||
BOSSAC_CXXFLAGS=$(COMMON_CXXFLAGS)
|
||||
BOSSASH_CXXFLAGS=$(COMMON_CXXFLAGS)
|
||||
|
||||
#
|
||||
# LD Flags
|
||||
#
|
||||
COMMON_LDFLAGS+=-g $(LDFLAGS)
|
||||
BOSSA_LDFLAGS=$(COMMON_LDFLAGS)
|
||||
BOSSAC_LDFLAGS=$(COMMON_LDFLAGS)
|
||||
BOSSASH_LDFLAGS=$(COMMON_LDFLAGS)
|
||||
|
||||
#
|
||||
# Libs
|
||||
#
|
||||
COMMON_LIBS+=
|
||||
WX_LIBS:=$(shell wx-config --libs --version=$(WXVERSION)) $(WX_LIBS)
|
||||
BOSSA_LIBS=$(COMMON_LIBS) $(WX_LIBS)
|
||||
BOSSAC_LIBS=$(COMMON_LIBS)
|
||||
BOSSASH_LIBS=-lreadline $(COMMON_LIBS)
|
||||
|
||||
#
|
||||
# Main targets
|
||||
#
|
||||
all: $(BINDIR)/bossa$(EXE) $(BINDIR)/bossac$(EXE) $(BINDIR)/bossash$(EXE)
|
||||
|
||||
#
|
||||
# Common rules
|
||||
#
|
||||
define common_obj
|
||||
$(OBJDIR)/$(1:%.cpp=%.o): $(SRCDIR)/$(1)
|
||||
@echo CPP COMMON $$<
|
||||
$$(Q)$$(CXX) $$(COMMON_CXXFLAGS) -c -o $$@ $$<
|
||||
endef
|
||||
$(foreach src,$(COMMON_SRCS),$(eval $(call common_obj,$(src))))
|
||||
|
||||
#
|
||||
# Applet rules
|
||||
#
|
||||
define applet_obj
|
||||
$(SRCDIR)/$(1:%.asm=%.cpp): $(SRCDIR)/$(1)
|
||||
@echo APPLET $(1:%.asm=%)
|
||||
$$(Q)$$(ARMAS) -o $$(@:$(SRCDIR)/%.cpp=$(OBJDIR)/%.obj) $$<
|
||||
$$(Q)$$(ARMOBJCOPY) -O binary $$(@:$(SRCDIR)/%.cpp=$(OBJDIR)/%.obj) $$(@:$(SRCDIR)/%.cpp=$(OBJDIR)/%.bin)
|
||||
$$(Q)./appletgen $(1:%.asm=%) $(SRCDIR) $(OBJDIR)
|
||||
$(OBJDIR)/$(1:%.asm=%.o): $(SRCDIR)/$(1:%.asm=%.cpp)
|
||||
@echo CPP APPLET $$<
|
||||
$$(Q)$$(CXX) $$(COMMON_CXXFLAGS) -c -o $$(@) $$(<:%.asm=%.cpp)
|
||||
endef
|
||||
$(foreach src,$(APPLET_SRCS),$(eval $(call applet_obj,$(src))))
|
||||
|
||||
#
|
||||
# BOSSA rules
|
||||
#
|
||||
define bossa_obj
|
||||
$(OBJDIR)/$(1:%.cpp=%.o): $(SRCDIR)/$(1)
|
||||
@echo CPP BOSSA $$<
|
||||
$$(Q)$$(CXX) $$(BOSSA_CXXFLAGS) -c -o $$@ $$<
|
||||
endef
|
||||
$(foreach src,$(BOSSA_SRCS),$(eval $(call bossa_obj,$(src))))
|
||||
|
||||
#
|
||||
# Resource rules
|
||||
#
|
||||
ifeq ($(OS),MINGW32)
|
||||
$(OBJDIR)/$(BOSSA_RC:%.rc=%.o): $(RESDIR)/$(BOSSA_RC)
|
||||
@echo RC $<
|
||||
$(Q)`wx-config --rescomp --version=$(WXVERSION)` -o $@ $<
|
||||
endif
|
||||
|
||||
#
|
||||
# BOSSAC rules
|
||||
#
|
||||
define bossac_obj
|
||||
$(OBJDIR)/$(1:%.cpp=%.o): $(SRCDIR)/$(1)
|
||||
@echo CPP BOSSAC $$<
|
||||
$$(Q)$$(CXX) $$(BOSSAC_CXXFLAGS) -c -o $$@ $$<
|
||||
endef
|
||||
$(foreach src,$(BOSSAC_SRCS),$(eval $(call bossac_obj,$(src))))
|
||||
|
||||
#
|
||||
# BOSSASH rules
|
||||
#
|
||||
define bossash_obj
|
||||
$(OBJDIR)/$(1:%.cpp=%.o): $(SRCDIR)/$(1)
|
||||
@echo CPP BOSSASH $$<
|
||||
$$(Q)$$(CXX) $$(BOSSASH_CXXFLAGS) -c -o $$@ $$<
|
||||
endef
|
||||
$(foreach src,$(BOSSASH_SRCS),$(eval $(call bossash_obj,$(src))))
|
||||
|
||||
#
|
||||
# BMP rules
|
||||
#
|
||||
define bossa_bmp
|
||||
$(SRCDIR)/$(1:%.bmp=%.cpp): $(RESDIR)/$(1)
|
||||
@echo BIN2C $$<
|
||||
$(Q)bin2c $$< $$@
|
||||
endef
|
||||
$(foreach bmp,$(BOSSA_BMPS),$(eval $(call bossa_bmp,$(bmp))))
|
||||
|
||||
#
|
||||
# Directory rules
|
||||
#
|
||||
$(OBJDIR):
|
||||
@mkdir $@
|
||||
|
||||
$(BINDIR):
|
||||
@mkdir $@
|
||||
|
||||
#
|
||||
# Target rules
|
||||
#
|
||||
$(BOSSA_OBJS): | $(OBJDIR)
|
||||
$(BINDIR)/bossa$(EXE): $(foreach bmp,$(BOSSA_BMPS),$(SRCDIR)/$(bmp:%.bmp=%.cpp)) $(BOSSA_OBJS) | $(BINDIR)
|
||||
@echo LD $@
|
||||
$(Q)$(CXX) $(BOSSA_LDFLAGS) -o $@ $(BOSSA_OBJS) $(BOSSA_LIBS)
|
||||
|
||||
$(BOSSAC_OBJS): | $(OBJDIR)
|
||||
$(BINDIR)/bossac$(EXE): $(BOSSAC_OBJS) | $(BINDIR)
|
||||
@echo LD $@
|
||||
$(Q)$(CXX) $(BOSSAC_LDFLAGS) -o $@ $(BOSSAC_OBJS) $(BOSSAC_LIBS)
|
||||
|
||||
$(BOSSASH_OBJS): | $(OBJDIR)
|
||||
$(BINDIR)/bossash$(EXE): $(BOSSASH_OBJS) | $(BINDIR)
|
||||
@echo LD $@
|
||||
$(Q)$(CXX) $(BOSSASH_LDFLAGS) -o $@ $(BOSSASH_OBJS) $(BOSSASH_LIBS)
|
||||
|
||||
strip-bossa: $(BINDIR)/bossa$(EXE)
|
||||
@echo STRIP $^
|
||||
$(Q)strip $^
|
||||
|
||||
strip-bossac: $(BINDIR)/bossac$(EXE)
|
||||
@echo STRIP $^
|
||||
$(Q)strip $^
|
||||
|
||||
strip-bossash: $(BINDIR)/bossash$(EXE)
|
||||
@echo STRIP $^
|
||||
$(Q)strip $^
|
||||
|
||||
strip: strip-bossa strip-bossac strip-bossash
|
||||
|
||||
clean:
|
||||
@echo CLEAN
|
||||
$(Q)rm -rf $(BINDIR) $(OBJDIR)
|
||||
|
||||
#
|
||||
# Include dependencies
|
||||
#
|
||||
-include $(DEPENDS)
|
||||
@@ -0,0 +1,64 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#include "Applet.h"
|
||||
|
||||
Applet::Applet(Samba& samba,
|
||||
uint32_t addr,
|
||||
uint8_t* code,
|
||||
uint32_t size,
|
||||
uint32_t start,
|
||||
uint32_t stack,
|
||||
uint32_t reset) :
|
||||
_samba(samba), _addr(addr), _size(size), _start(start), _stack(stack), _reset(reset)
|
||||
{
|
||||
_samba.write(addr, code, size);
|
||||
}
|
||||
|
||||
void
|
||||
Applet::setStack(uint32_t stack)
|
||||
{
|
||||
_samba.writeWord(_stack, stack);
|
||||
}
|
||||
|
||||
void
|
||||
Applet::run()
|
||||
{
|
||||
// Add one to the start address for Thumb mode
|
||||
_samba.go(_start + 1);
|
||||
}
|
||||
|
||||
void
|
||||
Applet::runv()
|
||||
{
|
||||
// Add one to the start address for Thumb mode
|
||||
_samba.writeWord(_reset, _start + 1);
|
||||
|
||||
// The stack is the first reset vector
|
||||
_samba.go(_stack);
|
||||
}
|
||||
@@ -0,0 +1,65 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#ifndef _APPLET_H
|
||||
#define _APPLET_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "Samba.h"
|
||||
|
||||
class Applet
|
||||
{
|
||||
public:
|
||||
Applet(Samba& samba,
|
||||
uint32_t addr,
|
||||
uint8_t* code,
|
||||
uint32_t size,
|
||||
uint32_t start,
|
||||
uint32_t stack,
|
||||
uint32_t reset);
|
||||
virtual ~Applet() {}
|
||||
|
||||
virtual uint32_t size() { return _size; }
|
||||
virtual uint32_t addr() { return _addr; }
|
||||
|
||||
virtual void setStack(uint32_t stack);
|
||||
|
||||
virtual void run(); // To be used for Thumb-1 based devices (ARM7TDMI, ARM9)
|
||||
virtual void runv(); // To be used for Thumb-2 based devices (Cortex-Mx)
|
||||
|
||||
protected:
|
||||
Samba& _samba;
|
||||
uint32_t _addr; // Address in device SRAM where will be placed the applet
|
||||
uint32_t _size; // Applet size
|
||||
uint32_t _start; //
|
||||
uint32_t _stack; // Applet stack address in device SRAM
|
||||
uint32_t _reset;
|
||||
};
|
||||
|
||||
#endif // _APPLET_H
|
||||
@@ -0,0 +1,159 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#include <stdlib.h>
|
||||
#include <getopt.h>
|
||||
#include <string.h>
|
||||
#include <assert.h>
|
||||
|
||||
#include "CmdOpts.h"
|
||||
|
||||
CmdOpts::CmdOpts(int argc, char* argv[], int numOpts, Option* opts) :
|
||||
_argc(argc), _argv(argv), _numOpts(numOpts), _opts(opts)
|
||||
{
|
||||
}
|
||||
|
||||
CmdOpts::~CmdOpts()
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
CmdOpts::usage(FILE* out)
|
||||
{
|
||||
int optIdx;
|
||||
char name[40];
|
||||
const char* start;
|
||||
const char* end;
|
||||
|
||||
for (optIdx = 0; optIdx < _numOpts; optIdx++)
|
||||
{
|
||||
if (_opts[optIdx].arg.has == ArgOptional)
|
||||
snprintf(name, sizeof(name), " -%c, --%s[=%s]",
|
||||
_opts[optIdx].letter,
|
||||
_opts[optIdx].name,
|
||||
_opts[optIdx].arg.name);
|
||||
else if (_opts[optIdx].arg.has == ArgRequired)
|
||||
snprintf(name, sizeof(name), " -%c, --%s=%s",
|
||||
_opts[optIdx].letter,
|
||||
_opts[optIdx].name,
|
||||
_opts[optIdx].arg.name);
|
||||
else
|
||||
snprintf(name, sizeof(name), " -%c, --%s",
|
||||
_opts[optIdx].letter,
|
||||
_opts[optIdx].name);
|
||||
|
||||
fprintf(out, "%-23s ", name);
|
||||
|
||||
start = _opts[optIdx].help;
|
||||
while ((end = strchr(start, '\n')))
|
||||
{
|
||||
fwrite(start, end - start + 1, 1, out);
|
||||
fprintf(out, "%24s", "");
|
||||
start = end + 1;
|
||||
}
|
||||
fprintf(out, "%s\n", start);
|
||||
}
|
||||
}
|
||||
|
||||
int
|
||||
CmdOpts::parse()
|
||||
{
|
||||
struct option long_opts[_numOpts + 1];
|
||||
char optstring[_numOpts * 3 + 1];
|
||||
char* optPtr = optstring;
|
||||
int optIdx;
|
||||
int rc;
|
||||
|
||||
for (optIdx = 0; optIdx < _numOpts; optIdx++)
|
||||
{
|
||||
*_opts[optIdx].present = false;
|
||||
|
||||
*optPtr++ = _opts[optIdx].letter;
|
||||
long_opts[optIdx].name = _opts[optIdx].name;
|
||||
switch (_opts[optIdx].arg.has)
|
||||
{
|
||||
default:
|
||||
case ArgNone:
|
||||
long_opts[optIdx].has_arg = no_argument;
|
||||
break;
|
||||
case ArgOptional:
|
||||
long_opts[optIdx].has_arg = optional_argument;
|
||||
*optPtr++ = ':';
|
||||
*optPtr++ = ':';
|
||||
break;
|
||||
case ArgRequired:
|
||||
long_opts[optIdx].has_arg = required_argument;
|
||||
*optPtr++ = ':';
|
||||
break;
|
||||
}
|
||||
long_opts[optIdx].flag = NULL;
|
||||
long_opts[optIdx].val = 0;
|
||||
}
|
||||
|
||||
memset(&long_opts[_numOpts], 0, sizeof(long_opts[_numOpts]));
|
||||
*optPtr = '\0';
|
||||
optIdx = 0;
|
||||
while ((rc = getopt_long(_argc, _argv, optstring, long_opts, &optIdx)) != -1)
|
||||
{
|
||||
if (rc == '?')
|
||||
return -1;
|
||||
|
||||
if (rc != 0)
|
||||
optIdx = find(rc);
|
||||
|
||||
assert(optIdx >= 0 && optIdx < _numOpts);
|
||||
*_opts[optIdx].present = true;
|
||||
if (_opts[optIdx].arg.has != ArgNone && optarg)
|
||||
{
|
||||
switch (_opts[optIdx].arg.type)
|
||||
{
|
||||
case ArgInt:
|
||||
*_opts[optIdx].arg.value.intPtr = strtol(optarg, NULL, 0);
|
||||
break;
|
||||
default:
|
||||
case ArgString:
|
||||
*_opts[optIdx].arg.value.strPtr = optarg;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return optind;
|
||||
}
|
||||
|
||||
int
|
||||
CmdOpts::find(char letter)
|
||||
{
|
||||
int optIdx;
|
||||
|
||||
for (optIdx = 0; optIdx < _numOpts; optIdx++)
|
||||
if (_opts[optIdx].letter == letter)
|
||||
break;
|
||||
|
||||
return optIdx;
|
||||
}
|
||||
@@ -0,0 +1,88 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#ifndef _OPTION_H
|
||||
#define _OPTION_H
|
||||
|
||||
#include <string>
|
||||
#include <stdio.h>
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ArgNone,
|
||||
ArgOptional,
|
||||
ArgRequired
|
||||
} ArgHas;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
ArgInt,
|
||||
ArgString
|
||||
} ArgType;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
ArgHas has;
|
||||
ArgType type;
|
||||
const char* name;
|
||||
union
|
||||
{
|
||||
void* voidPtr;
|
||||
int* intPtr;
|
||||
std::string* strPtr;
|
||||
} value;
|
||||
} OptArg;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
char letter;
|
||||
const char* name;
|
||||
bool* present;
|
||||
OptArg arg;
|
||||
const char* help;
|
||||
} Option;
|
||||
|
||||
class CmdOpts
|
||||
{
|
||||
public:
|
||||
CmdOpts(int argc, char* argv[], int numOpts, Option* opts);
|
||||
virtual ~CmdOpts();
|
||||
|
||||
void usage(FILE* out);
|
||||
int parse();
|
||||
|
||||
private:
|
||||
int _argc;
|
||||
char** _argv;
|
||||
int _numOpts;
|
||||
Option* _opts;
|
||||
|
||||
int find(char letter);
|
||||
};
|
||||
|
||||
#endif // _OPTION_H
|
||||
@@ -0,0 +1,347 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2018, ShumaTech
|
||||
//
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include "D2xNvmFlash.h"
|
||||
|
||||
// CMDEX field should be 0xA5 to allow execution of any command.
|
||||
#define CMDEX_KEY 0xa500
|
||||
|
||||
// NVM ready bit mask
|
||||
#define NVM_INT_STATUS_READY_MASK 0x1
|
||||
|
||||
// NVM status mask
|
||||
#define NVM_CTRL_STATUS_MASK 0xFFEB
|
||||
|
||||
#define NVM_REG_BASE 0x41004000
|
||||
|
||||
#define NVM_REG_CTRLA 0x00
|
||||
#define NVM_REG_CTRLB 0x04
|
||||
#define NVM_REG_INTFLAG 0x14
|
||||
#define NVM_REG_STATUS 0x18
|
||||
#define NVM_REG_ADDR 0x1c
|
||||
#define NVM_REG_LOCK 0x20
|
||||
|
||||
#define NVM_CMD_ER 0x02
|
||||
#define NVM_CMD_WP 0x04
|
||||
#define NVM_CMD_EAR 0x05
|
||||
#define NVM_CMD_WAP 0x06
|
||||
#define NVM_CMD_LR 0x40
|
||||
#define NVM_CMD_UR 0x41
|
||||
#define NVM_CMD_SSB 0x45
|
||||
#define NVM_CMD_PBC 0x44
|
||||
|
||||
#define ERASE_ROW_PAGES 4 // pages
|
||||
|
||||
// NVM User Row
|
||||
#define NVM_UR_ADDR 0x804000
|
||||
#define NVM_UR_SIZE (_size * ERASE_ROW_PAGES)
|
||||
#define NVM_UR_BOD33_ENABLE_OFFSET 0x1
|
||||
#define NVM_UR_BOD33_ENABLE_MASK 0x6
|
||||
#define NVM_UR_BOD33_RESET_OFFSET 0x1
|
||||
#define NVM_UR_BOD33_RESET_MASK 0x7
|
||||
#define NVM_UR_NVM_LOCK_OFFSET 0x6
|
||||
|
||||
D2xNvmFlash::D2xNvmFlash(
|
||||
Samba& samba,
|
||||
const std::string& name,
|
||||
uint32_t pages,
|
||||
uint32_t size,
|
||||
uint32_t user,
|
||||
uint32_t stack)
|
||||
:
|
||||
Flash(samba, name, 0, pages, size, 1, 16, user, stack), _eraseAuto(true)
|
||||
{
|
||||
}
|
||||
|
||||
D2xNvmFlash::~D2xNvmFlash()
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
D2xNvmFlash::erase(uint32_t offset, uint32_t size)
|
||||
{
|
||||
uint32_t eraseSize = _size * ERASE_ROW_PAGES;
|
||||
|
||||
// Offset must be a multiple of the erase size
|
||||
if (offset % eraseSize)
|
||||
throw FlashEraseError();
|
||||
|
||||
// Offset and size must be in range
|
||||
if (offset + size > totalSize())
|
||||
throw FlashEraseError();
|
||||
|
||||
uint32_t eraseEnd = (offset + size + eraseSize - 1) / eraseSize;
|
||||
|
||||
// Erase each erase size set of pages
|
||||
for (uint32_t eraseNum = offset / eraseSize; eraseNum < eraseEnd; eraseNum++)
|
||||
{
|
||||
waitReady();
|
||||
|
||||
// Clear error bits
|
||||
uint16_t statusReg = readReg(NVM_REG_STATUS);
|
||||
writeReg(NVM_REG_STATUS, statusReg | NVM_CTRL_STATUS_MASK);
|
||||
|
||||
// Issue erase command
|
||||
uint32_t wordAddr = (eraseNum * eraseSize) / 2;
|
||||
writeReg(NVM_REG_ADDR, wordAddr);
|
||||
command(NVM_CMD_ER);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
D2xNvmFlash::eraseAll(uint32_t offset)
|
||||
{
|
||||
// Use the extended Samba command if available
|
||||
if (_samba.canChipErase())
|
||||
{
|
||||
_samba.chipErase(offset);
|
||||
}
|
||||
else
|
||||
{
|
||||
erase(offset, totalSize() - offset);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
D2xNvmFlash::eraseAuto(bool enable)
|
||||
{
|
||||
_eraseAuto = enable;
|
||||
}
|
||||
|
||||
std::vector<bool>
|
||||
D2xNvmFlash::getLockRegions()
|
||||
{
|
||||
uint8_t lockBits = 0;
|
||||
uint32_t addr = NVM_UR_ADDR + NVM_UR_NVM_LOCK_OFFSET;
|
||||
std::vector<bool> regions(_lockRegions);
|
||||
|
||||
for (uint32_t region = 0; region < _lockRegions; region++)
|
||||
{
|
||||
if (region % 8 == 0)
|
||||
lockBits = _samba.readByte(addr++);
|
||||
regions[region] = (lockBits & (1 << (region % 8))) == 0;
|
||||
}
|
||||
|
||||
return regions;
|
||||
}
|
||||
|
||||
bool
|
||||
D2xNvmFlash::getSecurity()
|
||||
{
|
||||
return (readReg(NVM_REG_STATUS) & 0x100) != 0;
|
||||
}
|
||||
|
||||
bool
|
||||
D2xNvmFlash::getBod()
|
||||
{
|
||||
uint8_t byte = _samba.readByte(NVM_UR_ADDR + NVM_UR_BOD33_ENABLE_OFFSET);
|
||||
|
||||
return (byte & NVM_UR_BOD33_ENABLE_MASK) != 0;
|
||||
}
|
||||
|
||||
bool
|
||||
D2xNvmFlash::getBor()
|
||||
{
|
||||
uint8_t byte = _samba.readByte(NVM_UR_ADDR + NVM_UR_BOD33_RESET_OFFSET);
|
||||
|
||||
return (byte & NVM_UR_BOD33_RESET_MASK) != 0;
|
||||
}
|
||||
|
||||
bool
|
||||
D2xNvmFlash::getBootFlash()
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
void
|
||||
D2xNvmFlash::readUserRow(std::unique_ptr<uint8_t[]>& userRow)
|
||||
{
|
||||
if (!userRow)
|
||||
{
|
||||
userRow.reset(new uint8_t[NVM_UR_SIZE]);
|
||||
_samba.read(NVM_UR_ADDR, userRow.get(), NVM_UR_SIZE);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
D2xNvmFlash::writeOptions()
|
||||
{
|
||||
std::unique_ptr<uint8_t[]> userRow;
|
||||
|
||||
if (canBor() && _bor.isDirty() && _bor.get() != getBor())
|
||||
{
|
||||
readUserRow(userRow);
|
||||
if (_bor.get())
|
||||
userRow[NVM_UR_BOD33_RESET_OFFSET] |= NVM_UR_BOD33_RESET_MASK;
|
||||
else
|
||||
userRow[NVM_UR_BOD33_RESET_OFFSET] &= ~NVM_UR_BOD33_RESET_MASK;
|
||||
}
|
||||
if (canBod() && _bod.isDirty() && _bod.get() != getBod())
|
||||
{
|
||||
readUserRow(userRow);
|
||||
if (_bod.get())
|
||||
userRow[NVM_UR_BOD33_ENABLE_OFFSET] |= NVM_UR_BOD33_ENABLE_MASK;
|
||||
else
|
||||
userRow[NVM_UR_BOD33_ENABLE_OFFSET] &= ~NVM_UR_BOD33_ENABLE_MASK;
|
||||
}
|
||||
if (_regions.isDirty())
|
||||
{
|
||||
// Check if any lock bits are different from the current set
|
||||
std::vector<bool> current = getLockRegions();
|
||||
if (!equal(_regions.get().begin(), _regions.get().end(), current.begin()))
|
||||
{
|
||||
readUserRow(userRow);
|
||||
|
||||
uint8_t* lockBits = &userRow[NVM_UR_NVM_LOCK_OFFSET];
|
||||
for (uint32_t region = 0; region < _regions.get().size(); region++)
|
||||
{
|
||||
if (_regions.get()[region])
|
||||
lockBits[region / 8] &= ~(1 << (region % 8));
|
||||
else
|
||||
lockBits[region / 8] |= (1 << (region % 8));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Erase and write the user row if modified
|
||||
if (userRow)
|
||||
{
|
||||
// Disable cache and configure manual page write
|
||||
writeReg(NVM_REG_CTRLB, readReg(NVM_REG_CTRLB) | (0x1 << 18) | (0x1 << 7));
|
||||
|
||||
// Erase user row
|
||||
writeReg(NVM_REG_ADDR, NVM_UR_ADDR / 2);
|
||||
command(NVM_CMD_EAR);
|
||||
|
||||
// Write user row in page chunks
|
||||
for (uint32_t offset = 0; offset < NVM_UR_SIZE; offset += _size)
|
||||
{
|
||||
// Load the buffer with the page
|
||||
loadBuffer(&userRow[offset], _size);
|
||||
|
||||
// Clear page buffer
|
||||
command(NVM_CMD_PBC);
|
||||
|
||||
// Copy page to page buffer
|
||||
_wordCopy.setDstAddr(NVM_UR_ADDR + offset);
|
||||
_wordCopy.setSrcAddr(_onBufferA ? _pageBufferA : _pageBufferB);
|
||||
_onBufferA = !_onBufferA;
|
||||
waitReady();
|
||||
_wordCopy.runv();
|
||||
|
||||
// Write the page
|
||||
writeReg(NVM_REG_ADDR, (NVM_UR_ADDR + offset) / 2);
|
||||
command(NVM_CMD_WAP);
|
||||
}
|
||||
}
|
||||
|
||||
// Always do security last
|
||||
if (_security.isDirty() && _security.get() == true && _security.get() != getSecurity())
|
||||
{
|
||||
command(NVM_CMD_SSB);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
D2xNvmFlash::writePage(uint32_t page)
|
||||
{
|
||||
if (page >= _pages)
|
||||
{
|
||||
throw FlashPageError();
|
||||
}
|
||||
|
||||
// Disable cache and configure manual page write
|
||||
writeReg(NVM_REG_CTRLB, readReg(NVM_REG_CTRLB) | (0x1 << 18) | (0x1 << 7));
|
||||
|
||||
// Auto-erase if writing at the start of the erase page
|
||||
if (_eraseAuto && page % ERASE_ROW_PAGES == 0)
|
||||
erase(page * _size, ERASE_ROW_PAGES * _size);
|
||||
|
||||
// Clear page buffer
|
||||
command(NVM_CMD_PBC);
|
||||
|
||||
// Compute the start address.
|
||||
uint32_t addr = _addr + (page * _size);
|
||||
|
||||
_wordCopy.setDstAddr(addr);
|
||||
_wordCopy.setSrcAddr(_onBufferA ? _pageBufferA : _pageBufferB);
|
||||
_onBufferA = !_onBufferA;
|
||||
waitReady();
|
||||
_wordCopy.runv();
|
||||
|
||||
writeReg(NVM_REG_ADDR, addr / 2);
|
||||
command(NVM_CMD_WP);
|
||||
}
|
||||
|
||||
void
|
||||
D2xNvmFlash::waitReady()
|
||||
{
|
||||
while ((readReg(NVM_REG_INTFLAG) & 0x1) == 0);
|
||||
}
|
||||
|
||||
void
|
||||
D2xNvmFlash::readPage(uint32_t page, uint8_t* buf)
|
||||
{
|
||||
if (page >= _pages)
|
||||
{
|
||||
throw FlashPageError();
|
||||
}
|
||||
|
||||
_samba.read(_addr + (page * _size), buf, _size);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
D2xNvmFlash::readReg(uint8_t reg)
|
||||
{
|
||||
return _samba.readWord(NVM_REG_BASE + reg);
|
||||
}
|
||||
|
||||
void
|
||||
D2xNvmFlash::writeReg(uint8_t reg, uint32_t value)
|
||||
{
|
||||
_samba.writeWord(NVM_REG_BASE + reg, value);
|
||||
}
|
||||
|
||||
void
|
||||
D2xNvmFlash::command(uint8_t cmd)
|
||||
{
|
||||
waitReady();
|
||||
|
||||
writeReg(NVM_REG_CTRLA, CMDEX_KEY | cmd);
|
||||
|
||||
waitReady();
|
||||
|
||||
if (readReg(NVM_REG_INTFLAG) & 0x2)
|
||||
{
|
||||
// Clear the error bit
|
||||
writeReg(NVM_REG_INTFLAG, 0x2);
|
||||
throw FlashCmdError();
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
D2xNvmFlash::writeBuffer(uint32_t dst_addr, uint32_t size)
|
||||
{
|
||||
// Auto-erase if enabled
|
||||
if (_eraseAuto)
|
||||
erase(dst_addr, size);
|
||||
|
||||
// Call the base class method
|
||||
Flash::writeBuffer(dst_addr, size);
|
||||
}
|
||||
@@ -0,0 +1,76 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2018, ShumaTech
|
||||
//
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef _D2XNVMFLASH_H
|
||||
#define _D2XNVMFLASH_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <exception>
|
||||
|
||||
#include "Flash.h"
|
||||
|
||||
class D2xNvmFlash : public Flash
|
||||
{
|
||||
public:
|
||||
D2xNvmFlash(
|
||||
Samba& samba,
|
||||
const std::string& name,
|
||||
uint32_t pages,
|
||||
uint32_t size,
|
||||
uint32_t user,
|
||||
uint32_t stack);
|
||||
|
||||
virtual ~D2xNvmFlash();
|
||||
|
||||
void eraseAll(uint32_t offset);
|
||||
void eraseAuto(bool enable);
|
||||
|
||||
std::vector<bool> getLockRegions();
|
||||
|
||||
bool getSecurity();
|
||||
|
||||
bool getBod();
|
||||
bool canBod() { return true; }
|
||||
|
||||
bool getBor();
|
||||
bool canBor() { return true; }
|
||||
|
||||
bool getBootFlash();
|
||||
bool canBootFlash() { return false; }
|
||||
|
||||
void writeOptions();
|
||||
|
||||
void writePage(uint32_t page);
|
||||
void readPage(uint32_t page, uint8_t* data);
|
||||
|
||||
void writeBuffer(uint32_t dst_addr, uint32_t size);
|
||||
|
||||
protected:
|
||||
bool _eraseAuto;
|
||||
|
||||
uint32_t readReg(uint8_t reg);
|
||||
void writeReg(uint8_t reg, uint32_t value);
|
||||
|
||||
void waitReady();
|
||||
void command(uint8_t cmd);
|
||||
void erase(uint32_t offset, uint32_t size);
|
||||
void readUserRow(std::unique_ptr<uint8_t[]>& userRow);
|
||||
};
|
||||
|
||||
#endif // _D2XNVMFLASH_H
|
||||
@@ -0,0 +1,352 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2018, ShumaTech
|
||||
//
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#include "D5xNvmFlash.h"
|
||||
|
||||
|
||||
#define CMDEX_KEY 0xa500
|
||||
|
||||
#define NVM_REG_BASE 0x41004000
|
||||
|
||||
#define NVM_REG_CTRLA 0x00
|
||||
#define NVM_REG_CTRLB 0x04
|
||||
#define NVM_REG_INTFLAG 0x10
|
||||
#define NVM_REG_STATUS 0x12
|
||||
#define NVM_REG_ADDR 0x14
|
||||
#define NVM_REG_RUNLOCK 0x18
|
||||
|
||||
#define NVM_CMD_EP 0x00
|
||||
#define NVM_CMD_EB 0x01
|
||||
#define NVM_CMD_WP 0x03
|
||||
#define NVM_CMD_WQW 0x04
|
||||
#define NVM_CMD_LR 0x11
|
||||
#define NVM_CMD_UR 0x12
|
||||
#define NVM_CMD_SSB 0x16
|
||||
#define NVM_CMD_PBC 0x15
|
||||
|
||||
#define ERASE_BLOCK_PAGES 16 // pages
|
||||
|
||||
// NVM User Page
|
||||
#define NVM_UP_ADDR 0x804000
|
||||
#define NVM_UP_SIZE (_size)
|
||||
#define NVM_UP_BOD33_DISABLE_OFFSET 0x0
|
||||
#define NVM_UP_BOD33_DISABLE_MASK 0x1
|
||||
#define NVM_UP_BOD33_RESET_OFFSET 0x1
|
||||
#define NVM_UP_BOD33_RESET_MASK 0x2
|
||||
#define NVM_UP_NVM_LOCK_OFFSET 0x8
|
||||
|
||||
D5xNvmFlash::D5xNvmFlash(
|
||||
Samba& samba,
|
||||
const std::string& name,
|
||||
uint32_t pages,
|
||||
uint32_t size,
|
||||
uint32_t user,
|
||||
uint32_t stack)
|
||||
:
|
||||
Flash(samba, name, 0, pages, size, 1, 32, user, stack), _eraseAuto(true)
|
||||
{
|
||||
}
|
||||
|
||||
D5xNvmFlash::~D5xNvmFlash()
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
D5xNvmFlash::erase(uint32_t offset, uint32_t size)
|
||||
{
|
||||
uint32_t eraseSize = _size * ERASE_BLOCK_PAGES;
|
||||
|
||||
// Offset must be a multiple of the erase size
|
||||
if (offset % eraseSize)
|
||||
throw FlashEraseError();
|
||||
|
||||
// Offset and size must be in range
|
||||
if (offset + size > totalSize())
|
||||
throw FlashEraseError();
|
||||
|
||||
uint32_t eraseEnd = (offset + size + eraseSize - 1) / eraseSize;
|
||||
|
||||
// Erase each erase size set of pages
|
||||
for (uint32_t eraseNum = offset / eraseSize; eraseNum < eraseEnd; eraseNum++)
|
||||
{
|
||||
// Issue erase command
|
||||
writeRegU32(NVM_REG_ADDR, eraseNum * eraseSize);
|
||||
command(NVM_CMD_EB);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
D5xNvmFlash::eraseAll(uint32_t offset)
|
||||
{
|
||||
// Use the extended Samba command if available
|
||||
if (_samba.canChipErase())
|
||||
{
|
||||
_samba.chipErase(offset);
|
||||
}
|
||||
else
|
||||
{
|
||||
erase(offset, totalSize() - offset);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
D5xNvmFlash::waitReady()
|
||||
{
|
||||
while ((readRegU16(NVM_REG_STATUS) & 0x1) == 0);
|
||||
}
|
||||
|
||||
void
|
||||
D5xNvmFlash::eraseAuto(bool enable)
|
||||
{
|
||||
_eraseAuto = enable;
|
||||
}
|
||||
|
||||
std::vector<bool>
|
||||
D5xNvmFlash::getLockRegions()
|
||||
{
|
||||
uint8_t lockBits = 0;
|
||||
uint32_t addr = NVM_UP_ADDR + NVM_UP_NVM_LOCK_OFFSET;
|
||||
std::vector<bool> regions(_lockRegions);
|
||||
|
||||
for (uint32_t region = 0; region < _lockRegions; region++)
|
||||
{
|
||||
if (region % 8 == 0)
|
||||
lockBits = _samba.readByte(addr++);
|
||||
regions[region] = (lockBits & (1 << (region % 8))) == 0;
|
||||
}
|
||||
|
||||
return regions;
|
||||
}
|
||||
|
||||
bool
|
||||
D5xNvmFlash::getSecurity()
|
||||
{
|
||||
// There doesn't seem to be a way to read this
|
||||
return false;
|
||||
}
|
||||
|
||||
bool
|
||||
D5xNvmFlash::getBod()
|
||||
{
|
||||
uint8_t byte = _samba.readByte(NVM_UP_ADDR + NVM_UP_BOD33_DISABLE_OFFSET);
|
||||
|
||||
return (byte & NVM_UP_BOD33_DISABLE_MASK) == 0;
|
||||
}
|
||||
|
||||
bool
|
||||
D5xNvmFlash::getBor()
|
||||
{
|
||||
uint8_t byte = _samba.readByte(NVM_UP_ADDR + NVM_UP_BOD33_RESET_OFFSET);
|
||||
|
||||
return (byte & NVM_UP_BOD33_RESET_MASK) != 0;
|
||||
}
|
||||
|
||||
bool
|
||||
D5xNvmFlash::getBootFlash()
|
||||
{
|
||||
return true;
|
||||
}
|
||||
|
||||
void
|
||||
D5xNvmFlash::readUserPage(std::unique_ptr<uint8_t[]>& userPage)
|
||||
{
|
||||
if (!userPage)
|
||||
{
|
||||
userPage.reset(new uint8_t[NVM_UP_SIZE]);
|
||||
_samba.read(NVM_UP_ADDR, userPage.get(), NVM_UP_SIZE);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
D5xNvmFlash::writeOptions()
|
||||
{
|
||||
std::unique_ptr<uint8_t[]> userPage;
|
||||
|
||||
if (canBor() && _bor.isDirty() && _bor.get() != getBor())
|
||||
{
|
||||
readUserPage(userPage);
|
||||
if (_bor.get())
|
||||
userPage[NVM_UP_BOD33_RESET_OFFSET] |= NVM_UP_BOD33_RESET_MASK;
|
||||
else
|
||||
userPage[NVM_UP_BOD33_RESET_OFFSET] &= ~NVM_UP_BOD33_RESET_MASK;
|
||||
}
|
||||
if (canBod() && _bod.isDirty() && _bod.get() != getBod())
|
||||
{
|
||||
readUserPage(userPage);
|
||||
if (_bod.get())
|
||||
userPage[NVM_UP_BOD33_DISABLE_OFFSET] &= ~NVM_UP_BOD33_DISABLE_MASK;
|
||||
else
|
||||
userPage[NVM_UP_BOD33_DISABLE_OFFSET] |= NVM_UP_BOD33_DISABLE_MASK;
|
||||
}
|
||||
if (_regions.isDirty())
|
||||
{
|
||||
// Check if any lock bits are different from the current set
|
||||
std::vector<bool> current = getLockRegions();
|
||||
if (!equal(_regions.get().begin(), _regions.get().end(), current.begin()))
|
||||
{
|
||||
readUserPage(userPage);
|
||||
|
||||
uint8_t* lockBits = &userPage[NVM_UP_NVM_LOCK_OFFSET];
|
||||
for (uint32_t region = 0; region < _regions.get().size(); region++)
|
||||
{
|
||||
if (_regions.get()[region])
|
||||
lockBits[region / 8] &= ~(1 << (region % 8));
|
||||
else
|
||||
lockBits[region / 8] |= (1 << (region % 8));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Erase and write the user page if modified
|
||||
if (userPage)
|
||||
{
|
||||
// Configure manual page write and disable caches
|
||||
writeRegU16(NVM_REG_CTRLA, (readRegU16(NVM_REG_CTRLA) | (0x3 << 14)) & 0xffcf);
|
||||
|
||||
// Erase user page
|
||||
writeRegU32(NVM_REG_ADDR, NVM_UP_ADDR);
|
||||
command(NVM_CMD_EP);
|
||||
|
||||
// Write user page in quad-word chunks
|
||||
for (uint32_t offset = 0; offset < NVM_UP_SIZE; offset += 16)
|
||||
{
|
||||
// Load the buffer with the quad word
|
||||
loadBuffer(&userPage[offset], 16);
|
||||
|
||||
// Clear page buffer
|
||||
command(NVM_CMD_PBC);
|
||||
|
||||
// Copy quad word to page buffer
|
||||
_wordCopy.setDstAddr(NVM_UP_ADDR + offset);
|
||||
_wordCopy.setSrcAddr(_onBufferA ? _pageBufferA : _pageBufferB);
|
||||
_wordCopy.setWords(4);
|
||||
_onBufferA = !_onBufferA;
|
||||
waitReady();
|
||||
_wordCopy.runv();
|
||||
|
||||
// Write the quad word
|
||||
writeRegU32(NVM_REG_ADDR, NVM_UP_ADDR + offset);
|
||||
command(NVM_CMD_WQW);
|
||||
}
|
||||
}
|
||||
|
||||
// Always do security last
|
||||
if (_security.isDirty() && _security.get() == true && _security.get() != getSecurity())
|
||||
{
|
||||
command(NVM_CMD_SSB);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
D5xNvmFlash::writePage(uint32_t page)
|
||||
{
|
||||
if (page >= _pages)
|
||||
{
|
||||
throw FlashPageError();
|
||||
}
|
||||
|
||||
// Configure manual page write and disable caches
|
||||
writeRegU16(NVM_REG_CTRLA, (readRegU16(NVM_REG_CTRLA) | (0x3 << 14)) & 0xffcf);
|
||||
|
||||
// Auto-erase if writing at the start of the erase page
|
||||
if (_eraseAuto && page % ERASE_BLOCK_PAGES == 0)
|
||||
{
|
||||
erase(page * _size, ERASE_BLOCK_PAGES * _size);
|
||||
}
|
||||
|
||||
// Clear page bur
|
||||
command(NVM_CMD_PBC);
|
||||
|
||||
uint32_t addr = _addr + (page * _size );
|
||||
|
||||
_wordCopy.setDstAddr(addr);
|
||||
_wordCopy.setSrcAddr(_onBufferA ? _pageBufferA : _pageBufferB);
|
||||
_wordCopy.setWords(_size / sizeof(uint32_t));
|
||||
_onBufferA = !_onBufferA;
|
||||
waitReady();
|
||||
_wordCopy.runv();
|
||||
|
||||
writeRegU32(NVM_REG_ADDR, addr);
|
||||
command(NVM_CMD_WP);
|
||||
}
|
||||
|
||||
void
|
||||
D5xNvmFlash::readPage(uint32_t page, uint8_t* buf)
|
||||
{
|
||||
if (page >= _pages)
|
||||
{
|
||||
throw FlashPageError();
|
||||
}
|
||||
|
||||
_samba.read(_addr + (page * _size), buf, _size);
|
||||
}
|
||||
|
||||
uint16_t
|
||||
D5xNvmFlash::readRegU16(uint8_t reg)
|
||||
{
|
||||
return (uint16_t) _samba.readByte(NVM_REG_BASE + reg) |
|
||||
(_samba.readByte(NVM_REG_BASE + reg + 1) << 8);
|
||||
}
|
||||
|
||||
void
|
||||
D5xNvmFlash::writeRegU16(uint8_t reg, uint16_t value)
|
||||
{
|
||||
_samba.writeByte(NVM_REG_BASE + reg, value & 0xff);
|
||||
_samba.writeByte(NVM_REG_BASE + reg + 1, value >> 8);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
D5xNvmFlash::readRegU32(uint8_t reg)
|
||||
{
|
||||
return _samba.readWord(NVM_REG_BASE + reg);
|
||||
}
|
||||
|
||||
void
|
||||
D5xNvmFlash::writeRegU32(uint8_t reg, uint32_t value)
|
||||
{
|
||||
_samba.writeWord(NVM_REG_BASE + reg, value);
|
||||
}
|
||||
|
||||
void
|
||||
D5xNvmFlash::command(uint8_t cmd)
|
||||
{
|
||||
waitReady();
|
||||
|
||||
writeRegU32(NVM_REG_CTRLB, CMDEX_KEY | cmd);
|
||||
|
||||
waitReady();
|
||||
|
||||
if (readRegU16(NVM_REG_INTFLAG) & 0xce)
|
||||
{
|
||||
// Clear the error bits
|
||||
writeRegU16(NVM_REG_INTFLAG, 0xce);
|
||||
throw FlashCmdError();
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
D5xNvmFlash::writeBuffer(uint32_t dst_addr, uint32_t size)
|
||||
{
|
||||
// Auto-erase if writing at the start of the erase page
|
||||
if (_eraseAuto && ((dst_addr / _size) % ERASE_BLOCK_PAGES == 0))
|
||||
erase(dst_addr, size);
|
||||
|
||||
// Call the base class method
|
||||
Flash::writeBuffer(dst_addr, size);
|
||||
}
|
||||
@@ -0,0 +1,79 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2018, ShumaTech
|
||||
//
|
||||
// This program is free software: you can redistribute it and/or modify
|
||||
// it under the terms of the GNU General Public License as published by
|
||||
// the Free Software Foundation, either version 3 of the License, or
|
||||
// (at your option) any later version.
|
||||
//
|
||||
// This program is distributed in the hope that it will be useful,
|
||||
// but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
// GNU General Public License for more details.
|
||||
//
|
||||
// You should have received a copy of the GNU General Public License
|
||||
// along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef _D5XNVMFLASH_H
|
||||
#define _D5XNVMFLASH_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <exception>
|
||||
|
||||
#include "Flash.h"
|
||||
|
||||
class D5xNvmFlash : public Flash
|
||||
{
|
||||
public:
|
||||
D5xNvmFlash(
|
||||
Samba& samba,
|
||||
const std::string& name,
|
||||
uint32_t pages,
|
||||
uint32_t size,
|
||||
uint32_t user,
|
||||
uint32_t stack);
|
||||
|
||||
virtual ~D5xNvmFlash();
|
||||
|
||||
void eraseAll(uint32_t offset);
|
||||
void eraseAuto(bool enable);
|
||||
|
||||
std::vector<bool> getLockRegions();
|
||||
|
||||
bool getSecurity();
|
||||
|
||||
bool getBod();
|
||||
bool canBod() { return true; }
|
||||
|
||||
bool getBor();
|
||||
bool canBor() { return true; }
|
||||
|
||||
bool getBootFlash();
|
||||
bool canBootFlash() { return false; }
|
||||
|
||||
void writeOptions();
|
||||
|
||||
void writePage(uint32_t page);
|
||||
void readPage(uint32_t page, uint8_t* data);
|
||||
|
||||
void writeBuffer(uint32_t dst_addr, uint32_t size);
|
||||
|
||||
protected:
|
||||
bool _eraseAuto;
|
||||
|
||||
uint16_t readRegU16(uint8_t reg);
|
||||
void writeRegU16(uint8_t reg, uint16_t value);
|
||||
uint32_t readRegU32(uint8_t reg);
|
||||
void writeRegU32(uint8_t reg, uint32_t value);
|
||||
|
||||
void waitReady();
|
||||
void command(uint8_t cmd);
|
||||
void erase(uint32_t offset, uint32_t size);
|
||||
void checkError();
|
||||
void readUserPage(std::unique_ptr<uint8_t[]>& userPage);
|
||||
};
|
||||
|
||||
#endif // _D5XNVMFLASH_H
|
||||
@@ -0,0 +1,692 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#include "Device.h"
|
||||
#include "EfcFlash.h"
|
||||
#include "EefcFlash.h"
|
||||
#include "D2xNvmFlash.h"
|
||||
#include "D5xNvmFlash.h"
|
||||
|
||||
void
|
||||
Device::readChipId(uint32_t& chipId, uint32_t& extChipId)
|
||||
{
|
||||
if ((chipId = _samba.readWord(0x400e0740)) != 0)
|
||||
{
|
||||
extChipId = _samba.readWord(0x400e0744);
|
||||
}
|
||||
else if ((chipId = _samba.readWord(0x400e0940)) != 0)
|
||||
{
|
||||
extChipId = _samba.readWord(0x400e0944);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
Device::create()
|
||||
{
|
||||
Flash* flashPtr;
|
||||
uint32_t chipId = 0;
|
||||
uint32_t cpuId = 0;
|
||||
uint32_t extChipId = 0;
|
||||
uint32_t deviceId = 0;
|
||||
|
||||
// Device identification must be performed carefully to avoid reading from
|
||||
// addresses that devices do not support which will lock up the CPU
|
||||
|
||||
// All devices support addresss 0 as the ARM reset vector so if the vector is
|
||||
// a ARM7TDMI branch, then assume we have an Atmel SAM7/9 CHIPID register
|
||||
if ((_samba.readWord(0x0) & 0xff000000) == 0xea000000)
|
||||
{
|
||||
chipId = _samba.readWord(0xfffff240);
|
||||
}
|
||||
else
|
||||
{
|
||||
// Next try the ARM CPUID register since all Cortex-M devices support it
|
||||
cpuId = _samba.readWord(0xe000ed00) & 0x0000fff0;
|
||||
|
||||
// Cortex-M0+
|
||||
if (cpuId == 0xC600)
|
||||
{
|
||||
// These should support the ARM device ID register
|
||||
deviceId = _samba.readWord(0x41002018);
|
||||
}
|
||||
// Cortex-M4
|
||||
else if (cpuId == 0xC240)
|
||||
{
|
||||
// SAM4 processors have a reset vector to the SAM-BA ROM
|
||||
if ((_samba.readWord(0x4) & 0xfff00000) == 0x800000)
|
||||
{
|
||||
readChipId(chipId, extChipId);
|
||||
}
|
||||
// Else we should have a device that supports the ARM device ID register
|
||||
else
|
||||
{
|
||||
deviceId = _samba.readWord(0x41002018);
|
||||
}
|
||||
}
|
||||
// For all other Cortex versions try the Atmel chip ID registers
|
||||
else
|
||||
{
|
||||
readChipId(chipId, extChipId);
|
||||
}
|
||||
}
|
||||
|
||||
// Instantiate the proper flash for the device
|
||||
switch (chipId & 0x7fffffe0)
|
||||
{
|
||||
//
|
||||
// SAM7SE
|
||||
//
|
||||
case 0x272a0a40:
|
||||
_family = FAMILY_SAM7SE;
|
||||
flashPtr = new EfcFlash(_samba, "AT91SAM7SE512", 0x100000, 2048, 256, 2, 32, 0x202000, 0x208000, true);
|
||||
break;
|
||||
case 0x272a0940:
|
||||
_family = FAMILY_SAM7SE;
|
||||
flashPtr = new EfcFlash(_samba, "AT91SAM7SE256", 0x100000, 1024, 256, 1, 16, 0x202000, 0x208000, true);
|
||||
break;
|
||||
case 0x272a0340:
|
||||
_family = FAMILY_SAM7SE;
|
||||
flashPtr = new EfcFlash(_samba, "AT91SAM7SE32", 0x100000, 256, 128, 1, 8, 0x201400, 0x201C00, true);
|
||||
break;
|
||||
//
|
||||
// SAM7S
|
||||
//
|
||||
case 0x270b0a40:
|
||||
_family = FAMILY_SAM7S;
|
||||
flashPtr = new EfcFlash(_samba, "AT91SAM7S512", 0x100000, 2048, 256, 2, 32, 0x202000, 0x210000, false);
|
||||
break;
|
||||
case 0x270d0940: // A
|
||||
case 0x270b0940: // B/C
|
||||
_family = FAMILY_SAM7S;
|
||||
flashPtr = new EfcFlash(_samba, "AT91SAM7S256", 0x100000, 1024, 256, 1, 16, 0x202000, 0x210000, false);
|
||||
break;
|
||||
case 0x270c0740: // A
|
||||
case 0x270a0740: // B/C
|
||||
_family = FAMILY_SAM7S;
|
||||
flashPtr = new EfcFlash(_samba, "AT91SAM7S128", 0x100000, 512, 256, 1, 8, 0x202000, 0x208000, false);
|
||||
break;
|
||||
case 0x27090540:
|
||||
_family = FAMILY_SAM7S;
|
||||
flashPtr = new EfcFlash(_samba, "AT91SAM7S64", 0x100000, 512, 128, 1, 16, 0x202000, 0x204000, false);
|
||||
break;
|
||||
case 0x27080340:
|
||||
_family = FAMILY_SAM7S;
|
||||
flashPtr = new EfcFlash(_samba, "AT91SAM7S32", 0x100000, 256, 128, 1, 8, 0x201400, 0x202000, false);
|
||||
break;
|
||||
case 0x27050240:
|
||||
_family = FAMILY_SAM7S;
|
||||
flashPtr = new EfcFlash(_samba, "AT91SAM7S16", 0x100000, 256, 64, 1, 8, 0x200000, 0x200e00, false);
|
||||
break;
|
||||
//
|
||||
// SAM7XC
|
||||
//
|
||||
case 0x271c0a40:
|
||||
_family = FAMILY_SAM7XC;
|
||||
flashPtr = new EfcFlash(_samba, "AT91SAMXC512", 0x100000, 2048, 256, 2, 32, 0x202000, 0x220000, true);
|
||||
break;
|
||||
case 0x271b0940:
|
||||
_family = FAMILY_SAM7XC;
|
||||
flashPtr = new EfcFlash(_samba, "AT91SAMXC256", 0x100000, 1024, 256, 1, 16, 0x202000, 0x210000, true);
|
||||
break;
|
||||
case 0x271a0740:
|
||||
_family = FAMILY_SAM7XC;
|
||||
flashPtr = new EfcFlash(_samba, "AT91SAMXC128", 0x100000, 512, 256, 1, 8, 0x202000, 0x208000, true);
|
||||
break;
|
||||
//
|
||||
// SAM7X
|
||||
//
|
||||
case 0x275c0a40:
|
||||
_family = FAMILY_SAM7X;
|
||||
flashPtr = new EfcFlash(_samba, "AT91SAMX512", 0x100000, 2048, 256, 2, 32, 0x202000, 0x220000, true);
|
||||
break;
|
||||
case 0x275b0940:
|
||||
_family = FAMILY_SAM7X;
|
||||
flashPtr = new EfcFlash(_samba, "AT91SAMX256", 0x100000, 1024, 256, 1, 16, 0x202000, 0x210000, true);
|
||||
break;
|
||||
case 0x275a0740:
|
||||
_family = FAMILY_SAM7X;
|
||||
flashPtr = new EfcFlash(_samba, "AT91SAMX128", 0x100000, 512, 256, 1, 8, 0x202000, 0x208000, true);
|
||||
break;
|
||||
//
|
||||
// SAM4S
|
||||
//
|
||||
case 0x29870ee0: // A
|
||||
case 0x29970ee0: // B
|
||||
case 0x29A70ee0: // C
|
||||
_family = FAMILY_SAM4S;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM4SD32", 0x400000, 4096, 512, 2, 256, 0x20001000, 0x20010000, 0x400e0a00, false);
|
||||
break;
|
||||
case 0x29870c30: // A
|
||||
case 0x29970c30: // B
|
||||
case 0x29a70c30: // C
|
||||
_family = FAMILY_SAM4S;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM4SD16", 0x400000, 2048, 512, 2, 256, 0x20001000, 0x20010000, 0x400e0a00, false);
|
||||
break;
|
||||
case 0x28870ce0: // A
|
||||
case 0x28970ce0: // B
|
||||
case 0x28A70ce0: // C
|
||||
_family = FAMILY_SAM4S;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM4SA16", 0x400000, 2048, 512, 1, 256, 0x20001000, 0x20010000, 0x400e0a00, false);
|
||||
break;
|
||||
case 0x288c0ce0 : // A
|
||||
case 0x289c0ce0 : // B
|
||||
case 0x28ac0ce0 : // C
|
||||
_family = FAMILY_SAM4S;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM4S16", 0x400000, 2048, 512, 1, 128, 0x20001000, 0x20020000, 0x400e0a00, false);
|
||||
break;
|
||||
case 0x288c0ae0 : // A
|
||||
case 0x289c0ae0 : // B
|
||||
case 0x28ac0ae0 : // C
|
||||
_family = FAMILY_SAM4S;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM4S8", 0x400000, 1024, 512, 1, 64, 0x20001000, 0x20020000, 0x400e0a00, false);
|
||||
break;
|
||||
case 0x288b09e0 : // A
|
||||
case 0x289b09e0 : // B
|
||||
case 0x28ab09e0 : // C
|
||||
_family = FAMILY_SAM4S;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM4S4", 0x400000, 512, 512, 1, 16, 0x20001000, 0x20010000, 0x400e0a00, false);
|
||||
break;
|
||||
case 0x288b07e0 : // A
|
||||
case 0x289b07e0 : // B
|
||||
case 0x28ab07e0 : // C
|
||||
_family = FAMILY_SAM4S;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM4S2", 0x400000, 256, 512, 1, 16, 0x20001000, 0x20010000, 0x400e0a00, false);
|
||||
break;
|
||||
//
|
||||
// SAM3N
|
||||
//
|
||||
case 0x29340960 : // A
|
||||
case 0x29440960 : // B
|
||||
case 0x29540960 : // C
|
||||
_family = FAMILY_SAM3N;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM3N4", 0x400000, 1024, 256, 1, 16, 0x20001000, 0x20006000, 0x400e0a00, false);
|
||||
break;
|
||||
case 0x29390760 : // A
|
||||
case 0x29490760 : // B
|
||||
case 0x29590760 : // C
|
||||
_family = FAMILY_SAM3N;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM3N2", 0x400000, 512, 256, 1, 8, 0x20001000, 0x20004000, 0x400e0a00, false);
|
||||
break;
|
||||
case 0x29380560 : // A
|
||||
case 0x29480560 : // B
|
||||
case 0x29580560 : // C
|
||||
_family = FAMILY_SAM3N;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM3N1", 0x400000, 256, 256, 1, 4, 0x20000800, 0x20002000, 0x400e0a00, false);
|
||||
break;
|
||||
case 0x29380360 : // A
|
||||
case 0x29480360 : // B
|
||||
case 0x29580360 : // C
|
||||
_family = FAMILY_SAM3N;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM3N0", 0x400000, 128, 256, 1, 1, 0x20000800, 0x20002000, 0x400e0a00, false);
|
||||
break;
|
||||
//
|
||||
// SAM3S
|
||||
//
|
||||
case 0x299b0a60 : // B
|
||||
case 0x29ab0a60 : // C
|
||||
_family = FAMILY_SAM3S;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM3SD8", 0x400000, 2048, 256, 1, 16, 0x20001000, 0x20010000, 0x400e0a00, false);
|
||||
break;
|
||||
case 0x289b0a60 : // B
|
||||
case 0x28ab0a60 : // C
|
||||
_family = FAMILY_SAM3S;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM3S8", 0x400000, 2048, 256, 1, 16, 0x20001000, 0x20010000, 0x400e0a00, false);
|
||||
break;
|
||||
case 0x28800960 : // A
|
||||
case 0x28900960 : // B
|
||||
case 0x28a00960 : // C
|
||||
_family = FAMILY_SAM3S;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM3S4", 0x400000, 1024, 256, 1, 16, 0x20001000, 0x2000c000, 0x400e0a00, false);
|
||||
break;
|
||||
case 0x288a0760 : // A
|
||||
case 0x289a0760 : // B
|
||||
case 0x28aa0760 : // C
|
||||
_family = FAMILY_SAM3S;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM3S2", 0x400000, 512, 256, 1, 8, 0x20000800, 0x20008000, 0x400e0a00, false);
|
||||
break;
|
||||
case 0x288a0560 : // A
|
||||
case 0x289a0560 : // B
|
||||
case 0x28aa0560 : // C
|
||||
_family = FAMILY_SAM3S;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM3S1", 0x400000, 256, 256, 1, 4, 0x20000800, 0x20004000, 0x400e0a00, false);
|
||||
break;
|
||||
//
|
||||
// SAM3U
|
||||
//
|
||||
case 0x28000960 : // C
|
||||
case 0x28100960 : // E
|
||||
_family = FAMILY_SAM3U;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM3U4", 0xE0000, 1024, 256, 2, 32, 0x20001000, 0x20008000, 0x400e0800, false);
|
||||
break;
|
||||
case 0x280a0760 : // C
|
||||
case 0x281a0760 : // E
|
||||
_family = FAMILY_SAM3U;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM3U2", 0x80000, 512, 256, 1, 16, 0x20001000, 0x20004000, 0x400e0800, false);
|
||||
break;
|
||||
case 0x28090560 : // C
|
||||
case 0x28190560 : // E
|
||||
_family = FAMILY_SAM3U;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM3U1", 0x80000, 256, 256, 1, 8, 0x20001000, 0x20002000, 0x400e0800, false);
|
||||
break;
|
||||
//
|
||||
// SAM3X
|
||||
//
|
||||
case 0x286e0a60 : // 8H
|
||||
case 0x285e0a60 : // 8E
|
||||
case 0x284e0a60 : // 8C
|
||||
_family = FAMILY_SAM3X;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM3X8", 0x80000, 2048, 256, 2, 32, 0x20001000, 0x20010000, 0x400e0a00, false);
|
||||
break;
|
||||
case 0x285b0960 : // 4E
|
||||
case 0x284b0960 : // 4C
|
||||
_family = FAMILY_SAM3X;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM3X4", 0x80000, 1024, 256, 2, 16, 0x20001000, 0x20008000, 0x400e0a00, false);
|
||||
break;
|
||||
//
|
||||
// SAM3A
|
||||
//
|
||||
case 0x283e0A60 : // 8C
|
||||
_family = FAMILY_SAM3A;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM3A8", 0x80000, 2048, 256, 2, 32, 0x20001000, 0x20010000, 0x400e0a00, false);
|
||||
break;
|
||||
case 0x283b0960 : // 4C
|
||||
_family = FAMILY_SAM3A;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM3A4", 0x80000, 1024, 256, 2, 16, 0x20001000, 0x20008000, 0x400e0a00, false);
|
||||
break;
|
||||
//
|
||||
// SAM7L
|
||||
//
|
||||
case 0x27330740 :
|
||||
_family = FAMILY_SAM7L;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM7L128", 0x100000, 512, 256, 1, 16, 0x2ffb40, 0x300700, 0xffffff60, false);
|
||||
break;
|
||||
case 0x27330540 :
|
||||
_family = FAMILY_SAM7L;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM7L64", 0x100000, 256, 256, 1, 8, 0x2ffb40, 0x300700, 0xffffff60, false);
|
||||
break;
|
||||
//
|
||||
// SAM9XE
|
||||
//
|
||||
case 0x329aa3a0 :
|
||||
_family = FAMILY_SAM9XE;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM9XE512", 0x200000, 1024, 512, 1, 32, 0x300000, 0x307000, 0xfffffa00, true);
|
||||
break;
|
||||
case 0x329a93a0 :
|
||||
_family = FAMILY_SAM9XE;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM9XE256", 0x200000, 512, 512, 1, 16, 0x300000, 0x307000, 0xfffffa00, true);
|
||||
break;
|
||||
case 0x329973a0 :
|
||||
_family = FAMILY_SAM9XE;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM9XE128", 0x200000, 256, 512, 1, 8, 0x300000, 0x303000, 0xfffffa00, true);
|
||||
break;
|
||||
//
|
||||
// SAM4E
|
||||
//
|
||||
case 0x23cc0ce0:
|
||||
switch (extChipId)
|
||||
{
|
||||
case 0x00120200: // E
|
||||
case 0x00120201: // C
|
||||
_family = FAMILY_SAM4E;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM4E16", 0x400000, 2048, 512, 1, 128, 0x20001000, 0x20020000, 0x400e0a00, false);
|
||||
break;
|
||||
case 0x00120208: // E
|
||||
case 0x00120209: // C
|
||||
_family = FAMILY_SAM4E;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAM4E8", 0x400000, 1024, 512, 1, 64, 0x20001000, 0x20020000, 0x400e0a00, false);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
//
|
||||
// SAME70
|
||||
//
|
||||
case 0x210d0a00:
|
||||
_family = FAMILY_SAME70;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAME70x19", 0x400000, 1024, 512, 1, 32, 0x20401000, 0x20404000, 0x400e0c00, false);
|
||||
break;
|
||||
case 0x21020c00:
|
||||
_family = FAMILY_SAME70;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAME70x20", 0x400000, 2048, 512, 1, 64, 0x20401000, 0x20404000, 0x400e0c00, false);
|
||||
break;
|
||||
case 0x21020e00:
|
||||
_family = FAMILY_SAME70;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAME70x21", 0x400000, 4096, 512, 1, 128, 0x20401000, 0x20404000, 0x400e0c00, false);
|
||||
break;
|
||||
//
|
||||
// SAMS70
|
||||
//
|
||||
case 0x211d0a00:
|
||||
_family = FAMILY_SAMS70;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAMS70x19", 0x400000, 1024, 512, 1, 32, 0x20401000, 0x20404000, 0x400e0c00, false);
|
||||
break;
|
||||
case 0x21120c00:
|
||||
_family = FAMILY_SAMS70;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAMS70x20", 0x400000, 2048, 512, 1, 64, 0x20401000, 0x20404000, 0x400e0c00, false);
|
||||
break;
|
||||
case 0x21120e00:
|
||||
_family = FAMILY_SAMS70;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAMS70x21", 0x400000, 4096, 512, 1, 128, 0x20401000, 0x20404000, 0x400e0c00, false);
|
||||
break;
|
||||
//
|
||||
// SAMV70
|
||||
//
|
||||
case 0x213d0a00:
|
||||
_family = FAMILY_SAMV70;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAMV70x19", 0x400000, 1024, 512, 1, 32, 0x20401000, 0x20404000, 0x400e0c00, false);
|
||||
break;
|
||||
case 0x21320c00:
|
||||
_family = FAMILY_SAMV70;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAMV70x20", 0x400000, 2048, 512, 1, 64, 0x20401000, 0x20404000, 0x400e0c00, false);
|
||||
break;
|
||||
//
|
||||
// SAMV71
|
||||
//
|
||||
case 0x212d0a00:
|
||||
_family = FAMILY_SAMV71;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAMV71x19", 0x400000, 1024, 512, 1, 32, 0x20401000, 0x20404000, 0x400e0c00, false);
|
||||
break;
|
||||
case 0x21220c00:
|
||||
_family = FAMILY_SAMV71;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAMV71x20", 0x400000, 2048, 512, 1, 64, 0x20401000, 0x20404000, 0x400e0c00, false);
|
||||
break;
|
||||
case 0x21220e00:
|
||||
_family = FAMILY_SAMV71;
|
||||
flashPtr = new EefcFlash(_samba, "ATSAMV71x21", 0x400000, 4096, 512, 1, 128, 0x20401000, 0x20404000, 0x400e0c00, false);
|
||||
break;
|
||||
//
|
||||
// No CHIPID devices
|
||||
//
|
||||
case 0:
|
||||
switch (deviceId & 0xffff00ff)
|
||||
{
|
||||
//
|
||||
// SAMD21
|
||||
//
|
||||
case 0x10010003: // J15A
|
||||
case 0x10010008: // G15A
|
||||
case 0x1001000d: // E15A
|
||||
case 0x10010021: // J15B
|
||||
case 0x10010024: // G15B
|
||||
case 0x10010027: // E15B
|
||||
case 0x10010056: // E15B WLCSP
|
||||
case 0x10010063: // E15C WLCSP
|
||||
_family = FAMILY_SAMD21;
|
||||
flashPtr = new D2xNvmFlash(_samba, "ATSAMD21x15", 512, 64, 0x20000800, 0x20001000) ;
|
||||
break;
|
||||
|
||||
case 0x10010002: // J16A
|
||||
case 0x10010007: // G16A
|
||||
case 0x1001000c: // E16A
|
||||
case 0x10010020: // J16B
|
||||
case 0x10010023: // G16B
|
||||
case 0x10010026: // E16B
|
||||
case 0x10010055: // E16B WLCSP
|
||||
case 0x10010062: // E16C WLCSP
|
||||
_family = FAMILY_SAMD21;
|
||||
flashPtr = new D2xNvmFlash(_samba, "ATSAMD21x16", 1024, 64, 0x20001000, 0x20002000) ;
|
||||
break;
|
||||
|
||||
case 0x10010001: // J17A
|
||||
case 0x10010006: // G17A
|
||||
case 0x1001000b: // E17A
|
||||
case 0x10010010: // G17A WLCSP
|
||||
_family = FAMILY_SAMD21;
|
||||
flashPtr = new D2xNvmFlash(_samba, "ATSAMD21x17", 2048, 64, 0x20002000, 0x20004000) ;
|
||||
break;
|
||||
|
||||
case 0x10010000: // J18A
|
||||
case 0x10010005: // G18A
|
||||
case 0x1001000a: // E18A
|
||||
case 0x1001000f: // G18A WLCSP
|
||||
_family = FAMILY_SAMD21;
|
||||
flashPtr = new D2xNvmFlash(_samba, "ATSAMD21x18", 4096, 64, 0x20004000, 0x20008000) ;
|
||||
break;
|
||||
|
||||
//
|
||||
// SAMR21
|
||||
//
|
||||
case 0x1001001e: // E16A
|
||||
case 0x1001001b: // G16A
|
||||
_family = FAMILY_SAMR21;
|
||||
flashPtr = new D2xNvmFlash(_samba, "ATSAMR21x16", 1024, 64, 0x20001000, 0x20002000) ;
|
||||
break;
|
||||
|
||||
case 0x1001001d: // E17A
|
||||
case 0x1001001a: // G17A
|
||||
_family = FAMILY_SAMR21;
|
||||
flashPtr = new D2xNvmFlash(_samba, "ATSAMR21x17", 2048, 64, 0x20002000, 0x20004000) ;
|
||||
break;
|
||||
|
||||
case 0x1001001c: // E18A
|
||||
case 0x10010019: // G18A
|
||||
_family = FAMILY_SAMR21;
|
||||
flashPtr = new D2xNvmFlash(_samba, "ATSAMR21x18", 4096, 64, 0x20004000, 0x20008000) ;
|
||||
break;
|
||||
|
||||
case 0x10010018: // E19A
|
||||
_family = FAMILY_SAMR21;
|
||||
flashPtr = new D2xNvmFlash(_samba, "ATSAMR21x19", 4096, 64, 0x20004000, 0x20008000) ;
|
||||
break;
|
||||
|
||||
//
|
||||
// SAML21
|
||||
//
|
||||
case 0x1081000d: // E15A
|
||||
case 0x1081001c: // E15B
|
||||
_family = FAMILY_SAMD21;
|
||||
flashPtr = new D2xNvmFlash(_samba, "ATSAML21x15", 512, 64, 0x20000800, 0x20001000) ;
|
||||
break;
|
||||
|
||||
case 0x10810002: // J16A
|
||||
case 0x10810007: // G16A
|
||||
case 0x1081000c: // E16A
|
||||
case 0x10810011: // J16B
|
||||
case 0x10810016: // G16B
|
||||
case 0x1081001b: // E16B
|
||||
_family = FAMILY_SAML21;
|
||||
flashPtr = new D2xNvmFlash(_samba, "ATSAML21x16", 1024, 64, 0x20001000, 0x20002000) ;
|
||||
break;
|
||||
|
||||
case 0x10810001: // J17A
|
||||
case 0x10810006: // G17A
|
||||
case 0x1081000b: // E17A
|
||||
case 0x10810010: // J17B
|
||||
case 0x10810015: // G17B
|
||||
case 0x1081001a: // E17B
|
||||
_family = FAMILY_SAML21;
|
||||
flashPtr = new D2xNvmFlash(_samba, "ATSAML21x17", 2048, 64, 0x20002000, 0x20004000) ;
|
||||
break;
|
||||
|
||||
case 0x10810000: // J18A
|
||||
case 0x10810005: // G18A
|
||||
case 0x1081000a: // E18A
|
||||
case 0x1081000f: // J18B
|
||||
case 0x10810014: // G18B
|
||||
case 0x10810019: // E18B
|
||||
_family = FAMILY_SAML21;
|
||||
flashPtr = new D2xNvmFlash(_samba, "ATSAML21x18", 4096, 64, 0x20004000, 0x20008000) ;
|
||||
break;
|
||||
|
||||
//
|
||||
// SAMD51
|
||||
//
|
||||
case 0x60060006: // J18A
|
||||
case 0x60060008: // G18A
|
||||
_family = FAMILY_SAMD51;
|
||||
flashPtr = new D5xNvmFlash(_samba, "ATSAMD51x18", 512, 512, 0x20004000, 0x20008000) ;
|
||||
break;
|
||||
|
||||
case 0x60060001: // P19A
|
||||
case 0x60060003: // N19A
|
||||
case 0x60060005: // J19A
|
||||
case 0x60060007: // G19A
|
||||
_family = FAMILY_SAMD51;
|
||||
flashPtr = new D5xNvmFlash(_samba, "ATSAMD51x19", 1024, 512, 0x20004000, 0x20008000) ;
|
||||
break;
|
||||
|
||||
case 0x60060000: // P20A
|
||||
case 0x60060002: // N20A
|
||||
case 0x60060004: // J20A
|
||||
_family = FAMILY_SAMD51;
|
||||
flashPtr = new D5xNvmFlash(_samba, "ATSAMD51x20", 2048, 512, 0x20004000, 0x20008000) ;
|
||||
break;
|
||||
|
||||
//
|
||||
// SAME51
|
||||
//
|
||||
case 0x61810003: // J18A
|
||||
_family = FAMILY_SAME51;
|
||||
flashPtr = new D5xNvmFlash(_samba, "ATSAME51x18", 512, 512, 0x20004000, 0x20008000) ;
|
||||
break;
|
||||
|
||||
case 0x61810002: // J19A
|
||||
case 0x61810001: // N19A
|
||||
_family = FAMILY_SAME51;
|
||||
flashPtr = new D5xNvmFlash(_samba, "ATSAME51x19", 1024, 512, 0x20004000, 0x20008000) ;
|
||||
break;
|
||||
|
||||
case 0x61810004: // J20A
|
||||
case 0x61810000: // N20A
|
||||
_family = FAMILY_SAME51;
|
||||
flashPtr = new D5xNvmFlash(_samba, "ATSAME51x20", 2048, 512, 0x20004000, 0x20008000) ;
|
||||
break;
|
||||
|
||||
//
|
||||
// SAME53
|
||||
//
|
||||
case 0x61830006: // J18A
|
||||
_family = FAMILY_SAME53;
|
||||
flashPtr = new D5xNvmFlash(_samba, "ATSAME53x18", 512, 512, 0x20004000, 0x20008000) ;
|
||||
break;
|
||||
|
||||
case 0x61830005: // J19A
|
||||
case 0x61830003: // N19A
|
||||
_family = FAMILY_SAME53;
|
||||
flashPtr = new D5xNvmFlash(_samba, "ATSAME53x19", 1024, 512, 0x20004000, 0x20008000) ;
|
||||
break;
|
||||
|
||||
case 0x61830004: // J20A
|
||||
case 0x61830002: // N20A
|
||||
_family = FAMILY_SAME53;
|
||||
flashPtr = new D5xNvmFlash(_samba, "ATSAME53x20", 2048, 512, 0x20004000, 0x20008000) ;
|
||||
break;
|
||||
|
||||
//
|
||||
// SAME54
|
||||
//
|
||||
case 0x61840001: // P19A
|
||||
case 0x61840003: // N19A
|
||||
_family = FAMILY_SAME54;
|
||||
flashPtr = new D5xNvmFlash(_samba, "ATSAME54x19", 1024, 512, 0x20004000, 0x20008000) ;
|
||||
break;
|
||||
|
||||
case 0x61840000: // P20A
|
||||
case 0x61840002: // N20A
|
||||
_family = FAMILY_SAME54;
|
||||
flashPtr = new D5xNvmFlash(_samba, "ATSAME54x20", 2048, 512, 0x20004000, 0x20008000) ;
|
||||
break;
|
||||
|
||||
//
|
||||
// Unknown
|
||||
//
|
||||
default:
|
||||
throw DeviceUnsupportedError();
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
//
|
||||
// Unsupported device
|
||||
//
|
||||
default:
|
||||
throw DeviceUnsupportedError();
|
||||
break;
|
||||
}
|
||||
|
||||
_flash = std::unique_ptr<Flash>(flashPtr);
|
||||
}
|
||||
|
||||
void
|
||||
Device::reset()
|
||||
{
|
||||
try
|
||||
{
|
||||
switch (_family)
|
||||
{
|
||||
case FAMILY_SAMD21:
|
||||
case FAMILY_SAMR21:
|
||||
case FAMILY_SAML21:
|
||||
case FAMILY_SAMD51:
|
||||
case FAMILY_SAME51:
|
||||
case FAMILY_SAME53:
|
||||
case FAMILY_SAME54:
|
||||
case FAMILY_SAME70:
|
||||
case FAMILY_SAMS70:
|
||||
case FAMILY_SAMV70:
|
||||
case FAMILY_SAMV71:
|
||||
_samba.writeWord(0xE000ED0C, 0x05FA0004);
|
||||
break;
|
||||
|
||||
case FAMILY_SAM3X:
|
||||
case FAMILY_SAM3S:
|
||||
case FAMILY_SAM3A:
|
||||
_samba.writeWord(0x400E1A00, 0xA500000D);
|
||||
break;
|
||||
|
||||
case FAMILY_SAM3U:
|
||||
_samba.writeWord(0x400E1200, 0xA500000D);
|
||||
break;
|
||||
|
||||
case FAMILY_SAM3N:
|
||||
case FAMILY_SAM4S:
|
||||
_samba.writeWord(0x400E1400, 0xA500000D);
|
||||
break;
|
||||
|
||||
case FAMILY_SAM4E:
|
||||
_samba.writeWord(0x400E1800, 0xA500000D);
|
||||
break;
|
||||
|
||||
case FAMILY_SAM7S:
|
||||
case FAMILY_SAM7SE:
|
||||
case FAMILY_SAM7X:
|
||||
case FAMILY_SAM7XC:
|
||||
case FAMILY_SAM7L:
|
||||
case FAMILY_SAM9XE:
|
||||
_samba.writeWord(0xFFFFFD00, 0xA500000D);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
catch (std::exception& expected)
|
||||
{ // writeWord will most likely throw an exception when the CPU is reset
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -0,0 +1,104 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#ifndef _DEVICE_H
|
||||
#define _DEVICE_H
|
||||
|
||||
#include <exception>
|
||||
|
||||
#include "Samba.h"
|
||||
#include "Flash.h"
|
||||
|
||||
class DeviceUnsupportedError : public std::exception
|
||||
{
|
||||
public:
|
||||
DeviceUnsupportedError() : exception() {};
|
||||
const char* what() const throw() { return "Device unsupported"; }
|
||||
};
|
||||
|
||||
class Device
|
||||
{
|
||||
public:
|
||||
enum Family {
|
||||
FAMILY_NONE,
|
||||
|
||||
FAMILY_SAM7S,
|
||||
FAMILY_SAM7SE,
|
||||
FAMILY_SAM7X,
|
||||
FAMILY_SAM7XC,
|
||||
FAMILY_SAM7L,
|
||||
|
||||
FAMILY_SAM3N,
|
||||
FAMILY_SAM3S,
|
||||
FAMILY_SAM3U,
|
||||
FAMILY_SAM3X,
|
||||
FAMILY_SAM3A,
|
||||
|
||||
FAMILY_SAM4S,
|
||||
FAMILY_SAM4E,
|
||||
|
||||
FAMILY_SAM9XE,
|
||||
|
||||
FAMILY_SAMD21,
|
||||
FAMILY_SAMR21,
|
||||
FAMILY_SAML21,
|
||||
|
||||
FAMILY_SAMD51,
|
||||
FAMILY_SAME51,
|
||||
FAMILY_SAME53,
|
||||
FAMILY_SAME54,
|
||||
|
||||
FAMILY_SAME70,
|
||||
FAMILY_SAMS70,
|
||||
FAMILY_SAMV70,
|
||||
FAMILY_SAMV71,
|
||||
};
|
||||
|
||||
Device(Samba& samba) : _samba(samba), _flash(nullptr), _family(FAMILY_NONE) {}
|
||||
virtual ~Device() {}
|
||||
|
||||
void create();
|
||||
|
||||
Family getFamily() { return _family; }
|
||||
|
||||
typedef std::unique_ptr<Flash> const FlashPtr;
|
||||
|
||||
FlashPtr& getFlash() { return _flash; }
|
||||
|
||||
void reset();
|
||||
|
||||
private:
|
||||
Samba& _samba;
|
||||
std::unique_ptr<Flash> _flash;
|
||||
Family _family;
|
||||
|
||||
void readChipId(uint32_t& chipId, uint32_t& extChipId);
|
||||
};
|
||||
|
||||
#endif // _DEVICE_H
|
||||
|
||||
@@ -0,0 +1,363 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#include "EefcFlash.h"
|
||||
|
||||
#include <assert.h>
|
||||
#include <unistd.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#define EEFC_KEY 0x5a
|
||||
|
||||
#define EEFC0_FMR (_regs + 0x00)
|
||||
#define EEFC0_FCR (_regs + 0x04)
|
||||
#define EEFC0_FSR (_regs + 0x08)
|
||||
#define EEFC0_FRR (_regs + 0x0C)
|
||||
|
||||
#define EEFC1_FMR (_regs + 0x200)
|
||||
#define EEFC1_FCR (_regs + 0x204)
|
||||
#define EEFC1_FSR (_regs + 0x208)
|
||||
#define EEFC1_FRR (_regs + 0x20C)
|
||||
|
||||
#define EEFC_FCMD_GETD 0x0
|
||||
#define EEFC_FCMD_WP 0x1
|
||||
#define EEFC_FCMD_WPL 0x2
|
||||
#define EEFC_FCMD_EWP 0x3
|
||||
#define EEFC_FCMD_EWPL 0x4
|
||||
#define EEFC_FCMD_EA 0x5
|
||||
#define EEFC_FCMD_EPA 0x7
|
||||
#define EEFC_FCMD_SLB 0x8
|
||||
#define EEFC_FCMD_CLB 0x9
|
||||
#define EEFC_FCMD_GLB 0xa
|
||||
#define EEFC_FCMD_SGPB 0xb
|
||||
#define EEFC_FCMD_CGPB 0xc
|
||||
#define EEFC_FCMD_GGPB 0xd
|
||||
|
||||
const uint32_t
|
||||
EefcFlash::PagesPerErase = 8;
|
||||
|
||||
EefcFlash::EefcFlash(Samba& samba,
|
||||
const std::string& name,
|
||||
uint32_t addr,
|
||||
uint32_t pages,
|
||||
uint32_t size,
|
||||
uint32_t planes,
|
||||
uint32_t lockRegions,
|
||||
uint32_t user,
|
||||
uint32_t stack,
|
||||
uint32_t regs,
|
||||
bool canBrownout)
|
||||
: Flash(samba, name, addr, pages, size, planes, lockRegions, user, stack),
|
||||
_regs(regs), _canBrownout(canBrownout), _eraseAuto(true)
|
||||
{
|
||||
assert(planes == 1 || planes == 2);
|
||||
assert(pages <= 4096);
|
||||
assert(lockRegions <= 256);
|
||||
|
||||
// SAM3 Errata (FWS must be 6)
|
||||
_samba.writeWord(EEFC0_FMR, 0x6 << 8);
|
||||
if (planes == 2)
|
||||
_samba.writeWord(EEFC1_FMR, 0x6 << 8);
|
||||
}
|
||||
|
||||
EefcFlash::~EefcFlash()
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
EefcFlash::eraseAll(uint32_t offset)
|
||||
{
|
||||
// Do a full chip erase if the offset is 0
|
||||
if (offset == 0)
|
||||
{
|
||||
waitFSR();
|
||||
writeFCR0(EEFC_FCMD_EA, 0);
|
||||
if (_planes == 2)
|
||||
{
|
||||
waitFSR();
|
||||
writeFCR1(EEFC_FCMD_EA, 0);
|
||||
}
|
||||
|
||||
// Erase all can take an exceptionally long time on some devices
|
||||
// so wait on FSR for up to 30 seconds
|
||||
waitFSR(30);
|
||||
}
|
||||
// Else we must do it by pages
|
||||
else
|
||||
{
|
||||
// Offset must be on an erase page boundary
|
||||
if (offset % (_size * PagesPerErase))
|
||||
throw FlashEraseError();
|
||||
|
||||
// Erase each PagesPerErase set of pages
|
||||
for (uint32_t pageNum = offset / _size; pageNum < _pages; pageNum += PagesPerErase)
|
||||
{
|
||||
if (_planes == 1 || pageNum < _pages / 2)
|
||||
{
|
||||
waitFSR();
|
||||
writeFCR0(EEFC_FCMD_EPA, pageNum | 0x1);
|
||||
}
|
||||
else
|
||||
{
|
||||
waitFSR();
|
||||
writeFCR1(EEFC_FCMD_EPA, (pageNum % (_pages / 2)) | 0x1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
EefcFlash::eraseAuto(bool enable)
|
||||
{
|
||||
_eraseAuto = enable;
|
||||
}
|
||||
|
||||
std::vector<bool>
|
||||
EefcFlash::getLockRegions()
|
||||
{
|
||||
std::vector<bool> regions(_lockRegions);
|
||||
uint32_t frr;
|
||||
uint32_t bit;
|
||||
|
||||
waitFSR();
|
||||
for (uint32_t region = 0; region < _lockRegions; region++)
|
||||
{
|
||||
if (_planes == 2 && region >= _lockRegions / 2)
|
||||
{
|
||||
bit = region - _lockRegions / 2;
|
||||
writeFCR1(EEFC_FCMD_GLB, 0);
|
||||
waitFSR();
|
||||
frr = readFRR1();
|
||||
while (bit >= 32)
|
||||
{
|
||||
frr = readFRR1();
|
||||
bit -= 32;
|
||||
}
|
||||
regions[region] = (frr & (1 << bit)) != 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
bit = region;
|
||||
writeFCR0(EEFC_FCMD_GLB, 0);
|
||||
waitFSR();
|
||||
frr = readFRR0();
|
||||
while (bit >= 32)
|
||||
{
|
||||
frr = readFRR0();
|
||||
bit -= 32;
|
||||
}
|
||||
regions[region] = (frr & (1 << bit)) != 0;
|
||||
}
|
||||
}
|
||||
|
||||
return regions;
|
||||
}
|
||||
|
||||
bool
|
||||
EefcFlash::getSecurity()
|
||||
{
|
||||
waitFSR();
|
||||
writeFCR0(EEFC_FCMD_GGPB, 0);
|
||||
waitFSR();
|
||||
return (readFRR0() & (1 << 0));
|
||||
}
|
||||
|
||||
bool
|
||||
EefcFlash::getBod()
|
||||
{
|
||||
if (!_canBrownout)
|
||||
return false;
|
||||
|
||||
waitFSR();
|
||||
writeFCR0(EEFC_FCMD_GGPB, 0);
|
||||
waitFSR();
|
||||
return (readFRR0() & (1 << 1));
|
||||
}
|
||||
|
||||
bool
|
||||
EefcFlash::getBor()
|
||||
{
|
||||
if (!_canBrownout)
|
||||
return false;
|
||||
|
||||
waitFSR();
|
||||
writeFCR0(EEFC_FCMD_GGPB, 0);
|
||||
waitFSR();
|
||||
return (readFRR0() & (1 << 2));
|
||||
}
|
||||
|
||||
bool
|
||||
EefcFlash::getBootFlash()
|
||||
{
|
||||
waitFSR();
|
||||
writeFCR0(EEFC_FCMD_GGPB, 0);
|
||||
waitFSR();
|
||||
return (readFRR0() & (1 << (_canBrownout ? 3 : 1)));
|
||||
}
|
||||
|
||||
void
|
||||
EefcFlash::writeOptions()
|
||||
{
|
||||
if (canBootFlash() && _bootFlash.isDirty() && _bootFlash.get() != getBootFlash())
|
||||
{
|
||||
waitFSR();
|
||||
writeFCR0(_bootFlash.get() ? EEFC_FCMD_SGPB : EEFC_FCMD_CGPB, (canBod() ? 3 : 1));
|
||||
}
|
||||
if (canBor() && _bor.isDirty() && _bor.get() != getBor())
|
||||
{
|
||||
waitFSR();
|
||||
writeFCR0(_bor.get() ? EEFC_FCMD_SGPB : EEFC_FCMD_CGPB, 2);
|
||||
}
|
||||
if (canBod() && _bod.isDirty() && _bod.get() != getBod())
|
||||
{
|
||||
waitFSR();
|
||||
writeFCR0(_bod.get() ? EEFC_FCMD_SGPB : EEFC_FCMD_CGPB, 1);
|
||||
}
|
||||
if (_regions.isDirty())
|
||||
{
|
||||
uint32_t page;
|
||||
std::vector<bool> current;
|
||||
|
||||
if (_regions.get().size() >= _lockRegions)
|
||||
throw FlashRegionError();
|
||||
|
||||
current = getLockRegions();
|
||||
|
||||
for (uint32_t region = 0; region < _lockRegions; region++)
|
||||
{
|
||||
if (_regions.get()[region] != current[region])
|
||||
{
|
||||
if (_planes == 2 && region >= _lockRegions / 2)
|
||||
{
|
||||
page = (region - _lockRegions / 2) * _pages / _lockRegions;
|
||||
waitFSR();
|
||||
writeFCR1(_regions.get()[region] ? EEFC_FCMD_SLB : EEFC_FCMD_CLB, page);
|
||||
}
|
||||
else
|
||||
{
|
||||
page = region * _pages / _lockRegions;
|
||||
waitFSR();
|
||||
writeFCR0(_regions.get()[region] ? EEFC_FCMD_SLB : EEFC_FCMD_CLB, page);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if (_security.isDirty() && _security.get() == true && _security.get() != getSecurity())
|
||||
{
|
||||
waitFSR();
|
||||
writeFCR0(EEFC_FCMD_SGPB, 0);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
EefcFlash::writePage(uint32_t page)
|
||||
{
|
||||
if (page >= _pages)
|
||||
throw FlashPageError();
|
||||
|
||||
_wordCopy.setDstAddr(_addr + page * _size);
|
||||
_wordCopy.setSrcAddr(_onBufferA ? _pageBufferA : _pageBufferB);
|
||||
_onBufferA = !_onBufferA;
|
||||
waitFSR();
|
||||
_wordCopy.runv();
|
||||
if (_planes == 2 && page >= _pages / 2)
|
||||
writeFCR1(_eraseAuto ? EEFC_FCMD_EWP : EEFC_FCMD_WP, page - _pages / 2);
|
||||
else
|
||||
writeFCR0(_eraseAuto ? EEFC_FCMD_EWP : EEFC_FCMD_WP, page);
|
||||
}
|
||||
|
||||
void
|
||||
EefcFlash::readPage(uint32_t page, uint8_t* data)
|
||||
{
|
||||
if (page >= _pages)
|
||||
throw FlashPageError();
|
||||
|
||||
// The SAM3 firmware has a bug where it returns all zeros for reads
|
||||
// directly from the flash so instead, we copy the flash page to
|
||||
// SRAM and read it from there.
|
||||
_wordCopy.setDstAddr(_onBufferA ? _pageBufferA : _pageBufferB);
|
||||
_wordCopy.setSrcAddr(_addr + page * _size);
|
||||
waitFSR();
|
||||
_wordCopy.runv();
|
||||
_samba.read(_onBufferA ? _pageBufferA : _pageBufferB, data, _size);
|
||||
}
|
||||
|
||||
void
|
||||
EefcFlash::waitFSR(int seconds)
|
||||
{
|
||||
int tries = seconds * 1000;
|
||||
uint32_t fsr0;
|
||||
uint32_t fsr1 = 0x1;
|
||||
|
||||
while (tries-- > 0)
|
||||
{
|
||||
fsr0 = _samba.readWord(EEFC0_FSR);
|
||||
if (fsr0 & 0x2)
|
||||
throw FlashCmdError();
|
||||
if (fsr0 & 0x4)
|
||||
throw FlashLockError();
|
||||
|
||||
if (_planes == 2)
|
||||
{
|
||||
fsr1 = _samba.readWord(EEFC1_FSR);
|
||||
if (fsr1 & 0x2)
|
||||
throw FlashCmdError();
|
||||
if (fsr1 & 0x4)
|
||||
throw FlashLockError();
|
||||
}
|
||||
if (fsr0 & fsr1 & 0x1)
|
||||
break;
|
||||
usleep(1000);
|
||||
}
|
||||
if (tries == 0)
|
||||
throw FlashTimeoutError();
|
||||
}
|
||||
|
||||
void
|
||||
EefcFlash::writeFCR0(uint8_t cmd, uint32_t arg)
|
||||
{
|
||||
_samba.writeWord(EEFC0_FCR, (EEFC_KEY << 24) | (arg << 8) | cmd);
|
||||
}
|
||||
|
||||
void
|
||||
EefcFlash::writeFCR1(uint8_t cmd, uint32_t arg)
|
||||
{
|
||||
_samba.writeWord(EEFC1_FCR, (EEFC_KEY << 24) | (arg << 8) | cmd);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
EefcFlash::readFRR0()
|
||||
{
|
||||
return _samba.readWord(EEFC0_FRR);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
EefcFlash::readFRR1()
|
||||
{
|
||||
return _samba.readWord(EEFC1_FRR);
|
||||
}
|
||||
@@ -0,0 +1,88 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#ifndef _EEFCFLASH_H
|
||||
#define _EEFCFLASH_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <exception>
|
||||
|
||||
#include "Flash.h"
|
||||
|
||||
class EefcFlash : public Flash
|
||||
{
|
||||
public:
|
||||
EefcFlash(Samba& samba,
|
||||
const std::string& name,
|
||||
uint32_t addr,
|
||||
uint32_t pages,
|
||||
uint32_t size,
|
||||
uint32_t planes,
|
||||
uint32_t lockRegions,
|
||||
uint32_t user,
|
||||
uint32_t stack,
|
||||
uint32_t regs,
|
||||
bool canBrownout);
|
||||
virtual ~EefcFlash();
|
||||
|
||||
void eraseAll(uint32_t offset);
|
||||
void eraseAuto(bool enable);
|
||||
|
||||
std::vector<bool> getLockRegions();
|
||||
|
||||
bool getSecurity();
|
||||
|
||||
bool getBod();
|
||||
bool canBod() { return _canBrownout; }
|
||||
|
||||
bool getBor();
|
||||
bool canBor() { return _canBrownout; }
|
||||
|
||||
bool getBootFlash();
|
||||
bool canBootFlash() { return true; }
|
||||
|
||||
void writeOptions();
|
||||
|
||||
void writePage(uint32_t page);
|
||||
void readPage(uint32_t page, uint8_t* data);
|
||||
|
||||
static const uint32_t PagesPerErase;
|
||||
|
||||
private:
|
||||
uint32_t _regs;
|
||||
bool _canBrownout;
|
||||
bool _eraseAuto;
|
||||
|
||||
void waitFSR(int seconds = 1);
|
||||
void writeFCR0(uint8_t cmd, uint32_t arg);
|
||||
void writeFCR1(uint8_t cmd, uint32_t arg);
|
||||
uint32_t readFRR0();
|
||||
uint32_t readFRR1();
|
||||
};
|
||||
|
||||
#endif // _EEFCFLASH_H
|
||||
@@ -0,0 +1,295 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#include "EfcFlash.h"
|
||||
|
||||
#include <assert.h>
|
||||
#include <unistd.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#define EFC_KEY 0x5a
|
||||
|
||||
#define EFC0_FMR 0xffffff60
|
||||
#define EFC0_FCR 0xffffff64
|
||||
#define EFC0_FSR 0xffffff68
|
||||
|
||||
#define EFC1_FMR 0xffffff70
|
||||
#define EFC1_FCR 0xffffff74
|
||||
#define EFC1_FSR 0xffffff78
|
||||
|
||||
#define EFC_FCMD_WP 0x1
|
||||
#define EFC_FCMD_SLB 0x2
|
||||
#define EFC_FCMD_WPL 0x3
|
||||
#define EFC_FCMD_CLB 0x4
|
||||
#define EFC_FCMD_EA 0x8
|
||||
#define EFC_FCMD_SGPB 0xb
|
||||
#define EFC_FCMD_CGPB 0xd
|
||||
#define EFC_FCMD_SSB 0xf
|
||||
|
||||
EfcFlash::EfcFlash(Samba& samba,
|
||||
const std::string& name,
|
||||
uint32_t addr,
|
||||
uint32_t pages,
|
||||
uint32_t size,
|
||||
uint32_t planes,
|
||||
uint32_t lockRegions,
|
||||
uint32_t user,
|
||||
uint32_t stack,
|
||||
bool canBootFlash)
|
||||
: Flash(samba, name, addr, pages, size, planes, lockRegions, user, stack),
|
||||
_canBootFlash(canBootFlash)
|
||||
{
|
||||
assert(planes == 1 || planes == 2);
|
||||
assert(pages <= planes * 1024);
|
||||
assert(lockRegions <= 32);
|
||||
|
||||
eraseAuto(true);
|
||||
}
|
||||
|
||||
EfcFlash::~EfcFlash()
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
EfcFlash::eraseAll(uint32_t offset)
|
||||
{
|
||||
if (offset != 0)
|
||||
throw FlashEraseError();
|
||||
|
||||
waitFSR();
|
||||
writeFCR0(EFC_FCMD_EA, 0);
|
||||
if (_planes == 2)
|
||||
{
|
||||
waitFSR();
|
||||
writeFCR0(EFC_FCMD_EA, _pages / 2);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
EfcFlash::eraseAuto(bool enable)
|
||||
{
|
||||
uint32_t fmr;
|
||||
|
||||
waitFSR();
|
||||
fmr = _samba.readWord(EFC0_FMR);
|
||||
if (enable)
|
||||
fmr &= ~(1 << 7);
|
||||
else
|
||||
fmr |= (1 << 7);
|
||||
|
||||
_samba.writeWord(EFC0_FMR, fmr);
|
||||
if (_planes == 2)
|
||||
{
|
||||
waitFSR();
|
||||
_samba.writeWord(EFC1_FMR, fmr);
|
||||
}
|
||||
}
|
||||
|
||||
std::vector<bool>
|
||||
EfcFlash::getLockRegions()
|
||||
{
|
||||
std::vector<bool> regions(_lockRegions);
|
||||
uint32_t fsr0;
|
||||
uint32_t fsr1;
|
||||
|
||||
fsr0 = readFSR0();
|
||||
if (_planes == 2)
|
||||
fsr1 = readFSR1();
|
||||
else
|
||||
fsr1 = 0;
|
||||
|
||||
for (uint32_t region = 0; region < _lockRegions; region++)
|
||||
{
|
||||
if (_planes == 2 && region >= _lockRegions / 2)
|
||||
regions[region] = (fsr1 & (1 << (16 + region - _lockRegions / 2))) != 0;
|
||||
else
|
||||
regions[region] = (fsr0 & (1 << (16 + region))) != 0;
|
||||
}
|
||||
|
||||
return regions;
|
||||
}
|
||||
|
||||
bool
|
||||
EfcFlash::getSecurity()
|
||||
{
|
||||
return (readFSR0() & (1 << 4));
|
||||
}
|
||||
|
||||
bool
|
||||
EfcFlash::getBod()
|
||||
{
|
||||
return (readFSR0() & (1 << 8));
|
||||
}
|
||||
|
||||
bool
|
||||
EfcFlash::getBor()
|
||||
{
|
||||
return (readFSR0() & (2 << 8));
|
||||
}
|
||||
|
||||
bool
|
||||
EfcFlash::getBootFlash()
|
||||
{
|
||||
if (!_canBootFlash)
|
||||
return false;
|
||||
|
||||
return (readFSR0() & (1 << 10));
|
||||
}
|
||||
|
||||
void
|
||||
EfcFlash::writeOptions()
|
||||
{
|
||||
if (canBootFlash() && _bootFlash.isDirty() && _bootFlash.get() != getBootFlash())
|
||||
{
|
||||
waitFSR();
|
||||
writeFCR0(_bootFlash.get() ? EFC_FCMD_SGPB : EFC_FCMD_CGPB, 2);
|
||||
}
|
||||
if (canBor() && _bor.isDirty() && _bor.get() != getBor())
|
||||
{
|
||||
waitFSR();
|
||||
writeFCR0(_bor.get() ? EFC_FCMD_SGPB : EFC_FCMD_CGPB, 1);
|
||||
}
|
||||
if (canBod() && _bod.isDirty() && _bod.get() != getBod())
|
||||
{
|
||||
waitFSR();
|
||||
writeFCR0(_bod.get() ? EFC_FCMD_SGPB : EFC_FCMD_CGPB, 0);
|
||||
}
|
||||
if (_regions.isDirty())
|
||||
{
|
||||
uint32_t page;
|
||||
std::vector<bool> current;
|
||||
|
||||
current = getLockRegions();
|
||||
|
||||
for (uint32_t region = 0; region < _regions.get().size(); region++)
|
||||
{
|
||||
if (_regions.get()[region] != current[region])
|
||||
{
|
||||
if (_planes == 2 && region >= _lockRegions / 2)
|
||||
{
|
||||
page = (region - _lockRegions / 2) * _pages / _lockRegions;
|
||||
waitFSR();
|
||||
writeFCR1(_regions.get()[region] ? EFC_FCMD_SLB : EFC_FCMD_CLB, page);
|
||||
}
|
||||
else
|
||||
{
|
||||
page = region * _pages / _lockRegions;
|
||||
waitFSR();
|
||||
writeFCR0(_regions.get()[region] ? EFC_FCMD_SLB : EFC_FCMD_CLB, page);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
if (_security.isDirty() && _security.get() == true && _security.get() != getSecurity())
|
||||
{
|
||||
waitFSR();
|
||||
writeFCR0(EFC_FCMD_SSB, 0);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
EfcFlash::writePage(uint32_t page)
|
||||
{
|
||||
if (page >= _pages)
|
||||
throw FlashPageError();
|
||||
|
||||
_wordCopy.setDstAddr(_addr + page * _size);
|
||||
_wordCopy.setSrcAddr(_onBufferA ? _pageBufferA : _pageBufferB);
|
||||
_onBufferA = !_onBufferA;
|
||||
waitFSR();
|
||||
_wordCopy.run();
|
||||
if (_planes == 2 && page >= _pages / 2)
|
||||
writeFCR1(EFC_FCMD_WP, page - _pages / 2);
|
||||
else
|
||||
writeFCR0(EFC_FCMD_WP, page);
|
||||
}
|
||||
|
||||
void
|
||||
EfcFlash::readPage(uint32_t page, uint8_t* data)
|
||||
{
|
||||
if (page >= _pages)
|
||||
throw FlashPageError();
|
||||
|
||||
waitFSR();
|
||||
_samba.read(_addr + page * _size, data, _size);
|
||||
}
|
||||
|
||||
void
|
||||
EfcFlash::waitFSR(int seconds)
|
||||
{
|
||||
int tries = seconds * 1000;
|
||||
uint32_t fsr0;
|
||||
uint32_t fsr1 = 0x1;
|
||||
|
||||
while (tries-- > 0)
|
||||
{
|
||||
fsr0 = readFSR0();
|
||||
if (fsr0 & 0x2)
|
||||
throw FlashCmdError();
|
||||
if (fsr0 & 0x4)
|
||||
throw FlashLockError();
|
||||
|
||||
if (_planes == 2)
|
||||
{
|
||||
fsr1 = readFSR1();
|
||||
if (fsr1 & 0x2)
|
||||
throw FlashCmdError();
|
||||
if (fsr1 & 0x4)
|
||||
throw FlashLockError();
|
||||
}
|
||||
if (fsr0 & fsr1 & 0x1)
|
||||
break;
|
||||
usleep(1000);
|
||||
}
|
||||
if (tries == 0)
|
||||
throw FlashTimeoutError();
|
||||
}
|
||||
|
||||
void
|
||||
EfcFlash::writeFCR0(uint8_t cmd, uint32_t arg)
|
||||
{
|
||||
_samba.writeWord(EFC0_FCR, (EFC_KEY << 24) | (arg << 8) | cmd);
|
||||
}
|
||||
|
||||
void
|
||||
EfcFlash::writeFCR1(uint8_t cmd, uint32_t arg)
|
||||
{
|
||||
_samba.writeWord(EFC1_FCR, (EFC_KEY << 24) | (arg << 8) | cmd);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
EfcFlash::readFSR0()
|
||||
{
|
||||
return _samba.readWord(EFC0_FSR);
|
||||
}
|
||||
|
||||
uint32_t
|
||||
EfcFlash::readFSR1()
|
||||
{
|
||||
return _samba.readWord(EFC1_FSR);
|
||||
}
|
||||
@@ -0,0 +1,83 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#ifndef _EFCFLASH_H
|
||||
#define _EFCFLASH_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <exception>
|
||||
|
||||
#include "Flash.h"
|
||||
|
||||
class EfcFlash : public Flash
|
||||
{
|
||||
public:
|
||||
EfcFlash(Samba& samba,
|
||||
const std::string& name,
|
||||
uint32_t addr,
|
||||
uint32_t pages,
|
||||
uint32_t size,
|
||||
uint32_t planes,
|
||||
uint32_t lockRegions,
|
||||
uint32_t user,
|
||||
uint32_t stack,
|
||||
bool canBootFlash);
|
||||
virtual ~EfcFlash();
|
||||
|
||||
void eraseAll(uint32_t offset);
|
||||
void eraseAuto(bool enable);
|
||||
|
||||
std::vector<bool> getLockRegions();
|
||||
|
||||
bool getSecurity();
|
||||
|
||||
bool getBod();
|
||||
bool canBod() { return true; }
|
||||
|
||||
bool getBor();
|
||||
bool canBor() { return true; }
|
||||
|
||||
bool getBootFlash();
|
||||
bool canBootFlash() { return _canBootFlash; }
|
||||
|
||||
void writeOptions();
|
||||
|
||||
void writePage(uint32_t page);
|
||||
void readPage(uint32_t page, uint8_t* data);
|
||||
|
||||
private:
|
||||
bool _canBootFlash;
|
||||
|
||||
void waitFSR(int seconds = 1);
|
||||
void writeFCR0(uint8_t cmd, uint32_t arg);
|
||||
void writeFCR1(uint8_t cmd, uint32_t arg);
|
||||
uint32_t readFSR0();
|
||||
uint32_t readFSR1();
|
||||
};
|
||||
|
||||
#endif // _EFCFLASH_H
|
||||
@@ -0,0 +1,94 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#ifndef _FILEERROR_H
|
||||
#define _FILEERROR_H
|
||||
|
||||
#include <exception>
|
||||
#include <errno.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "Flash.h"
|
||||
#include "Samba.h"
|
||||
|
||||
class FileError : public std::exception
|
||||
{
|
||||
public:
|
||||
FileError() : std::exception() {}
|
||||
};
|
||||
|
||||
class FileOpenError : public FileError
|
||||
{
|
||||
public:
|
||||
FileOpenError() : FileError(), _errnum(0) {};
|
||||
FileOpenError(int errnum) : FileError(), _errnum(errnum) {};
|
||||
const char* what() const throw()
|
||||
{
|
||||
if (_errnum == 0)
|
||||
return "Unable to open file";
|
||||
else
|
||||
return strerror(_errnum);
|
||||
}
|
||||
private:
|
||||
int _errnum;
|
||||
};
|
||||
|
||||
class FileIoError : public FileError
|
||||
{
|
||||
public:
|
||||
FileIoError() : FileError(), _errnum(0) {};
|
||||
FileIoError(int errnum) : FileError(), _errnum(errnum) {};
|
||||
const char* what() const throw()
|
||||
{
|
||||
if (_errnum == 0)
|
||||
return "File I/O operation failed";
|
||||
else
|
||||
return strerror(_errnum);
|
||||
}
|
||||
private:
|
||||
int _errnum;
|
||||
};
|
||||
|
||||
class FileShortError : public FileError
|
||||
{
|
||||
public:
|
||||
FileShortError() : FileError() {};
|
||||
const char* what() const throw()
|
||||
{
|
||||
return "Operation ended with a short write";
|
||||
}
|
||||
};
|
||||
|
||||
class FileSizeError : public FileError
|
||||
{
|
||||
public:
|
||||
FileSizeError() {};
|
||||
const char* what() const throw() { return "File operation exceeds flash size"; }
|
||||
};
|
||||
|
||||
#endif // _FILEERROR_H
|
||||
@@ -0,0 +1,106 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#include "Flash.h"
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
Flash::Flash(Samba& samba,
|
||||
const std::string& name,
|
||||
uint32_t addr,
|
||||
uint32_t pages,
|
||||
uint32_t size,
|
||||
uint32_t planes,
|
||||
uint32_t lockRegions,
|
||||
uint32_t user,
|
||||
uint32_t stack)
|
||||
: _samba(samba), _name(name), _addr(addr), _pages(pages), _size(size),
|
||||
_planes(planes), _lockRegions(lockRegions), _user(user), _wordCopy(samba, user)
|
||||
{
|
||||
assert((size & (size - 1)) == 0);
|
||||
assert((pages & (pages - 1)) == 0);
|
||||
assert((lockRegions & (lockRegions - 1)) == 0);
|
||||
|
||||
_wordCopy.setWords(size / sizeof(uint32_t));
|
||||
_wordCopy.setStack(stack);
|
||||
|
||||
_onBufferA = true;
|
||||
|
||||
// page buffers will have the size of a physical page and will be situated right after the applet
|
||||
_pageBufferA = ((_user + _wordCopy.size() + 3) / 4) * 4; // we need to avoid non 32bits aligned access on Cortex-M0+
|
||||
_pageBufferB = _pageBufferA + size;
|
||||
}
|
||||
|
||||
void
|
||||
Flash::setLockRegions(const std::vector<bool>& regions)
|
||||
{
|
||||
if (regions.size() > _lockRegions)
|
||||
throw FlashRegionError();
|
||||
|
||||
_regions.set(regions);
|
||||
}
|
||||
|
||||
void
|
||||
Flash::setSecurity()
|
||||
{
|
||||
_security.set(true);
|
||||
}
|
||||
|
||||
void
|
||||
Flash::setBor(bool enable)
|
||||
{
|
||||
if (canBor())
|
||||
_bor.set(enable);
|
||||
}
|
||||
|
||||
void
|
||||
Flash::setBod(bool enable)
|
||||
{
|
||||
if (canBod())
|
||||
_bod.set(enable);
|
||||
}
|
||||
|
||||
void
|
||||
Flash::setBootFlash(bool enable)
|
||||
{
|
||||
if (canBootFlash())
|
||||
_bootFlash.set(enable);
|
||||
}
|
||||
|
||||
void
|
||||
Flash::loadBuffer(const uint8_t* data, uint16_t bufferSize)
|
||||
{
|
||||
_samba.write(_onBufferA ? _pageBufferA : _pageBufferB, data, bufferSize);
|
||||
}
|
||||
|
||||
void
|
||||
Flash::writeBuffer(uint32_t dst_addr, uint32_t size)
|
||||
{
|
||||
_samba.writeBuffer(_onBufferA ? _pageBufferA : _pageBufferB, dst_addr + _addr, size);
|
||||
}
|
||||
|
||||
@@ -0,0 +1,180 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#ifndef _FLASH_H
|
||||
#define _FLASH_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <vector>
|
||||
#include <memory>
|
||||
#include <exception>
|
||||
|
||||
#include "Samba.h"
|
||||
#include "WordCopyApplet.h"
|
||||
|
||||
class FlashPageError : public std::exception
|
||||
{
|
||||
public:
|
||||
FlashPageError() : exception() {};
|
||||
const char* what() const throw() { return "Invalid flash page"; }
|
||||
};
|
||||
|
||||
class FlashRegionError : public std::exception
|
||||
{
|
||||
public:
|
||||
FlashRegionError() : exception() {};
|
||||
const char* what() const throw() { return "Invalid lock region"; }
|
||||
};
|
||||
|
||||
class FlashLockError : public std::exception
|
||||
{
|
||||
public:
|
||||
FlashLockError() : exception() {};
|
||||
const char* what() const throw() { return "Flash page is locked"; }
|
||||
};
|
||||
|
||||
class FlashCmdError : public std::exception
|
||||
{
|
||||
public:
|
||||
FlashCmdError() : exception() {};
|
||||
const char* what() const throw() { return "Flash command failed"; }
|
||||
};
|
||||
|
||||
class FlashTimeoutError : public std::exception
|
||||
{
|
||||
public:
|
||||
FlashTimeoutError() : exception() {};
|
||||
const char* what() const throw() { return "Flash command timeout"; }
|
||||
};
|
||||
|
||||
class BootFlashError : public std::exception
|
||||
{
|
||||
public:
|
||||
BootFlashError() : exception() {};
|
||||
const char* what() const throw() { return "Unable to clear boot flash for this device"; }
|
||||
|
||||
};
|
||||
|
||||
class FlashEraseError : public std::exception
|
||||
{
|
||||
public:
|
||||
FlashEraseError() : exception() {};
|
||||
const char* what() const throw() { return "Flash erase failed"; }
|
||||
|
||||
};
|
||||
|
||||
template<class T>
|
||||
class FlashOption
|
||||
{
|
||||
public:
|
||||
FlashOption() : _dirty(false) {}
|
||||
virtual ~FlashOption() {}
|
||||
void set(const T& value) { _value = value; _dirty = true; }
|
||||
const T& get() { return _value; }
|
||||
bool isDirty() { return _dirty; }
|
||||
|
||||
private:
|
||||
T _value;
|
||||
bool _dirty;
|
||||
};
|
||||
|
||||
class Flash
|
||||
{
|
||||
public:
|
||||
Flash(Samba& samba,
|
||||
const std::string& name,
|
||||
uint32_t addr, // Flash base address
|
||||
uint32_t pages, // Number of pages
|
||||
uint32_t size, // Page size in bytes
|
||||
uint32_t planes, // Number of flash planes
|
||||
uint32_t lockRegions, // Number of flash lock regions
|
||||
uint32_t user, // Address in SRAM where the applet and buffers will be placed
|
||||
uint32_t stack); // Address in SRAM where the applet stack will be placed
|
||||
virtual ~Flash() {}
|
||||
|
||||
const std::string& name() { return _name; }
|
||||
|
||||
virtual uint32_t address() { return _addr; }
|
||||
virtual uint32_t pageSize() { return _size; }
|
||||
virtual uint32_t numPages() { return _pages; }
|
||||
virtual uint32_t numPlanes() { return _planes; }
|
||||
virtual uint32_t totalSize() { return _size * _pages; }
|
||||
virtual uint32_t lockRegions() { return _lockRegions; }
|
||||
|
||||
virtual void eraseAll(uint32_t offset) = 0;
|
||||
virtual void eraseAuto(bool enable) = 0;
|
||||
|
||||
virtual std::vector<bool> getLockRegions() = 0;
|
||||
virtual void setLockRegions(const std::vector<bool>& regions);
|
||||
|
||||
virtual bool getSecurity() = 0;
|
||||
virtual void setSecurity();
|
||||
|
||||
virtual bool getBod() = 0;
|
||||
virtual void setBod(bool enable);
|
||||
virtual bool canBod() = 0;
|
||||
|
||||
virtual bool getBor() = 0;
|
||||
virtual void setBor(bool enable);
|
||||
virtual bool canBor() = 0;
|
||||
|
||||
virtual bool getBootFlash() = 0;
|
||||
virtual void setBootFlash(bool enable);
|
||||
virtual bool canBootFlash() = 0;
|
||||
|
||||
virtual void writeOptions() = 0;
|
||||
|
||||
virtual void writePage(uint32_t page) = 0;
|
||||
virtual void readPage(uint32_t page, uint8_t* data) = 0;
|
||||
|
||||
virtual void writeBuffer(uint32_t dst_addr, uint32_t size);
|
||||
virtual void loadBuffer(const uint8_t* data, uint16_t size);
|
||||
|
||||
protected:
|
||||
Samba& _samba;
|
||||
std::string _name;
|
||||
uint32_t _addr;
|
||||
uint32_t _pages;
|
||||
uint32_t _size;
|
||||
uint32_t _planes;
|
||||
uint32_t _lockRegions;
|
||||
uint32_t _user;
|
||||
WordCopyApplet _wordCopy;
|
||||
|
||||
FlashOption<bool> _bootFlash;
|
||||
FlashOption< std::vector<bool> > _regions;
|
||||
FlashOption<bool> _bod;
|
||||
FlashOption<bool> _bor;
|
||||
FlashOption<bool> _security;
|
||||
|
||||
bool _onBufferA;
|
||||
uint32_t _pageBufferA;
|
||||
uint32_t _pageBufferB;
|
||||
};
|
||||
|
||||
#endif // _FLASH_H
|
||||
@@ -0,0 +1,373 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#include <string>
|
||||
#include <exception>
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "Flasher.h"
|
||||
|
||||
using namespace std;
|
||||
|
||||
void
|
||||
FlasherInfo::print()
|
||||
{
|
||||
bool first;
|
||||
|
||||
printf("Device : %s\n", name.c_str());
|
||||
printf("Version : %s\n", version.c_str());
|
||||
printf("Address : 0x%x\n", address);
|
||||
printf("Pages : %d\n", numPages);
|
||||
printf("Page Size : %d bytes\n", pageSize);
|
||||
printf("Total Size : %dKB\n", totalSize / 1024);
|
||||
printf("Planes : %d\n", numPlanes);
|
||||
printf("Lock Regions : %zd\n", lockRegions.size());
|
||||
printf("Locked : ");
|
||||
first = true;
|
||||
for (uint32_t region = 0; region < lockRegions.size(); region++)
|
||||
{
|
||||
if (lockRegions[region])
|
||||
{
|
||||
printf("%s%d", first ? "" : ",", region);
|
||||
first = false;
|
||||
}
|
||||
}
|
||||
printf("%s\n", first ? "none" : "");
|
||||
printf("Security : %s\n", security ? "true" : "false");
|
||||
if (canBootFlash)
|
||||
printf("Boot Flash : %s\n", bootFlash ? "true" : "false");
|
||||
if (canBod)
|
||||
printf("BOD : %s\n", bod ? "true" : "false");
|
||||
if (canBor)
|
||||
printf("BOR : %s\n", bor ? "true" : "false");
|
||||
}
|
||||
|
||||
void
|
||||
Flasher::erase(uint32_t foffset)
|
||||
{
|
||||
_observer.onStatus("Erase flash\n");
|
||||
_flash->eraseAll(foffset);
|
||||
_flash->eraseAuto(false);
|
||||
}
|
||||
|
||||
void
|
||||
Flasher::write(const char* filename, uint32_t foffset)
|
||||
{
|
||||
FILE* infile;
|
||||
uint32_t pageSize = _flash->pageSize();
|
||||
uint32_t pageNum = 0;
|
||||
uint32_t numPages;
|
||||
long fsize;
|
||||
size_t fbytes;
|
||||
|
||||
if (foffset % pageSize != 0 || foffset >= _flash->totalSize())
|
||||
throw FlashOffsetError();
|
||||
|
||||
infile = fopen(filename, "rb");
|
||||
if (!infile)
|
||||
throw FileOpenError(errno);
|
||||
|
||||
try
|
||||
{
|
||||
if (fseek(infile, 0, SEEK_END) != 0 || (fsize = ftell(infile)) < 0)
|
||||
throw FileIoError(errno);
|
||||
|
||||
rewind(infile);
|
||||
|
||||
numPages = (fsize + pageSize - 1) / pageSize;
|
||||
if (numPages > _flash->numPages())
|
||||
throw FileSizeError();
|
||||
|
||||
_observer.onStatus("Write %ld bytes to flash (%u pages)\n", fsize, numPages);
|
||||
|
||||
if (_samba.canWriteBuffer())
|
||||
{
|
||||
uint32_t offset = 0;
|
||||
uint32_t bufferSize = _samba.writeBufferSize();
|
||||
uint8_t buffer[bufferSize];
|
||||
|
||||
while ((fbytes = fread(buffer, 1, bufferSize, infile)) > 0)
|
||||
{
|
||||
_observer.onProgress(offset / pageSize, numPages);
|
||||
|
||||
if (fbytes < bufferSize)
|
||||
{
|
||||
memset(buffer + fbytes, 0, bufferSize - fbytes);
|
||||
fbytes = (fbytes + pageSize - 1) / pageSize * pageSize;
|
||||
}
|
||||
|
||||
_flash->loadBuffer(buffer, fbytes);
|
||||
_flash->writeBuffer(foffset + offset, fbytes);
|
||||
offset += fbytes;
|
||||
}
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
uint8_t buffer[pageSize];
|
||||
uint32_t pageOffset = foffset / pageSize;
|
||||
|
||||
while ((fbytes = fread(buffer, 1, pageSize, infile)) > 0)
|
||||
{
|
||||
_observer.onProgress(pageNum, numPages);
|
||||
|
||||
_flash->loadBuffer(buffer, fbytes);
|
||||
_flash->writePage(pageOffset + pageNum);
|
||||
|
||||
pageNum++;
|
||||
if (pageNum == numPages || fbytes != pageSize)
|
||||
break;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
catch(...)
|
||||
{
|
||||
fclose(infile);
|
||||
throw;
|
||||
}
|
||||
|
||||
fclose(infile);
|
||||
_observer.onProgress(numPages, numPages);
|
||||
}
|
||||
|
||||
bool
|
||||
Flasher::verify(const char* filename, uint32_t& pageErrors, uint32_t& totalErrors, uint32_t foffset)
|
||||
{
|
||||
FILE* infile;
|
||||
uint32_t pageSize = _flash->pageSize();
|
||||
uint8_t bufferA[pageSize];
|
||||
uint8_t bufferB[pageSize];
|
||||
uint32_t pageNum = 0;
|
||||
uint32_t numPages;
|
||||
uint32_t pageOffset;
|
||||
uint32_t byteErrors = 0;
|
||||
uint16_t calcCrc = 0;
|
||||
uint16_t flashCrc;
|
||||
long fsize;
|
||||
size_t fbytes;
|
||||
|
||||
pageErrors = 0;
|
||||
totalErrors = 0;
|
||||
|
||||
if (foffset % pageSize != 0 || foffset >= _flash->totalSize())
|
||||
throw FlashOffsetError();
|
||||
|
||||
pageOffset = foffset / pageSize;
|
||||
|
||||
infile = fopen(filename, "rb");
|
||||
if (!infile)
|
||||
throw FileOpenError(errno);
|
||||
|
||||
try
|
||||
{
|
||||
if (fseek(infile, 0, SEEK_END) != 0 || (fsize = ftell(infile)) < 0)
|
||||
throw FileIoError(errno);
|
||||
|
||||
rewind(infile);
|
||||
|
||||
numPages = (fsize + pageSize - 1) / pageSize;
|
||||
if (numPages > _flash->numPages())
|
||||
throw FileSizeError();
|
||||
|
||||
_observer.onStatus("Verify %ld bytes of flash\n", fsize);
|
||||
|
||||
while ((fbytes = fread(bufferA, 1, pageSize, infile)) > 0)
|
||||
{
|
||||
byteErrors = 0;
|
||||
|
||||
_observer.onProgress(pageNum, numPages);
|
||||
|
||||
if (_samba.canChecksumBuffer())
|
||||
{
|
||||
for (uint32_t i = 0; i < fbytes; i++)
|
||||
calcCrc = _samba.checksumCalc(bufferA[i], calcCrc);
|
||||
|
||||
flashCrc = _samba.checksumBuffer((pageOffset + pageNum) * pageSize, fbytes);
|
||||
|
||||
if (flashCrc != calcCrc)
|
||||
{
|
||||
_flash->readPage(pageOffset + pageNum, bufferB);
|
||||
|
||||
for (uint32_t i = 0; i < fbytes; i++)
|
||||
{
|
||||
if (bufferA[i] != bufferB[i])
|
||||
byteErrors++;
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
_flash->readPage(pageOffset + pageNum, bufferB);
|
||||
|
||||
for (uint32_t i = 0; i < fbytes; i++)
|
||||
{
|
||||
if (bufferA[i] != bufferB[i])
|
||||
byteErrors++;
|
||||
}
|
||||
}
|
||||
|
||||
if (byteErrors != 0)
|
||||
{
|
||||
pageErrors++;
|
||||
totalErrors += byteErrors;
|
||||
}
|
||||
|
||||
pageNum++;
|
||||
if (pageNum == numPages || fbytes != pageSize)
|
||||
break;
|
||||
}
|
||||
}
|
||||
catch(...)
|
||||
{
|
||||
fclose(infile);
|
||||
throw;
|
||||
}
|
||||
|
||||
fclose(infile);
|
||||
|
||||
_observer.onProgress(numPages, numPages);
|
||||
|
||||
if (pageErrors != 0)
|
||||
return false;
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void
|
||||
Flasher::read(const char* filename, uint32_t fsize, uint32_t foffset)
|
||||
{
|
||||
FILE* outfile;
|
||||
uint32_t pageSize = _flash->pageSize();
|
||||
uint8_t buffer[pageSize];
|
||||
uint32_t pageNum = 0;
|
||||
uint32_t pageOffset;
|
||||
uint32_t numPages;
|
||||
size_t fbytes;
|
||||
|
||||
if (foffset % pageSize != 0 || foffset >= _flash->totalSize())
|
||||
throw FlashOffsetError();
|
||||
|
||||
pageOffset = foffset / pageSize;
|
||||
|
||||
if (fsize == 0)
|
||||
fsize = pageSize * (_flash->numPages() - pageOffset);
|
||||
|
||||
numPages = (fsize + pageSize - 1) / pageSize;
|
||||
if (pageOffset + numPages > _flash->numPages())
|
||||
throw FileSizeError();
|
||||
|
||||
outfile = fopen(filename, "wb");
|
||||
if (!outfile)
|
||||
throw FileOpenError(errno);
|
||||
|
||||
_observer.onStatus("Read %d bytes from flash\n", fsize);
|
||||
|
||||
try
|
||||
{
|
||||
for (pageNum = 0; pageNum < numPages; pageNum++)
|
||||
{
|
||||
_observer.onProgress(pageNum, numPages);
|
||||
|
||||
_flash->readPage(pageOffset + pageNum, buffer);
|
||||
|
||||
if (pageNum == numPages - 1 && fsize % pageSize > 0)
|
||||
pageSize = fsize % pageSize;
|
||||
fbytes = fwrite(buffer, 1, pageSize, outfile);
|
||||
if (fbytes != pageSize)
|
||||
throw FileShortError();
|
||||
}
|
||||
}
|
||||
catch(...)
|
||||
{
|
||||
fclose(outfile);
|
||||
throw;
|
||||
}
|
||||
|
||||
_observer.onProgress(numPages, numPages);
|
||||
|
||||
fclose(outfile);
|
||||
}
|
||||
|
||||
void
|
||||
Flasher::lock(string& regionArg, bool enable)
|
||||
{
|
||||
if (regionArg.empty())
|
||||
{
|
||||
_observer.onStatus("%s all regions\n", enable ? "Lock" : "Unlock");
|
||||
std::vector<bool> regions(_flash->lockRegions(), enable);
|
||||
_flash->setLockRegions(regions);
|
||||
}
|
||||
else
|
||||
{
|
||||
size_t pos = 0;
|
||||
size_t delim;
|
||||
uint32_t region;
|
||||
string sub;
|
||||
std::vector<bool> regions = _flash->getLockRegions();
|
||||
|
||||
do
|
||||
{
|
||||
delim = regionArg.find(',', pos);
|
||||
sub = regionArg.substr(pos, delim - pos);
|
||||
region = strtol(sub.c_str(), NULL, 0);
|
||||
_observer.onStatus("%s region %d\n", enable ? "Lock" : "Unlock", region);
|
||||
regions[region] = enable;
|
||||
pos = delim + 1;
|
||||
} while (delim != string::npos);
|
||||
|
||||
_flash->setLockRegions(regions);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
Flasher::info(FlasherInfo& info)
|
||||
{
|
||||
info.name = _flash->name();
|
||||
info.version = _samba.version();
|
||||
info.address = _flash->address();
|
||||
info.numPages = _flash->numPages();
|
||||
info.pageSize = _flash->pageSize();
|
||||
info.totalSize = _flash->numPages() * _flash->pageSize();
|
||||
info.numPlanes = _flash->numPlanes();
|
||||
info.security = _flash->getSecurity();
|
||||
info.bootFlash = _flash->getBootFlash();
|
||||
info.bod = _flash->getBod();
|
||||
info.bor = _flash->getBor();
|
||||
|
||||
info.canBootFlash = _flash->canBootFlash();
|
||||
info.canBod = _flash->canBod();
|
||||
info.canBor = _flash->canBor();
|
||||
info.canChipErase = _samba.canChipErase();
|
||||
info.canWriteBuffer = _samba.canWriteBuffer();
|
||||
info.canChecksumBuffer = _samba.canChecksumBuffer();
|
||||
info.lockRegions = _flash->getLockRegions();
|
||||
}
|
||||
@@ -0,0 +1,110 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#ifndef _FLASHER_H
|
||||
#define _FLASHER_H
|
||||
|
||||
#include <string>
|
||||
#include <exception>
|
||||
#include <vector>
|
||||
|
||||
#include "Device.h"
|
||||
#include "Flash.h"
|
||||
#include "Samba.h"
|
||||
#include "FileError.h"
|
||||
|
||||
class FlashOffsetError : public std::exception
|
||||
{
|
||||
public:
|
||||
FlashOffsetError() : std::exception() {};
|
||||
virtual const char* what() const throw() { return "Flash offset is invalid"; }
|
||||
};
|
||||
|
||||
class FlasherObserver
|
||||
{
|
||||
public:
|
||||
FlasherObserver() {}
|
||||
virtual ~FlasherObserver() {}
|
||||
|
||||
virtual void onStatus(const char *message, ...) = 0;
|
||||
virtual void onProgress(int num, int div) = 0;
|
||||
};
|
||||
|
||||
class FlasherInfo
|
||||
{
|
||||
public:
|
||||
FlasherInfo() {}
|
||||
virtual ~FlasherInfo() {}
|
||||
|
||||
void print();
|
||||
|
||||
std::string name;
|
||||
uint32_t chipId;
|
||||
uint32_t extChipId;
|
||||
std::string version;
|
||||
uint32_t address;
|
||||
uint32_t numPages;
|
||||
uint32_t pageSize;
|
||||
uint32_t totalSize;
|
||||
uint32_t numPlanes;
|
||||
|
||||
bool security;
|
||||
bool bootFlash;
|
||||
bool bod;
|
||||
bool bor;
|
||||
|
||||
bool canBootFlash;
|
||||
bool canBod;
|
||||
bool canBor;
|
||||
bool canChipErase;
|
||||
bool canWriteBuffer;
|
||||
bool canChecksumBuffer;
|
||||
|
||||
std::vector<bool> lockRegions;
|
||||
};
|
||||
|
||||
class Flasher
|
||||
{
|
||||
public:
|
||||
Flasher(Samba& samba, Device& device, FlasherObserver& observer) : _samba(samba), _flash(device.getFlash()), _observer(observer) {}
|
||||
virtual ~Flasher() {}
|
||||
|
||||
void erase(uint32_t foffset);
|
||||
void write(const char* filename, uint32_t foffset = 0);
|
||||
bool verify(const char* filename, uint32_t& pageErrors, uint32_t& totalErrors, uint32_t foffset = 0);
|
||||
void read(const char* filename, uint32_t fsize, uint32_t foffset = 0);
|
||||
void lock(std::string& regionArg, bool enable);
|
||||
void info(FlasherInfo& info);
|
||||
|
||||
private:
|
||||
Samba& _samba;
|
||||
Device::FlashPtr& _flash;
|
||||
FlasherObserver& _observer;
|
||||
};
|
||||
|
||||
#endif // _FLASHER_H
|
||||
@@ -0,0 +1,109 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#include "LinuxPortFactory.h"
|
||||
#include "PosixSerialPort.h"
|
||||
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#include <string>
|
||||
|
||||
LinuxPortFactory::LinuxPortFactory()
|
||||
{
|
||||
_dir = opendir("/dev");
|
||||
}
|
||||
|
||||
LinuxPortFactory::~LinuxPortFactory()
|
||||
{
|
||||
if (_dir)
|
||||
closedir(_dir);
|
||||
}
|
||||
|
||||
SerialPort::Ptr
|
||||
LinuxPortFactory::create(const std::string& name)
|
||||
{
|
||||
bool isUsb = false;
|
||||
|
||||
if (name.find("ttyUSB") != std::string::npos ||
|
||||
name.find("ttyACM") != std::string::npos)
|
||||
isUsb = true;
|
||||
|
||||
return create(name, isUsb);
|
||||
}
|
||||
|
||||
SerialPort::Ptr
|
||||
LinuxPortFactory::create(const std::string& name, bool isUsb)
|
||||
{
|
||||
return SerialPort::Ptr(new PosixSerialPort(name, isUsb));
|
||||
}
|
||||
|
||||
std::string
|
||||
LinuxPortFactory::begin()
|
||||
{
|
||||
if (!_dir)
|
||||
return end();
|
||||
|
||||
rewinddir(_dir);
|
||||
|
||||
return next();
|
||||
}
|
||||
|
||||
std::string
|
||||
LinuxPortFactory::next()
|
||||
{
|
||||
struct dirent* entry;
|
||||
|
||||
if (!_dir)
|
||||
return end();
|
||||
|
||||
while ((entry = readdir(_dir)))
|
||||
{
|
||||
if (strncmp("ttyUSB", entry->d_name, sizeof("ttyUSB") - 1) == 0)
|
||||
return std::string(entry->d_name);
|
||||
else if (strncmp("ttyACM", entry->d_name, sizeof("ttyACM") - 1) == 0)
|
||||
return std::string(entry->d_name);
|
||||
else if (strncmp("ttyS", entry->d_name, sizeof("ttyS") - 1) == 0)
|
||||
return std::string(entry->d_name);
|
||||
}
|
||||
|
||||
return end();
|
||||
}
|
||||
|
||||
std::string
|
||||
LinuxPortFactory::end()
|
||||
{
|
||||
return std::string();
|
||||
}
|
||||
|
||||
std::string
|
||||
LinuxPortFactory::def()
|
||||
{
|
||||
return std::string("/dev/ttyACM0");
|
||||
}
|
||||
|
||||
@@ -0,0 +1,60 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#ifndef _LINUXPORTFACTORY_H
|
||||
#define _LINUXPORTFACTORY_H
|
||||
|
||||
class LinuxPortFactory;
|
||||
#include "PortFactory.h"
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <dirent.h>
|
||||
|
||||
#include <string>
|
||||
|
||||
|
||||
class LinuxPortFactory : public PortFactoryBase
|
||||
{
|
||||
public:
|
||||
LinuxPortFactory();
|
||||
virtual ~LinuxPortFactory();
|
||||
|
||||
virtual std::string begin();
|
||||
virtual std::string end();
|
||||
virtual std::string next();
|
||||
virtual std::string def();
|
||||
|
||||
virtual SerialPort::Ptr create(const std::string& name);
|
||||
virtual SerialPort::Ptr create(const std::string& name, bool isUsb);
|
||||
|
||||
private:
|
||||
std::string _empty;
|
||||
DIR* _dir;
|
||||
};
|
||||
|
||||
#endif // _LINUXPORTFACTORY_H
|
||||
@@ -0,0 +1,68 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#ifndef _PORTFACTORY_H
|
||||
#define _PORTFACTORY_H
|
||||
|
||||
#include <string>
|
||||
|
||||
#include "SerialPort.h"
|
||||
|
||||
class PortFactoryBase
|
||||
{
|
||||
public:
|
||||
PortFactoryBase() {}
|
||||
virtual ~PortFactoryBase() {}
|
||||
|
||||
virtual std::string begin() = 0;
|
||||
virtual std::string end() = 0;
|
||||
virtual std::string next() = 0;
|
||||
virtual std::string def() = 0;
|
||||
|
||||
virtual SerialPort::Ptr create(const std::string& name) = 0;
|
||||
virtual SerialPort::Ptr create(const std::string& name, bool isUsb) = 0;
|
||||
};
|
||||
|
||||
#if defined(__WIN32__)
|
||||
#include "WinPortFactory.h"
|
||||
typedef WinPortFactory PortFactory;
|
||||
#elif defined(__linux__)
|
||||
#include "LinuxPortFactory.h"
|
||||
typedef LinuxPortFactory PortFactory;
|
||||
#elif defined(__APPLE__)
|
||||
#include "OSXPortFactory.h"
|
||||
typedef OSXPortFactory PortFactory;
|
||||
#elif defined(__OpenBSD__) || defined(__FreeBSD__)
|
||||
// This is likely to work (but not tested) for the other BSDs as well
|
||||
#include "BSDPortFactory.h"
|
||||
typedef BSDPortFactory PortFactory;
|
||||
#else
|
||||
#error "Platform is not supported"
|
||||
#endif
|
||||
|
||||
#endif // _PORTFACTORY_H
|
||||
@@ -0,0 +1,332 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#include "PosixSerialPort.h"
|
||||
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
#include <fcntl.h>
|
||||
#include <errno.h>
|
||||
#include <termios.h>
|
||||
#include <errno.h>
|
||||
#include <sys/ioctl.h>
|
||||
|
||||
#include <string>
|
||||
|
||||
#ifndef B460800
|
||||
#define B460800 460800
|
||||
#endif
|
||||
#ifndef B921600
|
||||
#define B921600 921600
|
||||
#endif
|
||||
|
||||
PosixSerialPort::PosixSerialPort(const std::string& name, bool isUsb) :
|
||||
SerialPort(name), _devfd(-1), _isUsb(isUsb), _timeout(0),
|
||||
_autoFlush(false)
|
||||
{
|
||||
}
|
||||
|
||||
PosixSerialPort::~PosixSerialPort()
|
||||
{
|
||||
if (_devfd >= 0)
|
||||
::close(_devfd);
|
||||
}
|
||||
|
||||
bool
|
||||
PosixSerialPort::open(int baud,
|
||||
int data,
|
||||
SerialPort::Parity parity,
|
||||
SerialPort::StopBit stop)
|
||||
{
|
||||
struct termios options;
|
||||
speed_t speed;
|
||||
// Try opening port assuming _name is full path. If it fails
|
||||
// try "/dev/" + _name
|
||||
_devfd = ::open(_name.c_str(), O_RDWR | O_NOCTTY | O_NDELAY);
|
||||
if (_devfd == -1)
|
||||
{
|
||||
std::string dev("/dev/");
|
||||
dev += _name;
|
||||
_devfd = ::open(dev.c_str(), O_RDWR | O_NOCTTY | O_NDELAY);
|
||||
if (_devfd == -1)
|
||||
return false;
|
||||
}
|
||||
|
||||
if (tcgetattr(_devfd, &options) == -1)
|
||||
{
|
||||
close();
|
||||
return false;
|
||||
}
|
||||
|
||||
switch (baud)
|
||||
{
|
||||
case 1200:
|
||||
speed = B1200;
|
||||
break;
|
||||
case 9600:
|
||||
speed = B9600;
|
||||
break;
|
||||
case 19200:
|
||||
speed = B19200;
|
||||
break;
|
||||
case 38400:
|
||||
speed = B38400;
|
||||
break;
|
||||
case 57600:
|
||||
speed = B57600;
|
||||
break;
|
||||
case 115200:
|
||||
speed = B115200;
|
||||
break;
|
||||
case 230400:
|
||||
speed = B230400;
|
||||
break;
|
||||
case 460800:
|
||||
speed = B460800;
|
||||
break;
|
||||
case 921600:
|
||||
speed = B921600;
|
||||
break;
|
||||
default:
|
||||
close();
|
||||
return false;
|
||||
}
|
||||
|
||||
if (cfsetispeed(&options, speed) || cfsetospeed(&options, speed))
|
||||
{
|
||||
close();
|
||||
return false;
|
||||
}
|
||||
|
||||
options.c_cflag |= (CLOCAL | CREAD);
|
||||
|
||||
switch (data)
|
||||
{
|
||||
case 8:
|
||||
options.c_cflag &= ~CSIZE;
|
||||
options.c_cflag |= CS8;
|
||||
break;
|
||||
case 7:
|
||||
options.c_cflag &= ~CSIZE;
|
||||
options.c_cflag |= CS7;
|
||||
break;
|
||||
default:
|
||||
close();
|
||||
return false;
|
||||
}
|
||||
|
||||
switch (parity)
|
||||
{
|
||||
case SerialPort::ParityNone:
|
||||
options.c_cflag &= ~PARENB;
|
||||
options.c_cflag &= ~PARODD;
|
||||
options.c_iflag &= ~(INPCK | ISTRIP);
|
||||
break;
|
||||
case SerialPort::ParityOdd:
|
||||
options.c_cflag |= PARENB;
|
||||
options.c_cflag |= PARODD;
|
||||
options.c_iflag |= (INPCK | ISTRIP);
|
||||
break;
|
||||
case SerialPort::ParityEven:
|
||||
options.c_cflag |= PARENB;
|
||||
options.c_cflag &= ~PARODD;
|
||||
options.c_iflag |= (INPCK | ISTRIP);
|
||||
break;
|
||||
default:
|
||||
close();
|
||||
return false;
|
||||
}
|
||||
|
||||
switch (stop)
|
||||
{
|
||||
case StopBitOne:
|
||||
options.c_cflag &= ~CSTOPB;
|
||||
break;
|
||||
case StopBitTwo:
|
||||
options.c_cflag |= CSTOPB;
|
||||
break;
|
||||
default:
|
||||
close();
|
||||
return false;
|
||||
}
|
||||
|
||||
// No hardware flow control
|
||||
options.c_cflag &= ~CRTSCTS;
|
||||
|
||||
// No software flow control
|
||||
options.c_iflag &= ~(IXON | IXOFF | IXANY);
|
||||
|
||||
// Raw input
|
||||
options.c_iflag &= ~(BRKINT | ICRNL);
|
||||
options.c_lflag &= ~(ICANON | IEXTEN | ECHO | ECHOE | ISIG);
|
||||
|
||||
// Raw output
|
||||
options.c_oflag &= ~OPOST;
|
||||
|
||||
// No wait time
|
||||
options.c_cc[VMIN] = 0;
|
||||
options.c_cc[VTIME] = 0;
|
||||
|
||||
if (tcsetattr(_devfd, TCSANOW, &options))
|
||||
{
|
||||
close();
|
||||
return false;
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void
|
||||
PosixSerialPort::close()
|
||||
{
|
||||
if (_devfd >= 0)
|
||||
::close(_devfd);
|
||||
_devfd = -1;
|
||||
}
|
||||
|
||||
int
|
||||
PosixSerialPort::read(uint8_t* buffer, int len)
|
||||
{
|
||||
fd_set fds;
|
||||
struct timeval tv;
|
||||
int numread = 0;
|
||||
int retval;
|
||||
|
||||
if (_devfd == -1)
|
||||
return -1;
|
||||
|
||||
while (numread < len)
|
||||
{
|
||||
FD_ZERO(&fds);
|
||||
FD_SET(_devfd, &fds);
|
||||
|
||||
tv.tv_sec = _timeout / 1000;
|
||||
tv.tv_usec = (_timeout % 1000) * 1000;
|
||||
|
||||
retval = select(_devfd + 1, &fds, NULL, NULL, &tv);
|
||||
|
||||
if (retval < 0)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
else if (retval == 0)
|
||||
{
|
||||
return numread;
|
||||
}
|
||||
else if (FD_ISSET(_devfd, &fds))
|
||||
{
|
||||
retval = ::read(_devfd, (uint8_t*) buffer + numread, len - numread);
|
||||
if (retval < 0)
|
||||
return -1;
|
||||
numread += retval;
|
||||
}
|
||||
}
|
||||
|
||||
return numread;
|
||||
}
|
||||
|
||||
int
|
||||
PosixSerialPort::write(const uint8_t* buffer, int len)
|
||||
{
|
||||
if (_devfd == -1)
|
||||
return -1;
|
||||
|
||||
int res = ::write(_devfd, buffer, len);
|
||||
// Used on macos to avoid upload errors
|
||||
if (_autoFlush)
|
||||
flush();
|
||||
return res;
|
||||
}
|
||||
|
||||
int
|
||||
PosixSerialPort::get()
|
||||
{
|
||||
uint8_t byte;
|
||||
|
||||
if (_devfd == -1)
|
||||
return -1;
|
||||
|
||||
if (read(&byte, 1) != 1)
|
||||
return -1;
|
||||
|
||||
return byte;
|
||||
}
|
||||
|
||||
int
|
||||
PosixSerialPort::put(int c)
|
||||
{
|
||||
uint8_t byte;
|
||||
|
||||
byte = c;
|
||||
return write(&byte, 1);
|
||||
}
|
||||
|
||||
void
|
||||
PosixSerialPort::flush()
|
||||
{
|
||||
// There isn't a reliable way to flush on a file descriptor
|
||||
// so we just wait it out. One millisecond is the USB poll
|
||||
// interval so that should cover it.
|
||||
usleep(1000);
|
||||
}
|
||||
|
||||
bool
|
||||
PosixSerialPort::timeout(int millisecs)
|
||||
{
|
||||
_timeout = millisecs;
|
||||
return true;
|
||||
}
|
||||
|
||||
void
|
||||
PosixSerialPort::setDTR(bool dtr)
|
||||
{
|
||||
if (_devfd == -1)
|
||||
return;
|
||||
|
||||
int iFlags = TIOCM_DTR;
|
||||
|
||||
ioctl(_devfd, (dtr ? TIOCMBIS : TIOCMBIC), &iFlags);
|
||||
}
|
||||
|
||||
void
|
||||
PosixSerialPort::setRTS(bool rts)
|
||||
{
|
||||
if (_devfd == -1)
|
||||
return;
|
||||
|
||||
int iFlags = TIOCM_RTS;
|
||||
|
||||
ioctl(_devfd, (rts ? TIOCMBIS : TIOCMBIC), &iFlags);
|
||||
}
|
||||
|
||||
void
|
||||
PosixSerialPort::setAutoFlush(bool autoflush)
|
||||
{
|
||||
_autoFlush = autoflush;
|
||||
}
|
||||
@@ -0,0 +1,66 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#ifndef _POSIXSERIALPORT_H
|
||||
#define _POSIXSERIALPORT_H
|
||||
|
||||
#include "SerialPort.h"
|
||||
|
||||
class PosixSerialPort : public SerialPort
|
||||
{
|
||||
public:
|
||||
PosixSerialPort(const std::string& name, bool isUsb);
|
||||
virtual ~PosixSerialPort();
|
||||
|
||||
bool open(int baud = 115200,
|
||||
int data = 8,
|
||||
SerialPort::Parity parity = SerialPort::ParityNone,
|
||||
SerialPort::StopBit stop = SerialPort::StopBitOne);
|
||||
void close();
|
||||
|
||||
bool isUsb() { return _isUsb; };
|
||||
|
||||
int read(uint8_t* data, int size);
|
||||
int write(const uint8_t* data, int size);
|
||||
int get();
|
||||
int put(int c);
|
||||
|
||||
bool timeout(int millisecs);
|
||||
void flush();
|
||||
void setDTR(bool dtr);
|
||||
void setRTS(bool rts);
|
||||
void setAutoFlush(bool autoflush);
|
||||
|
||||
private:
|
||||
int _devfd;
|
||||
bool _isUsb;
|
||||
int _timeout;
|
||||
bool _autoFlush;
|
||||
};
|
||||
|
||||
#endif // _POSIXSERIALPORT_H
|
||||
@@ -0,0 +1,672 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#include "Samba.h"
|
||||
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <stdlib.h>
|
||||
#include <ctype.h>
|
||||
#include <unistd.h>
|
||||
#include <errno.h>
|
||||
|
||||
using namespace std;
|
||||
|
||||
// XMODEM definitions
|
||||
#define BLK_SIZE 128
|
||||
#define MAX_RETRIES 5
|
||||
#define SOH 0x01
|
||||
#define EOT 0x04
|
||||
#define ACK 0x06
|
||||
#define NAK 0x15
|
||||
#define CAN 0x18
|
||||
#define START 'C'
|
||||
|
||||
#define TIMEOUT_QUICK 100
|
||||
#define TIMEOUT_NORMAL 1000
|
||||
#define TIMEOUT_LONG 5000
|
||||
|
||||
#define min(a, b) ((a) < (b) ? (a) : (b))
|
||||
|
||||
Samba::Samba() :
|
||||
_canChipErase(false),
|
||||
_canWriteBuffer(false),
|
||||
_canChecksumBuffer(false),
|
||||
_readBufferSize(0),
|
||||
_debug(false),
|
||||
_isUsb(false)
|
||||
{
|
||||
}
|
||||
|
||||
Samba::~Samba()
|
||||
{
|
||||
}
|
||||
|
||||
bool
|
||||
Samba::init()
|
||||
{
|
||||
uint8_t cmd[3];
|
||||
|
||||
_port->timeout(TIMEOUT_QUICK);
|
||||
|
||||
// Flush garbage
|
||||
uint8_t dummy[1024];
|
||||
_port->read(dummy, sizeof(dummy));
|
||||
|
||||
if (!_isUsb)
|
||||
{
|
||||
if (_debug)
|
||||
printf("Send auto-baud\n");
|
||||
|
||||
// RS-232 auto-baud sequence
|
||||
_port->put(0x80);
|
||||
_port->get();
|
||||
_port->put(0x80);
|
||||
_port->get();
|
||||
_port->put('#');
|
||||
_port->read(cmd, 3);
|
||||
}
|
||||
|
||||
// Set binary mode
|
||||
if (_debug)
|
||||
printf("Set binary mode\n");
|
||||
cmd[0] = 'N';
|
||||
cmd[1] = '#';
|
||||
_port->write(cmd, 2);
|
||||
_port->read(cmd, 2);
|
||||
|
||||
std::string ver;
|
||||
try
|
||||
{
|
||||
ver = version();
|
||||
}
|
||||
catch(SambaError& err)
|
||||
{
|
||||
return false;
|
||||
}
|
||||
|
||||
std::size_t extIndex = ver.find("[Arduino:");
|
||||
if (extIndex != string::npos)
|
||||
{
|
||||
extIndex += 9;
|
||||
while (ver[extIndex] != ']')
|
||||
{
|
||||
switch (ver[extIndex])
|
||||
{
|
||||
case 'X': _canChipErase = true; break;
|
||||
case 'Y': _canWriteBuffer = true; break;
|
||||
case 'Z': _canChecksumBuffer = true; break;
|
||||
}
|
||||
extIndex++;
|
||||
}
|
||||
|
||||
// All SAMD-based Arduino/AdaFruit boards have a bug in their bootloader
|
||||
// that trying to read 64 bytes or more over USB corrupts the data.
|
||||
// We must limit these boards to read chunks of 63 bytes.
|
||||
if (_isUsb)
|
||||
_readBufferSize = 63;
|
||||
}
|
||||
|
||||
_port->timeout(TIMEOUT_NORMAL);
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
bool
|
||||
Samba::connect(SerialPort::Ptr port, int bps)
|
||||
{
|
||||
_port = move(port);
|
||||
|
||||
// Try to connect at a high speed if USB
|
||||
_isUsb = _port->isUsb();
|
||||
if (_isUsb)
|
||||
{
|
||||
if (_port->open(921600) && init())
|
||||
{
|
||||
if (_debug)
|
||||
printf("Connected at 921600 baud\n");
|
||||
return true;
|
||||
}
|
||||
else
|
||||
{
|
||||
_port->close();
|
||||
}
|
||||
}
|
||||
_isUsb = false;
|
||||
|
||||
// Try the serial port at slower speed
|
||||
if (_port->open(bps) && init())
|
||||
{
|
||||
if (_debug)
|
||||
printf("Connected at %d baud\n", bps);
|
||||
return true;
|
||||
}
|
||||
|
||||
disconnect();
|
||||
return false;
|
||||
}
|
||||
|
||||
void
|
||||
Samba::disconnect()
|
||||
{
|
||||
_port->close();
|
||||
_port.release();
|
||||
}
|
||||
|
||||
void
|
||||
Samba::writeByte(uint32_t addr, uint8_t value)
|
||||
{
|
||||
uint8_t cmd[14];
|
||||
|
||||
if (_debug)
|
||||
printf("%s(addr=%#x,value=%#x)\n", __FUNCTION__, addr, value);
|
||||
|
||||
snprintf((char*) cmd, sizeof(cmd), "O%08X,%02X#", addr, value);
|
||||
if (_port->write(cmd, sizeof(cmd) - 1) != sizeof(cmd) - 1)
|
||||
throw SambaError();
|
||||
|
||||
// The SAM firmware has a bug that if the command and binary data
|
||||
// are received in the same USB data packet, then the firmware
|
||||
// gets confused. Even though the writes are separated in the code,
|
||||
// USB drivers often do write combining which can put them together
|
||||
// in the same USB data packet. To avoid this, we call the serial
|
||||
// port object's flush method before writing the data.
|
||||
if (_isUsb)
|
||||
_port->flush();
|
||||
}
|
||||
|
||||
uint8_t
|
||||
Samba::readByte(uint32_t addr)
|
||||
{
|
||||
uint8_t cmd[13];
|
||||
uint8_t value;
|
||||
|
||||
snprintf((char*) cmd, sizeof(cmd), "o%08X,4#", addr);
|
||||
if (_port->write(cmd, sizeof(cmd) - 1) != sizeof(cmd) - 1)
|
||||
throw SambaError();
|
||||
if (_port->read(cmd, sizeof(uint8_t)) != sizeof(uint8_t))
|
||||
throw SambaError();
|
||||
|
||||
value = cmd[0];
|
||||
|
||||
if (_debug)
|
||||
printf("%s(addr=%#x)=%#x\n", __FUNCTION__, addr, value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
|
||||
void
|
||||
Samba::writeWord(uint32_t addr, uint32_t value)
|
||||
{
|
||||
uint8_t cmd[20];
|
||||
|
||||
if (_debug)
|
||||
printf("%s(addr=%#x,value=%#x)\n", __FUNCTION__, addr, value);
|
||||
|
||||
snprintf((char*) cmd, sizeof(cmd), "W%08X,%08X#", addr, value);
|
||||
if (_port->write(cmd, sizeof(cmd) - 1) != sizeof(cmd) - 1)
|
||||
throw SambaError();
|
||||
|
||||
// The SAM firmware has a bug that if the command and binary data
|
||||
// are received in the same USB data packet, then the firmware
|
||||
// gets confused. Even though the writes are sperated in the code,
|
||||
// USB drivers often do write combining which can put them together
|
||||
// in the same USB data packet. To avoid this, we call the serial
|
||||
// port object's flush method before writing the data.
|
||||
if (_isUsb)
|
||||
_port->flush();
|
||||
}
|
||||
|
||||
|
||||
uint32_t
|
||||
Samba::readWord(uint32_t addr)
|
||||
{
|
||||
uint8_t cmd[13];
|
||||
uint32_t value;
|
||||
|
||||
snprintf((char*) cmd, sizeof(cmd), "w%08X,4#", addr);
|
||||
if (_port->write(cmd, sizeof(cmd) - 1) != sizeof(cmd) - 1)
|
||||
throw SambaError();
|
||||
if (_port->read(cmd, sizeof(uint32_t)) != sizeof(uint32_t))
|
||||
throw SambaError();
|
||||
|
||||
value = (cmd[3] << 24 | cmd[2] << 16 | cmd[1] << 8 | cmd[0] << 0);
|
||||
|
||||
if (_debug)
|
||||
printf("%s(addr=%#x)=%#x\n", __FUNCTION__, addr, value);
|
||||
|
||||
return value;
|
||||
}
|
||||
|
||||
static const uint16_t crc16Table[256] = {
|
||||
0x0000,0x1021,0x2042,0x3063,0x4084,0x50a5,0x60c6,0x70e7,
|
||||
0x8108,0x9129,0xa14a,0xb16b,0xc18c,0xd1ad,0xe1ce,0xf1ef,
|
||||
0x1231,0x0210,0x3273,0x2252,0x52b5,0x4294,0x72f7,0x62d6,
|
||||
0x9339,0x8318,0xb37b,0xa35a,0xd3bd,0xc39c,0xf3ff,0xe3de,
|
||||
0x2462,0x3443,0x0420,0x1401,0x64e6,0x74c7,0x44a4,0x5485,
|
||||
0xa56a,0xb54b,0x8528,0x9509,0xe5ee,0xf5cf,0xc5ac,0xd58d,
|
||||
0x3653,0x2672,0x1611,0x0630,0x76d7,0x66f6,0x5695,0x46b4,
|
||||
0xb75b,0xa77a,0x9719,0x8738,0xf7df,0xe7fe,0xd79d,0xc7bc,
|
||||
0x48c4,0x58e5,0x6886,0x78a7,0x0840,0x1861,0x2802,0x3823,
|
||||
0xc9cc,0xd9ed,0xe98e,0xf9af,0x8948,0x9969,0xa90a,0xb92b,
|
||||
0x5af5,0x4ad4,0x7ab7,0x6a96,0x1a71,0x0a50,0x3a33,0x2a12,
|
||||
0xdbfd,0xcbdc,0xfbbf,0xeb9e,0x9b79,0x8b58,0xbb3b,0xab1a,
|
||||
0x6ca6,0x7c87,0x4ce4,0x5cc5,0x2c22,0x3c03,0x0c60,0x1c41,
|
||||
0xedae,0xfd8f,0xcdec,0xddcd,0xad2a,0xbd0b,0x8d68,0x9d49,
|
||||
0x7e97,0x6eb6,0x5ed5,0x4ef4,0x3e13,0x2e32,0x1e51,0x0e70,
|
||||
0xff9f,0xefbe,0xdfdd,0xcffc,0xbf1b,0xaf3a,0x9f59,0x8f78,
|
||||
0x9188,0x81a9,0xb1ca,0xa1eb,0xd10c,0xc12d,0xf14e,0xe16f,
|
||||
0x1080,0x00a1,0x30c2,0x20e3,0x5004,0x4025,0x7046,0x6067,
|
||||
0x83b9,0x9398,0xa3fb,0xb3da,0xc33d,0xd31c,0xe37f,0xf35e,
|
||||
0x02b1,0x1290,0x22f3,0x32d2,0x4235,0x5214,0x6277,0x7256,
|
||||
0xb5ea,0xa5cb,0x95a8,0x8589,0xf56e,0xe54f,0xd52c,0xc50d,
|
||||
0x34e2,0x24c3,0x14a0,0x0481,0x7466,0x6447,0x5424,0x4405,
|
||||
0xa7db,0xb7fa,0x8799,0x97b8,0xe75f,0xf77e,0xc71d,0xd73c,
|
||||
0x26d3,0x36f2,0x0691,0x16b0,0x6657,0x7676,0x4615,0x5634,
|
||||
0xd94c,0xc96d,0xf90e,0xe92f,0x99c8,0x89e9,0xb98a,0xa9ab,
|
||||
0x5844,0x4865,0x7806,0x6827,0x18c0,0x08e1,0x3882,0x28a3,
|
||||
0xcb7d,0xdb5c,0xeb3f,0xfb1e,0x8bf9,0x9bd8,0xabbb,0xbb9a,
|
||||
0x4a75,0x5a54,0x6a37,0x7a16,0x0af1,0x1ad0,0x2ab3,0x3a92,
|
||||
0xfd2e,0xed0f,0xdd6c,0xcd4d,0xbdaa,0xad8b,0x9de8,0x8dc9,
|
||||
0x7c26,0x6c07,0x5c64,0x4c45,0x3ca2,0x2c83,0x1ce0,0x0cc1,
|
||||
0xef1f,0xff3e,0xcf5d,0xdf7c,0xaf9b,0xbfba,0x8fd9,0x9ff8,
|
||||
0x6e17,0x7e36,0x4e55,0x5e74,0x2e93,0x3eb2,0x0ed1,0x1ef0
|
||||
};
|
||||
|
||||
uint16_t
|
||||
Samba::crc16Calc(const uint8_t *data, int len)
|
||||
{
|
||||
uint16_t crc16 = 0;
|
||||
|
||||
while (len-- > 0)
|
||||
crc16 = (crc16 << 8) ^ crc16Table[((crc16 >> 8) ^ *(uint8_t*) data++) & 0xff];
|
||||
return crc16;
|
||||
}
|
||||
|
||||
bool
|
||||
Samba::crc16Check(const uint8_t *blk)
|
||||
{
|
||||
uint16_t crc16;
|
||||
|
||||
crc16 = blk[BLK_SIZE + 3] << 8 | blk[BLK_SIZE + 4];
|
||||
return (crc16Calc(&blk[3], BLK_SIZE) == crc16);
|
||||
}
|
||||
|
||||
void
|
||||
Samba::crc16Add(uint8_t *blk)
|
||||
{
|
||||
uint16_t crc16;
|
||||
|
||||
crc16 = crc16Calc(&blk[3], BLK_SIZE);
|
||||
blk[BLK_SIZE + 3] = (crc16 >> 8) & 0xff;
|
||||
blk[BLK_SIZE + 4] = crc16 & 0xff;
|
||||
}
|
||||
|
||||
uint16_t
|
||||
Samba::checksumCalc(uint8_t data, uint16_t crc16) {
|
||||
return (crc16 << 8) ^ crc16Table[((crc16 >> 8) ^ data) & 0xff];
|
||||
}
|
||||
|
||||
void
|
||||
Samba::readXmodem(uint8_t* buffer, int size)
|
||||
{
|
||||
uint8_t blk[BLK_SIZE + 5];
|
||||
uint32_t blkNum = 1;
|
||||
int retries;
|
||||
int bytes;
|
||||
|
||||
while (size > 0)
|
||||
{
|
||||
for (retries = 0; retries < MAX_RETRIES; retries++)
|
||||
{
|
||||
if (blkNum == 1)
|
||||
_port->put(START);
|
||||
|
||||
bytes = _port->read(blk, sizeof(blk));
|
||||
if (bytes == sizeof(blk) &&
|
||||
blk[0] == SOH &&
|
||||
blk[1] == (blkNum & 0xff) &&
|
||||
crc16Check(blk))
|
||||
break;
|
||||
|
||||
if (blkNum != 1)
|
||||
_port->put(NAK);
|
||||
}
|
||||
if (retries == MAX_RETRIES)
|
||||
throw SambaError();
|
||||
|
||||
_port->put(ACK);
|
||||
|
||||
memmove(buffer, &blk[3], min(size, BLK_SIZE));
|
||||
buffer += BLK_SIZE;
|
||||
size -= BLK_SIZE;
|
||||
blkNum++;
|
||||
}
|
||||
|
||||
for (retries = 0; retries < MAX_RETRIES; retries++)
|
||||
{
|
||||
if (_port->get() == EOT)
|
||||
{
|
||||
_port->put(ACK);
|
||||
break;
|
||||
}
|
||||
_port->put(NAK);
|
||||
}
|
||||
if (retries == MAX_RETRIES)
|
||||
throw SambaError();
|
||||
}
|
||||
|
||||
void
|
||||
Samba::writeXmodem(const uint8_t* buffer, int size)
|
||||
{
|
||||
uint8_t blk[BLK_SIZE + 5];
|
||||
uint32_t blkNum = 1;
|
||||
int retries;
|
||||
int bytes;
|
||||
|
||||
for (retries = 0; retries < MAX_RETRIES; retries++)
|
||||
{
|
||||
if (_port->get() == START)
|
||||
break;
|
||||
}
|
||||
if (retries == MAX_RETRIES)
|
||||
throw SambaError();
|
||||
|
||||
while (size > 0)
|
||||
{
|
||||
blk[0] = SOH;
|
||||
blk[1] = (blkNum & 0xff);
|
||||
blk[2] = ~(blkNum & 0xff);
|
||||
memmove(&blk[3], buffer, min(size, BLK_SIZE));
|
||||
if (size < BLK_SIZE)
|
||||
memset(&blk[3] + size, 0, BLK_SIZE - size);
|
||||
crc16Add(blk);
|
||||
|
||||
for (retries = 0; retries < MAX_RETRIES; retries++)
|
||||
{
|
||||
bytes = _port->write(blk, sizeof(blk));
|
||||
if (bytes != sizeof(blk))
|
||||
throw SambaError();
|
||||
|
||||
if (_port->get() == ACK)
|
||||
break;
|
||||
}
|
||||
|
||||
if (retries == MAX_RETRIES)
|
||||
throw SambaError();
|
||||
|
||||
buffer += BLK_SIZE;
|
||||
size -= BLK_SIZE;
|
||||
blkNum++;
|
||||
}
|
||||
|
||||
for (retries = 0; retries < MAX_RETRIES; retries++)
|
||||
{
|
||||
_port->put(EOT);
|
||||
if (_port->get() == ACK)
|
||||
break;
|
||||
}
|
||||
if (retries == MAX_RETRIES)
|
||||
throw SambaError();
|
||||
}
|
||||
|
||||
void
|
||||
Samba::readBinary(uint8_t* buffer, int size)
|
||||
{
|
||||
if (_port->read(buffer, size) != size)
|
||||
throw SambaError();
|
||||
}
|
||||
|
||||
void
|
||||
Samba::writeBinary(const uint8_t* buffer, int size)
|
||||
{
|
||||
while (size)
|
||||
{
|
||||
int written = _port->write(buffer, size);
|
||||
if (written <= 0)
|
||||
throw SambaError();
|
||||
buffer += written;
|
||||
size -= written;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
Samba::read(uint32_t addr, uint8_t* buffer, int size)
|
||||
{
|
||||
uint8_t cmd[20];
|
||||
int chunk;
|
||||
|
||||
if (_debug)
|
||||
printf("%s(addr=%#x,size=%#x)\n", __FUNCTION__, addr, size);
|
||||
|
||||
// The SAM firmware has a bug reading powers of 2 over 32 bytes
|
||||
// via USB. If that is the case here, then read the first byte
|
||||
// with a readByte and then read one less than the requested size.
|
||||
if (_isUsb && _readBufferSize == 0 && size > 32 && !(size & (size - 1)))
|
||||
{
|
||||
*buffer = readByte(addr);
|
||||
addr++;
|
||||
buffer++;
|
||||
size--;
|
||||
}
|
||||
|
||||
while (size > 0)
|
||||
{
|
||||
// Handle any limitations on the size of the read
|
||||
if (_readBufferSize > 0 && size > _readBufferSize)
|
||||
chunk = _readBufferSize;
|
||||
else
|
||||
chunk = size;
|
||||
|
||||
snprintf((char*) cmd, sizeof(cmd), "R%08X,%08X#", addr, chunk);
|
||||
if (_port->write(cmd, sizeof(cmd) - 1) != sizeof(cmd) - 1)
|
||||
throw SambaError();
|
||||
|
||||
if (_isUsb)
|
||||
readBinary(buffer, chunk);
|
||||
else
|
||||
readXmodem(buffer, chunk);
|
||||
|
||||
size -= chunk;
|
||||
addr += chunk;
|
||||
buffer += chunk;
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
Samba::write(uint32_t addr, const uint8_t* buffer, int size)
|
||||
{
|
||||
uint8_t cmd[20];
|
||||
|
||||
if (_debug)
|
||||
printf("%s(addr=%#x,size=%#x)\n", __FUNCTION__, addr, size);
|
||||
|
||||
snprintf((char*) cmd, sizeof(cmd), "S%08X,%08X#", addr, size);
|
||||
if (_port->write(cmd, sizeof(cmd) - 1) != sizeof(cmd) - 1)
|
||||
throw SambaError();
|
||||
|
||||
// The SAM firmware has a bug that if the command and binary data
|
||||
// are received in the same USB data packet, then the firmware
|
||||
// gets confused. Even though the writes are separated in the code,
|
||||
// USB drivers often do write combining which can put them together
|
||||
// in the same USB data packet. To avoid this, we call the serial
|
||||
// port object's flush method before writing the data.
|
||||
if (_isUsb)
|
||||
{
|
||||
_port->flush();
|
||||
writeBinary(buffer, size);
|
||||
}
|
||||
else
|
||||
{
|
||||
writeXmodem(buffer, size);
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
Samba::go(uint32_t addr)
|
||||
{
|
||||
uint8_t cmd[11];
|
||||
|
||||
if (_debug)
|
||||
printf("%s(addr=%#x)\n", __FUNCTION__, addr);
|
||||
|
||||
snprintf((char*) cmd, sizeof(cmd), "G%08X#", addr);
|
||||
if (_port->write(cmd, sizeof(cmd) - 1) != sizeof(cmd) - 1)
|
||||
throw SambaError();
|
||||
|
||||
// The SAM firmware can get confused if another command is
|
||||
// received in the same USB data packet as the go command
|
||||
// so we flush after writing the command over USB.
|
||||
if (_isUsb)
|
||||
_port->flush();
|
||||
}
|
||||
|
||||
std::string
|
||||
Samba::version()
|
||||
{
|
||||
uint8_t cmd[256];
|
||||
char* str;
|
||||
int size;
|
||||
int pos;
|
||||
|
||||
cmd[0] = 'V';
|
||||
cmd[1] = '#';
|
||||
_port->write(cmd, 2);
|
||||
|
||||
_port->timeout(TIMEOUT_QUICK);
|
||||
size = _port->read(cmd, sizeof(cmd) - 1);
|
||||
_port->timeout(TIMEOUT_NORMAL);
|
||||
if (size <= 0)
|
||||
throw SambaError();
|
||||
|
||||
str = (char*) cmd;
|
||||
for (pos = 0; pos < size; pos++)
|
||||
{
|
||||
if (!isprint(str[pos]))
|
||||
break;
|
||||
}
|
||||
str[pos] = '\0';
|
||||
|
||||
std::string ver(str);
|
||||
|
||||
if (_debug)
|
||||
printf("%s()=%s\n", __FUNCTION__, ver.c_str());
|
||||
|
||||
return ver;
|
||||
}
|
||||
|
||||
void
|
||||
Samba::chipErase(uint32_t start_addr)
|
||||
{
|
||||
if (!_canChipErase)
|
||||
throw SambaError();
|
||||
|
||||
uint8_t cmd[64];
|
||||
|
||||
if (_debug)
|
||||
printf("%s(addr=%#x)\n", __FUNCTION__, start_addr);
|
||||
|
||||
int l = snprintf((char*) cmd, sizeof(cmd), "X%08X#", start_addr);
|
||||
if (_port->write(cmd, l) != l)
|
||||
throw SambaError();
|
||||
_port->timeout(TIMEOUT_LONG);
|
||||
_port->read(cmd, 3); // Expects "X\n\r"
|
||||
_port->timeout(TIMEOUT_NORMAL);
|
||||
if (cmd[0] != 'X')
|
||||
throw SambaError();
|
||||
}
|
||||
|
||||
void
|
||||
Samba::writeBuffer(uint32_t src_addr, uint32_t dst_addr, uint32_t size)
|
||||
{
|
||||
if (!_canWriteBuffer)
|
||||
throw SambaError();
|
||||
|
||||
if (size > checksumBufferSize())
|
||||
throw SambaError();
|
||||
|
||||
if (_debug)
|
||||
printf("%s(scr_addr=%#x, dst_addr=%#x, size=%#x)\n", __FUNCTION__, src_addr, dst_addr, size);
|
||||
|
||||
uint8_t cmd[64];
|
||||
int l = snprintf((char*) cmd, sizeof(cmd), "Y%08X,0#", src_addr);
|
||||
if (_port->write(cmd, l) != l)
|
||||
throw SambaError();
|
||||
_port->timeout(TIMEOUT_QUICK);
|
||||
cmd[0] = 0;
|
||||
_port->read(cmd, 3); // Expects "Y\n\r"
|
||||
_port->timeout(TIMEOUT_NORMAL);
|
||||
if (cmd[0] != 'Y')
|
||||
throw SambaError();
|
||||
|
||||
l = snprintf((char*) cmd, sizeof(cmd), "Y%08X,%08X#", dst_addr, size);
|
||||
if (_port->write(cmd, l) != l)
|
||||
throw SambaError();
|
||||
_port->timeout(TIMEOUT_LONG);
|
||||
cmd[0] = 0;
|
||||
_port->read(cmd, 3); // Expects "Y\n\r"
|
||||
_port->timeout(TIMEOUT_NORMAL);
|
||||
if (cmd[0] != 'Y')
|
||||
throw SambaError();
|
||||
}
|
||||
|
||||
uint16_t
|
||||
Samba::checksumBuffer(uint32_t start_addr, uint32_t size)
|
||||
{
|
||||
if (!_canChecksumBuffer)
|
||||
throw SambaError();
|
||||
|
||||
if (size > checksumBufferSize())
|
||||
throw SambaError();
|
||||
|
||||
if (_debug)
|
||||
printf("%s(start_addr=%#x, size=%#x) = ", __FUNCTION__, start_addr, size);
|
||||
|
||||
uint8_t cmd[64];
|
||||
int l = snprintf((char*) cmd, sizeof(cmd), "Z%08X,%08X#", start_addr, size);
|
||||
if (_port->write(cmd, l) != l)
|
||||
throw SambaError();
|
||||
_port->timeout(TIMEOUT_LONG);
|
||||
cmd[0] = 0;
|
||||
_port->read(cmd, 12); // Expects "Z00000000#\n\r"
|
||||
_port->timeout(TIMEOUT_NORMAL);
|
||||
if (cmd[0] != 'Z')
|
||||
throw SambaError();
|
||||
|
||||
cmd[9] = 0;
|
||||
errno = 0;
|
||||
uint32_t res = strtol((char*) &cmd[1], NULL, 16);
|
||||
if (errno != 0)
|
||||
throw SambaError();
|
||||
if (_debug)
|
||||
printf("%x\n", res);
|
||||
return res;
|
||||
}
|
||||
|
||||
@@ -0,0 +1,115 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
#ifndef _SAMBA_H
|
||||
#define _SAMBA_H
|
||||
|
||||
#include <string>
|
||||
#include <stdint.h>
|
||||
#include <exception>
|
||||
#include <memory>
|
||||
|
||||
#include "SerialPort.h"
|
||||
|
||||
class SambaError : public std::exception
|
||||
{
|
||||
public:
|
||||
SambaError() : exception() {};
|
||||
const char* what() const throw() { return "SAM-BA operation failed"; }
|
||||
};
|
||||
|
||||
|
||||
|
||||
class Samba
|
||||
{
|
||||
public:
|
||||
Samba();
|
||||
virtual ~Samba();
|
||||
|
||||
bool connect(SerialPort::Ptr port, int bps = 115200);
|
||||
void disconnect();
|
||||
|
||||
void writeByte(uint32_t addr, uint8_t value);
|
||||
uint8_t readByte(uint32_t addr);
|
||||
|
||||
void writeWord(uint32_t addr, uint32_t value);
|
||||
uint32_t readWord(uint32_t addr);
|
||||
|
||||
void write(uint32_t addr, const uint8_t* buffer, int size);
|
||||
void read(uint32_t addr, uint8_t* buffer, int size);
|
||||
|
||||
void go(uint32_t addr);
|
||||
|
||||
std::string version();
|
||||
|
||||
void chipId(uint32_t& chipId, uint32_t& extChipId);
|
||||
|
||||
void setDebug(bool debug) { _debug = debug; }
|
||||
|
||||
const SerialPort& getSerialPort() { return *_port; }
|
||||
|
||||
void reset();
|
||||
|
||||
// Extended SAM-BA functions
|
||||
bool canChipErase() { return _canChipErase; }
|
||||
void chipErase(uint32_t start_addr);
|
||||
|
||||
bool canWriteBuffer() { return _canWriteBuffer; }
|
||||
void writeBuffer(uint32_t src_addr, uint32_t dst_addr, uint32_t size);
|
||||
uint32_t writeBufferSize() { return 4096; }
|
||||
|
||||
bool canChecksumBuffer() { return _canChecksumBuffer; }
|
||||
uint16_t checksumBuffer(uint32_t start_addr, uint32_t size);
|
||||
uint32_t checksumBufferSize() { return 4096; }
|
||||
uint16_t checksumCalc(uint8_t c, uint16_t crc);
|
||||
|
||||
private:
|
||||
bool _canChipErase;
|
||||
bool _canWriteBuffer;
|
||||
bool _canChecksumBuffer;
|
||||
int _readBufferSize;
|
||||
bool _debug;
|
||||
bool _isUsb;
|
||||
SerialPort::Ptr _port;
|
||||
|
||||
bool init();
|
||||
|
||||
uint16_t crc16Calc(const uint8_t *data, int len);
|
||||
bool crc16Check(const uint8_t *blk);
|
||||
void crc16Add(uint8_t *blk);
|
||||
void writeXmodem(const uint8_t* buffer, int size);
|
||||
void readXmodem(uint8_t* buffer, int size);
|
||||
|
||||
void writeBinary(const uint8_t* buffer, int size);
|
||||
void readBinary(uint8_t* buffer, int size);
|
||||
|
||||
};
|
||||
|
||||
|
||||
#endif // _SAMBA_H
|
||||
@@ -0,0 +1,82 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#ifndef _SERIALPORT_H
|
||||
#define _SERIALPORT_H
|
||||
|
||||
#include <string>
|
||||
#include <memory>
|
||||
#include <stdint.h>
|
||||
|
||||
class SerialPort
|
||||
{
|
||||
public:
|
||||
SerialPort(const std::string& name) : _name(name) {}
|
||||
virtual ~SerialPort() {}
|
||||
|
||||
enum Parity
|
||||
{
|
||||
ParityNone,
|
||||
ParityOdd,
|
||||
ParityEven,
|
||||
};
|
||||
|
||||
enum StopBit
|
||||
{
|
||||
StopBitOne,
|
||||
StopBitOneFive,
|
||||
StopBitTwo,
|
||||
};
|
||||
|
||||
virtual bool open(int baud = 115200,
|
||||
int data = 8,
|
||||
Parity parity = ParityNone,
|
||||
StopBit stop = StopBitOne) = 0;
|
||||
virtual void close() = 0;
|
||||
|
||||
virtual bool isUsb() = 0;
|
||||
|
||||
virtual int read(uint8_t* data, int size) = 0;
|
||||
virtual int write(const uint8_t* data, int size) = 0;
|
||||
virtual int get() = 0;
|
||||
virtual int put(int c) = 0;
|
||||
|
||||
virtual bool timeout(int millisecs) = 0;
|
||||
virtual void flush() = 0;
|
||||
virtual void setDTR(bool dtr) = 0;
|
||||
virtual void setRTS(bool rts) = 0;
|
||||
|
||||
virtual std::string name() const { return _name; }
|
||||
|
||||
typedef std::unique_ptr<SerialPort> Ptr;
|
||||
|
||||
protected:
|
||||
std::string _name;
|
||||
};
|
||||
|
||||
#endif // _SERIALPORT_H
|
||||
@@ -0,0 +1,62 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#include "WordCopyApplet.h"
|
||||
|
||||
WordCopyApplet::WordCopyApplet(Samba& samba, uint32_t addr)
|
||||
: Applet(samba,
|
||||
addr,
|
||||
applet.code,
|
||||
sizeof(applet.code),
|
||||
addr + applet.start,
|
||||
addr + applet.stack,
|
||||
addr + applet.reset)
|
||||
{
|
||||
}
|
||||
|
||||
WordCopyApplet::~WordCopyApplet()
|
||||
{
|
||||
}
|
||||
|
||||
void
|
||||
WordCopyApplet::setDstAddr(uint32_t dstAddr)
|
||||
{
|
||||
_samba.writeWord(_addr + applet.dst_addr, dstAddr);
|
||||
}
|
||||
|
||||
void
|
||||
WordCopyApplet::setSrcAddr(uint32_t srcAddr)
|
||||
{
|
||||
_samba.writeWord(_addr + applet.src_addr, srcAddr);
|
||||
}
|
||||
|
||||
void
|
||||
WordCopyApplet::setWords(uint32_t words)
|
||||
{
|
||||
_samba.writeWord(_addr + applet.words, words);
|
||||
}
|
||||
@@ -0,0 +1,49 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#ifndef _WORDCOPYAPPLET_H
|
||||
#define _WORDCOPYAPPLET_H
|
||||
|
||||
#include "Applet.h"
|
||||
#include "WordCopyArm.h"
|
||||
|
||||
class WordCopyApplet : public Applet
|
||||
{
|
||||
public:
|
||||
WordCopyApplet(Samba& samba, uint32_t addr);
|
||||
virtual ~WordCopyApplet();
|
||||
|
||||
void setDstAddr(uint32_t dstAddr);
|
||||
void setSrcAddr(uint32_t srcAddr);
|
||||
void setWords(uint32_t words);
|
||||
|
||||
private:
|
||||
static WordCopyArm applet;
|
||||
};
|
||||
|
||||
#endif // _WORDCOPYAPPLET_H
|
||||
@@ -0,0 +1,47 @@
|
||||
.global start
|
||||
.global stack
|
||||
.global reset
|
||||
.global dst_addr
|
||||
.global src_addr
|
||||
.global words
|
||||
|
||||
.text
|
||||
.thumb
|
||||
.align 0
|
||||
|
||||
start:
|
||||
ldr r0, dst_addr
|
||||
ldr r1, src_addr
|
||||
ldr r2, words
|
||||
b check
|
||||
|
||||
copy:
|
||||
ldmia r1!, {r3}
|
||||
stmia r0!, {r3}
|
||||
sub r2, #1
|
||||
|
||||
check:
|
||||
cmp r2, #0
|
||||
bne copy
|
||||
|
||||
@ Fix for SAM-BA stack bug
|
||||
ldr r0, reset
|
||||
cmp r0, #0
|
||||
bne return
|
||||
ldr r0, stack
|
||||
mov sp, r0
|
||||
|
||||
return:
|
||||
bx lr
|
||||
|
||||
.align 0
|
||||
stack:
|
||||
.word 0
|
||||
reset:
|
||||
.word 0
|
||||
dst_addr:
|
||||
.word 0
|
||||
src_addr:
|
||||
.word 0
|
||||
words:
|
||||
.word 0
|
||||
@@ -0,0 +1,25 @@
|
||||
// WARNING!!! DO NOT EDIT - FILE GENERATED BY APPLETGEN
|
||||
#include "WordCopyArm.h"
|
||||
#include "WordCopyApplet.h"
|
||||
|
||||
WordCopyArm WordCopyApplet::applet = {
|
||||
// dst_addr
|
||||
0x00000028,
|
||||
// reset
|
||||
0x00000024,
|
||||
// src_addr
|
||||
0x0000002c,
|
||||
// stack
|
||||
0x00000020,
|
||||
// start
|
||||
0x00000000,
|
||||
// words
|
||||
0x00000030,
|
||||
// code
|
||||
{
|
||||
0x09, 0x48, 0x0a, 0x49, 0x0a, 0x4a, 0x02, 0xe0, 0x08, 0xc9, 0x08, 0xc0, 0x01, 0x3a, 0x00, 0x2a,
|
||||
0xfa, 0xd1, 0x04, 0x48, 0x00, 0x28, 0x01, 0xd1, 0x01, 0x48, 0x85, 0x46, 0x70, 0x47, 0xc0, 0x46,
|
||||
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
|
||||
0x00, 0x00, 0x00, 0x00,
|
||||
}
|
||||
};
|
||||
@@ -0,0 +1,18 @@
|
||||
// WARNING!!! DO NOT EDIT - FILE GENERATED BY APPLETGEN
|
||||
#ifndef _WORDCOPYARM_H
|
||||
#define _WORDCOPYARM_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t dst_addr;
|
||||
uint32_t reset;
|
||||
uint32_t src_addr;
|
||||
uint32_t stack;
|
||||
uint32_t start;
|
||||
uint32_t words;
|
||||
uint8_t code[52];
|
||||
} WordCopyArm;
|
||||
|
||||
#endif // _WORDCOPYARM_H
|
||||
@@ -0,0 +1,489 @@
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
// BOSSA
|
||||
//
|
||||
// Copyright (c) 2011-2018, ShumaTech
|
||||
// All rights reserved.
|
||||
//
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// * Redistributions of source code must retain the above copyright
|
||||
// notice, this list of conditions and the following disclaimer.
|
||||
// * Redistributions in binary form must reproduce the above copyright
|
||||
// notice, this list of conditions and the following disclaimer in the
|
||||
// documentation and/or other materials provided with the distribution.
|
||||
// * Neither the name of the <organization> nor the
|
||||
// names of its contributors may be used to endorse or promote products
|
||||
// derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
// DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
|
||||
// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
///////////////////////////////////////////////////////////////////////////////
|
||||
#include <string>
|
||||
#include <exception>
|
||||
#include <string.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <stdarg.h>
|
||||
#include <sys/time.h>
|
||||
|
||||
#include "CmdOpts.h"
|
||||
#include "Samba.h"
|
||||
#include "PortFactory.h"
|
||||
#include "Device.h"
|
||||
#include "Flasher.h"
|
||||
|
||||
using namespace std;
|
||||
|
||||
class BossaConfig
|
||||
{
|
||||
public:
|
||||
BossaConfig();
|
||||
virtual ~BossaConfig() {}
|
||||
|
||||
bool erase;
|
||||
bool write;
|
||||
bool read;
|
||||
bool verify;
|
||||
bool offset;
|
||||
bool reset;
|
||||
bool port;
|
||||
bool boot;
|
||||
bool bor;
|
||||
bool bod;
|
||||
bool lock;
|
||||
bool unlock;
|
||||
bool security;
|
||||
bool info;
|
||||
bool debug;
|
||||
bool help;
|
||||
bool usbPort;
|
||||
bool arduinoErase;
|
||||
|
||||
int readArg;
|
||||
int offsetArg;
|
||||
string portArg;
|
||||
int bootArg;
|
||||
int bodArg;
|
||||
int borArg;
|
||||
string lockArg;
|
||||
string unlockArg;
|
||||
bool usbPortArg;
|
||||
};
|
||||
|
||||
BossaConfig::BossaConfig()
|
||||
{
|
||||
erase = false;
|
||||
write = false;
|
||||
read = false;
|
||||
verify = false;
|
||||
port = false;
|
||||
boot = false;
|
||||
bod = false;
|
||||
bor = false;
|
||||
lock = false;
|
||||
security = false;
|
||||
info = false;
|
||||
help = false;
|
||||
usbPort = false;
|
||||
arduinoErase = false;
|
||||
|
||||
readArg = 0;
|
||||
offsetArg = 0;
|
||||
bootArg = 1;
|
||||
bodArg = 1;
|
||||
borArg = 1;
|
||||
usbPortArg=1;
|
||||
|
||||
reset = false;
|
||||
}
|
||||
|
||||
class BossaObserver : public FlasherObserver
|
||||
{
|
||||
public:
|
||||
BossaObserver() : _lastTicks(-1) {}
|
||||
virtual ~BossaObserver() {}
|
||||
|
||||
virtual void onStatus(const char *message, ...);
|
||||
virtual void onProgress(int num, int div);
|
||||
private:
|
||||
int _lastTicks;
|
||||
};
|
||||
|
||||
void
|
||||
BossaObserver::onStatus(const char *message, ...)
|
||||
{
|
||||
va_list ap;
|
||||
|
||||
va_start(ap, message);
|
||||
vprintf(message, ap);
|
||||
va_end(ap);
|
||||
}
|
||||
|
||||
void
|
||||
BossaObserver::onProgress(int num, int div)
|
||||
{
|
||||
int ticks;
|
||||
int bars = 30;
|
||||
|
||||
ticks = num * bars / div;
|
||||
|
||||
if (ticks == _lastTicks)
|
||||
return;
|
||||
|
||||
printf("\r[");
|
||||
while (ticks-- > 0)
|
||||
{
|
||||
putchar('=');
|
||||
bars--;
|
||||
}
|
||||
while (bars-- > 0)
|
||||
{
|
||||
putchar(' ');
|
||||
}
|
||||
printf("] %d%% (%d/%d pages)", num * 100 / div, num, div);
|
||||
fflush(stdout);
|
||||
|
||||
_lastTicks = 0;
|
||||
}
|
||||
|
||||
static BossaConfig config;
|
||||
static Option opts[] =
|
||||
{
|
||||
{
|
||||
'e', "erase", &config.erase,
|
||||
{ ArgNone },
|
||||
"erase the entire flash starting at the offset"
|
||||
},
|
||||
{
|
||||
'w', "write", &config.write,
|
||||
{ ArgNone },
|
||||
"write FILE to the flash; accelerated when\n"
|
||||
"combined with erase option"
|
||||
},
|
||||
{
|
||||
'r', "read", &config.read,
|
||||
{ ArgOptional, ArgInt, "SIZE", { &config.readArg } },
|
||||
"read SIZE from flash and store in FILE;\n"
|
||||
"read entire flash if SIZE not specified"
|
||||
},
|
||||
{
|
||||
'v', "verify", &config.verify,
|
||||
{ ArgNone },
|
||||
"verify FILE matches flash contents"
|
||||
},
|
||||
{
|
||||
'o', "offset", &config.offset,
|
||||
{ ArgRequired, ArgInt, "OFFSET", { &config.offsetArg } },
|
||||
"start erase/write/read/verify operation at flash OFFSET;\n"
|
||||
"OFFSET must be aligned to a flash page boundary"
|
||||
},
|
||||
{
|
||||
'p', "port", &config.port,
|
||||
{ ArgRequired, ArgString, "PORT", { &config.portArg } },
|
||||
"use serial PORT to communicate to device;\n"
|
||||
"default behavior is to use first serial port"
|
||||
},
|
||||
{
|
||||
'b', "boot", &config.boot,
|
||||
{ ArgOptional, ArgInt, "BOOL", { &config.bootArg } },
|
||||
"boot from ROM if BOOL is 0;\n"
|
||||
"boot from FLASH if BOOL is 1 [default];\n"
|
||||
"option is ignored on unsupported devices"
|
||||
},
|
||||
{
|
||||
'c', "bod", &config.bod,
|
||||
{ ArgOptional, ArgInt, "BOOL", { &config.bodArg } },
|
||||
"no brownout detection if BOOL is 0;\n"
|
||||
"brownout detection is on if BOOL is 1 [default]"
|
||||
},
|
||||
{
|
||||
't', "bor", &config.bor,
|
||||
{ ArgOptional, ArgInt, "BOOL", { &config.borArg } },
|
||||
"no brownout reset if BOOL is 0;\n"
|
||||
"brownout reset is on if BOOL is 1 [default]"
|
||||
},
|
||||
{
|
||||
'l', "lock", &config.lock,
|
||||
{ ArgOptional, ArgString, "REGION", { &config.lockArg } },
|
||||
"lock the flash REGION as a comma-separated list;\n"
|
||||
"lock all if not given [default]"
|
||||
},
|
||||
{
|
||||
'u', "unlock", &config.unlock,
|
||||
{ ArgOptional, ArgString, "REGION", { &config.unlockArg } },
|
||||
"unlock the flash REGION as a comma-separated list;\n"
|
||||
"unlock all if not given [default]"
|
||||
},
|
||||
{
|
||||
's', "security", &config.security,
|
||||
{ ArgNone },
|
||||
"set the flash security flag"
|
||||
},
|
||||
{
|
||||
'i', "info", &config.info,
|
||||
{ ArgNone },
|
||||
"display device information"
|
||||
},
|
||||
{
|
||||
'd', "debug", &config.debug,
|
||||
{ ArgNone },
|
||||
"print debug messages"
|
||||
},
|
||||
{
|
||||
'h', "help", &config.help,
|
||||
{ ArgNone },
|
||||
"display this help text"
|
||||
},
|
||||
{
|
||||
'U', "usb-port", &config.usbPort,
|
||||
{ ArgOptional, ArgInt, "BOOL", { &config.usbPortArg } },
|
||||
"force serial port detection to USB if BOOL is 1 [default]\n"
|
||||
"or to RS-232 if BOOL is 0"
|
||||
},
|
||||
{
|
||||
'R', "reset", &config.reset,
|
||||
{ ArgNone },
|
||||
"reset CPU (if supported)"
|
||||
},
|
||||
{
|
||||
'a', "arduino-erase", &config.arduinoErase,
|
||||
{ ArgNone },
|
||||
"erase and reset via Arduino 1200 baud hack"
|
||||
}
|
||||
};
|
||||
|
||||
int
|
||||
help(const char* program)
|
||||
{
|
||||
fprintf(stderr, "Try '%s -h' or '%s --help' for more information\n", program, program);
|
||||
return 1;
|
||||
}
|
||||
|
||||
static struct timeval start_time;
|
||||
|
||||
void
|
||||
timer_start()
|
||||
{
|
||||
gettimeofday(&start_time, NULL);
|
||||
}
|
||||
|
||||
float
|
||||
timer_stop()
|
||||
{
|
||||
struct timeval end;
|
||||
gettimeofday(&end, NULL);
|
||||
return (end.tv_sec - start_time.tv_sec) + (end.tv_usec - start_time.tv_usec) / 1000000.0;
|
||||
}
|
||||
|
||||
int
|
||||
main(int argc, char* argv[])
|
||||
{
|
||||
int args;
|
||||
char* pos;
|
||||
CmdOpts cmd(argc, argv, sizeof(opts) / sizeof(opts[0]), opts);
|
||||
|
||||
if ((pos = strrchr(argv[0], '/')) || (pos = strrchr(argv[0], '\\')))
|
||||
argv[0] = pos + 1;
|
||||
|
||||
if (argc <= 1)
|
||||
{
|
||||
fprintf(stderr, "%s: you must specify at least one option\n", argv[0]);
|
||||
return help(argv[0]);
|
||||
}
|
||||
|
||||
args = cmd.parse();
|
||||
if (args < 0)
|
||||
return help(argv[0]);
|
||||
|
||||
if (config.read && (config.write || config.verify))
|
||||
{
|
||||
fprintf(stderr, "%s: read option is exclusive of write or verify\n", argv[0]);
|
||||
return help(argv[0]);
|
||||
}
|
||||
|
||||
if (config.read || config.write || config.verify)
|
||||
{
|
||||
if (args == argc)
|
||||
{
|
||||
fprintf(stderr, "%s: missing file\n", argv[0]);
|
||||
return help(argv[0]);
|
||||
}
|
||||
argc--;
|
||||
}
|
||||
if (args != argc)
|
||||
{
|
||||
fprintf(stderr, "%s: extra arguments found\n", argv[0]);
|
||||
return help(argv[0]);
|
||||
}
|
||||
|
||||
if (config.help)
|
||||
{
|
||||
printf("Usage: %s [OPTION...] [FILE]\n", argv[0]);
|
||||
printf("Basic Open Source SAM-BA Application (BOSSA) Version " VERSION "\n"
|
||||
"Flash programmer for Atmel SAM devices.\n"
|
||||
"Copyright (c) 2011-2018 ShumaTech (http://www.shumatech.com)\n"
|
||||
"\n"
|
||||
"Examples:\n"
|
||||
" bossac -e -w -v -b image.bin # Erase flash, write flash with image.bin,\n"
|
||||
" # verify the write, and set boot from flash\n"
|
||||
" bossac -r0x10000 image.bin # Read 64KB from flash and store in image.bin\n"
|
||||
);
|
||||
printf("\nOptions:\n");
|
||||
cmd.usage(stdout);
|
||||
printf("\nReport bugs to <bugs@shumatech.com>\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
try
|
||||
{
|
||||
Samba samba;
|
||||
PortFactory portFactory;
|
||||
|
||||
if (config.debug)
|
||||
samba.setDebug(true);
|
||||
|
||||
if (!config.port)
|
||||
config.portArg = portFactory.def();
|
||||
|
||||
if (config.arduinoErase)
|
||||
{
|
||||
SerialPort::Ptr port;
|
||||
port = portFactory.create(config.portArg, config.usbPortArg != 0);
|
||||
|
||||
if(!port->open(1200))
|
||||
{
|
||||
fprintf(stderr, "Failed to open port at 1200bps\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
port->setRTS(true);
|
||||
port->setDTR(false);
|
||||
port->close();
|
||||
}
|
||||
|
||||
if (config.portArg.empty())
|
||||
{
|
||||
fprintf(stderr, "No serial ports available\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
bool res;
|
||||
if (config.usbPort)
|
||||
res = samba.connect(portFactory.create(config.portArg, config.usbPortArg != 0));
|
||||
else
|
||||
res = samba.connect(portFactory.create(config.portArg));
|
||||
if (!res)
|
||||
{
|
||||
fprintf(stderr, "No device found on %s\n", config.portArg.c_str());
|
||||
return 1;
|
||||
}
|
||||
|
||||
Device device(samba);
|
||||
device.create();
|
||||
|
||||
Device::FlashPtr& flash = device.getFlash();
|
||||
|
||||
BossaObserver observer;
|
||||
Flasher flasher(samba, device, observer);
|
||||
|
||||
if (config.info)
|
||||
{
|
||||
FlasherInfo info;
|
||||
flasher.info(info);
|
||||
info.print();
|
||||
}
|
||||
|
||||
if (config.unlock)
|
||||
flasher.lock(config.unlockArg, false);
|
||||
|
||||
if (config.erase)
|
||||
{
|
||||
timer_start();
|
||||
flasher.erase(config.offsetArg);
|
||||
printf("\nDone in %5.3f seconds\n", timer_stop());
|
||||
}
|
||||
|
||||
if (config.write)
|
||||
{
|
||||
timer_start();
|
||||
flasher.write(argv[args], config.offsetArg);
|
||||
printf("\nDone in %5.3f seconds\n", timer_stop());
|
||||
}
|
||||
|
||||
if (config.verify)
|
||||
{
|
||||
uint32_t pageErrors;
|
||||
uint32_t totalErrors;
|
||||
|
||||
timer_start();
|
||||
if (!flasher.verify(argv[args], pageErrors, totalErrors, config.offsetArg))
|
||||
{
|
||||
printf("\nVerify failed\nPage errors: %d\nByte errors: %d\n",
|
||||
pageErrors, totalErrors);
|
||||
return 2;
|
||||
}
|
||||
|
||||
printf("\nVerify successful\nDone in %5.3f seconds\n", timer_stop());
|
||||
}
|
||||
|
||||
if (config.read)
|
||||
{
|
||||
timer_start();
|
||||
flasher.read(argv[args], config.readArg, config.offsetArg);
|
||||
printf("\nDone in %5.3f seconds\n", timer_stop());
|
||||
}
|
||||
|
||||
if (config.boot)
|
||||
{
|
||||
printf("Set boot flash %s\n", config.bootArg ? "true" : "false");
|
||||
flash->setBootFlash(config.bootArg);
|
||||
}
|
||||
|
||||
if (config.bod)
|
||||
{
|
||||
printf("Set brownout detect %s\n", config.bodArg ? "true" : "false");
|
||||
flash->setBod(config.bodArg);
|
||||
}
|
||||
|
||||
if (config.bor)
|
||||
{
|
||||
printf("Set brownout reset %s\n", config.borArg ? "true" : "false");
|
||||
flash->setBor(config.borArg);
|
||||
}
|
||||
|
||||
if (config.security)
|
||||
{
|
||||
printf("Set security\n");
|
||||
flash->setSecurity();
|
||||
}
|
||||
|
||||
if (config.lock)
|
||||
flasher.lock(config.lockArg, true);
|
||||
|
||||
flash->writeOptions();
|
||||
|
||||
if (config.reset)
|
||||
device.reset();
|
||||
}
|
||||
catch (exception& e)
|
||||
{
|
||||
fprintf(stderr, "\n%s\n", e.what());
|
||||
return 1;
|
||||
}
|
||||
catch(...)
|
||||
{
|
||||
fprintf(stderr, "\nUnhandled exception\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,78 @@
|
||||
#ifndef _CAN2040_H
|
||||
#define _CAN2040_H
|
||||
|
||||
#include <stdint.h> // uint32_t
|
||||
|
||||
struct can2040_msg {
|
||||
uint32_t id;
|
||||
uint32_t dlc;
|
||||
union {
|
||||
uint8_t data[8];
|
||||
uint32_t data32[2];
|
||||
};
|
||||
};
|
||||
|
||||
enum {
|
||||
CAN2040_ID_RTR = 1<<30,
|
||||
CAN2040_ID_EFF = 1<<31,
|
||||
};
|
||||
|
||||
enum {
|
||||
CAN2040_NOTIFY_RX = 1<<20,
|
||||
CAN2040_NOTIFY_TX = 1<<21,
|
||||
CAN2040_NOTIFY_ERROR = 1<<23,
|
||||
};
|
||||
struct can2040;
|
||||
typedef void (*can2040_rx_cb)(struct can2040 *cd, uint32_t notify
|
||||
, struct can2040_msg *msg);
|
||||
|
||||
void can2040_setup(struct can2040 *cd, uint32_t pio_num);
|
||||
void can2040_callback_config(struct can2040 *cd, can2040_rx_cb rx_cb);
|
||||
void can2040_start(struct can2040 *cd, uint32_t sys_clock, uint32_t bitrate
|
||||
, uint32_t gpio_rx, uint32_t gpio_tx);
|
||||
void can2040_shutdown(struct can2040 *cd);
|
||||
void can2040_pio_irq_handler(struct can2040 *cd);
|
||||
int can2040_check_transmit(struct can2040 *cd);
|
||||
int can2040_transmit(struct can2040 *cd, struct can2040_msg *msg);
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* Internal definitions
|
||||
****************************************************************/
|
||||
|
||||
struct can2040_bitunstuffer {
|
||||
uint32_t stuffed_bits, count_stuff;
|
||||
uint32_t unstuffed_bits, count_unstuff;
|
||||
};
|
||||
|
||||
struct can2040_transmit {
|
||||
struct can2040_msg msg;
|
||||
uint32_t crc, stuffed_words, stuffed_data[5];
|
||||
};
|
||||
|
||||
struct can2040 {
|
||||
// Setup
|
||||
uint32_t pio_num;
|
||||
void *pio_hw;
|
||||
uint32_t gpio_rx, gpio_tx;
|
||||
can2040_rx_cb rx_cb;
|
||||
|
||||
// Bit unstuffing
|
||||
struct can2040_bitunstuffer unstuf;
|
||||
uint32_t raw_bit_count;
|
||||
|
||||
// Input data state
|
||||
uint32_t parse_state;
|
||||
uint32_t parse_crc, parse_crc_bits, parse_crc_pos;
|
||||
struct can2040_msg parse_msg;
|
||||
|
||||
// Reporting
|
||||
uint32_t report_state;
|
||||
|
||||
// Transmits
|
||||
uint32_t tx_state;
|
||||
uint32_t tx_pull_pos, tx_push_pos;
|
||||
struct can2040_transmit tx_queue[4];
|
||||
};
|
||||
|
||||
#endif // can2040.h
|
||||
Executable
+624
@@ -0,0 +1,624 @@
|
||||
#!/usr/bin/env python3
|
||||
# Script to upload software via Can Bootloader
|
||||
#
|
||||
# Copyright (C) 2022 Eric Callahan <arksine.code@gmail.com>
|
||||
#
|
||||
# This file may be distributed under the terms of the GNU GPLv3 license.
|
||||
from __future__ import annotations
|
||||
import sys
|
||||
import os
|
||||
import asyncio
|
||||
import socket
|
||||
import struct
|
||||
import logging
|
||||
import errno
|
||||
import argparse
|
||||
import hashlib
|
||||
import pathlib
|
||||
from typing import Dict, List, Optional, Union
|
||||
|
||||
def output_line(msg: str) -> None:
|
||||
sys.stdout.write(msg + "\n")
|
||||
sys.stdout.flush()
|
||||
|
||||
def output(msg: str) -> None:
|
||||
sys.stdout.write(msg)
|
||||
sys.stdout.flush()
|
||||
|
||||
# Standard crc16 ccitt, take from msgproto.py in Klipper
|
||||
def crc16_ccitt(buf: Union[bytes, bytearray]) -> int:
|
||||
crc = 0xffff
|
||||
for data in buf:
|
||||
data ^= crc & 0xff
|
||||
data ^= (data & 0x0f) << 4
|
||||
crc = ((data << 8) | (crc >> 8)) ^ (data >> 4) ^ (data << 3)
|
||||
return crc & 0xFFFF
|
||||
|
||||
logging.basicConfig(level=logging.INFO)
|
||||
CAN_FMT = "<IB3x8s"
|
||||
CAN_READER_LIMIT = 1024 * 1024
|
||||
|
||||
# Canboot Defs
|
||||
CMD_HEADER = b'\x01\x88'
|
||||
CMD_TRAILER = b'\x99\x03'
|
||||
BOOTLOADER_CMDS = {
|
||||
'CONNECT': 0x11,
|
||||
'SEND_BLOCK': 0x12,
|
||||
'SEND_EOF': 0x13,
|
||||
'REQUEST_BLOCK': 0x14,
|
||||
'COMPLETE': 0x15,
|
||||
'GET_CANBUS_ID': 0x16,
|
||||
}
|
||||
|
||||
ACK_SUCCESS = 0xa0
|
||||
NACK = 0xf1
|
||||
|
||||
# Klipper Admin Defs (for jumping to bootloader)
|
||||
KLIPPER_ADMIN_ID = 0x3f0
|
||||
KLIPPER_SET_NODE_CMD = 0x01
|
||||
KLIPPER_REBOOT_CMD = 0x02
|
||||
|
||||
# CAN Admin Defs
|
||||
CANBUS_ID_ADMIN = 0x3f0
|
||||
CANBUS_ID_ADMIN_RESP = 0x3f1
|
||||
CANBUS_CMD_QUERY_UNASSIGNED = 0x00
|
||||
CANBUS_CMD_SET_NODEID = 0x11
|
||||
CANBUS_CMD_CLEAR_NODE_ID = 0x12
|
||||
CANBUS_RESP_NEED_NODEID = 0x20
|
||||
CANBUS_NODEID_OFFSET = 128
|
||||
|
||||
class FlashCanError(Exception):
|
||||
pass
|
||||
|
||||
class CanFlasher:
|
||||
def __init__(
|
||||
self,
|
||||
node: CanNode,
|
||||
fw_file: pathlib.Path
|
||||
) -> None:
|
||||
self.node = node
|
||||
self.fw_name = fw_file
|
||||
self.fw_sha = hashlib.sha1()
|
||||
self.file_size = 0
|
||||
self.block_size = 64
|
||||
self.block_count = 0
|
||||
self.app_start_addr = 0
|
||||
|
||||
async def connect_btl(self):
|
||||
output_line("Attempting to connect to bootloader")
|
||||
ret = await self.send_command('CONNECT')
|
||||
pinfo = ret[:12]
|
||||
mcu_type = ret[12:]
|
||||
ver_bytes, start_addr, self.block_size = struct.unpack("<4sII", pinfo)
|
||||
self.app_start_addr = start_addr
|
||||
proto_version = ".".join([str(v) for v in reversed(ver_bytes[:3])])
|
||||
if self.block_size not in [64, 128, 256, 512]:
|
||||
raise FlashCanError("Invalid Block Size: %d" % (self.block_size,))
|
||||
while mcu_type and mcu_type[-1] == 0x00:
|
||||
mcu_type = mcu_type[:-1]
|
||||
mcu_type = mcu_type.decode()
|
||||
output_line(
|
||||
f"CanBoot Connected\nProtocol Version: {proto_version}\n"
|
||||
f"Block Size: {self.block_size} bytes\n"
|
||||
f"Application Start: 0x{self.app_start_addr:4X}\n"
|
||||
f"MCU type: {mcu_type}"
|
||||
)
|
||||
|
||||
async def verify_canbus_uuid(self, uuid):
|
||||
output_line("Verifying canbus connection")
|
||||
ret = await self.send_command('GET_CANBUS_ID')
|
||||
mcu_uuid = sum([v << ((5 - i) * 8) for i, v in enumerate(ret[:6])])
|
||||
if mcu_uuid != uuid:
|
||||
raise FlashCanError("UUID mismatch (%s vs %s)" % (uuid, mcu_uuid))
|
||||
|
||||
async def send_command(
|
||||
self,
|
||||
cmdname: str,
|
||||
payload: bytes = b"",
|
||||
tries: int = 5
|
||||
) -> bytearray:
|
||||
word_cnt = (len(payload) // 4) & 0xFF
|
||||
cmd = BOOTLOADER_CMDS[cmdname]
|
||||
out_cmd = bytearray(CMD_HEADER)
|
||||
out_cmd.append(cmd)
|
||||
out_cmd.append(word_cnt)
|
||||
if payload:
|
||||
out_cmd.extend(payload)
|
||||
crc = crc16_ccitt(out_cmd[2:])
|
||||
out_cmd.extend(struct.pack("<H", crc))
|
||||
out_cmd.extend(CMD_TRAILER)
|
||||
while tries:
|
||||
data = bytearray()
|
||||
recd_len = 0
|
||||
try:
|
||||
self.node.write(out_cmd)
|
||||
read_done = False
|
||||
while not read_done:
|
||||
ret = await self.node.readuntil()
|
||||
data.extend(ret)
|
||||
while len(data) > 7:
|
||||
if data[:2] != CMD_HEADER:
|
||||
data = data[1:]
|
||||
continue
|
||||
recd_len = data[3] * 4
|
||||
read_done = len(data) == recd_len + 8
|
||||
break
|
||||
|
||||
except Exception:
|
||||
logging.exception("Can Read Error")
|
||||
else:
|
||||
trailer = data[-2:]
|
||||
recd_crc, = struct.unpack("<H", data[-4:-2])
|
||||
calc_crc = crc16_ccitt(data[2:-4])
|
||||
recd_ack = data[2]
|
||||
cmd_response = 0
|
||||
if recd_len:
|
||||
cmd_response, = struct.unpack("<I", data[4:8])
|
||||
if trailer != CMD_TRAILER:
|
||||
logging.info(
|
||||
f"Command '{cmdname}': Invalid Trailer Received "
|
||||
f"0x{trailer.hex()}"
|
||||
)
|
||||
elif recd_crc != calc_crc:
|
||||
logging.info(
|
||||
f"Command '{cmdname}': Frame CRC Mismatch, expected: "
|
||||
f"{calc_crc}, received {recd_crc}"
|
||||
)
|
||||
elif recd_ack != ACK_SUCCESS:
|
||||
logging.info(f"Command '{cmdname}': Received NACK")
|
||||
elif cmd_response != cmd:
|
||||
logging.info(
|
||||
f"Command '{cmdname}': Acknowledged wrong command, "
|
||||
f"expected: {cmd:2x}, received: {cmd_response:2x}"
|
||||
)
|
||||
else:
|
||||
# Validation passed, return payload sans command
|
||||
if recd_len <= 4:
|
||||
return bytearray()
|
||||
return data[8:recd_len + 4]
|
||||
tries -= 1
|
||||
# clear the read buffer
|
||||
try:
|
||||
await self.node.read(1024, timeout=.1)
|
||||
except asyncio.TimeoutError:
|
||||
pass
|
||||
await asyncio.sleep(.1)
|
||||
raise FlashCanError("Error sending command [%s] to Can Device"
|
||||
% (cmdname))
|
||||
|
||||
async def send_file(self):
|
||||
last_percent = 0
|
||||
output_line("Flashing '%s'..." % (self.fw_name))
|
||||
output("\n[")
|
||||
with open(self.fw_name, 'rb') as f:
|
||||
f.seek(0, os.SEEK_END)
|
||||
self.file_size = f.tell()
|
||||
f.seek(0)
|
||||
flash_address = self.app_start_addr
|
||||
while True:
|
||||
buf = f.read(self.block_size)
|
||||
if not buf:
|
||||
break
|
||||
if len(buf) < self.block_size:
|
||||
buf += b"\xFF" * (self.block_size - len(buf))
|
||||
self.fw_sha.update(buf)
|
||||
prefix = struct.pack("<I", flash_address)
|
||||
for _ in range(3):
|
||||
resp = await self.send_command('SEND_BLOCK', prefix + buf)
|
||||
recd_addr, = struct.unpack("<I", resp)
|
||||
if recd_addr == flash_address:
|
||||
break
|
||||
logging.info(
|
||||
f"Block write mismatch: expected: {flash_address:4X}, "
|
||||
f"received: {recd_addr:4X}"
|
||||
)
|
||||
await asyncio.sleep(.1)
|
||||
else:
|
||||
raise FlashCanError(
|
||||
f"Flash write failed, block address 0x{recd_addr:4X}"
|
||||
)
|
||||
flash_address += self.block_size
|
||||
self.block_count += 1
|
||||
uploaded = self.block_count * self.block_size
|
||||
pct = int(uploaded / float(self.file_size) * 100 + .5)
|
||||
if pct >= last_percent + 2:
|
||||
last_percent += 2.
|
||||
output("#")
|
||||
resp = await self.send_command('SEND_EOF')
|
||||
page_count, = struct.unpack("<I", resp)
|
||||
output_line("]\n\nWrite complete: %d pages" % (page_count))
|
||||
|
||||
async def verify_file(self):
|
||||
last_percent = 0
|
||||
output_line("Verifying (block count = %d)..." % (self.block_count,))
|
||||
output("\n[")
|
||||
ver_sha = hashlib.sha1()
|
||||
for i in range(self.block_count):
|
||||
flash_address = i * self.block_size + self.app_start_addr
|
||||
for _ in range(3):
|
||||
payload = struct.pack("<I", flash_address)
|
||||
resp = await self.send_command("REQUEST_BLOCK", payload)
|
||||
recd_addr, = struct.unpack("<I", resp[:4])
|
||||
if recd_addr == flash_address:
|
||||
break
|
||||
logging.info(
|
||||
f"Block read mismatch: expected: 0x{flash_address:4X}, "
|
||||
f"received: 0x{recd_addr}"
|
||||
)
|
||||
await asyncio.sleep(.1)
|
||||
else:
|
||||
output_line("Error")
|
||||
raise FlashCanError("Block Request Error, block: %d" % (i,))
|
||||
ver_sha.update(resp[4:])
|
||||
pct = int(i * self.block_size / float(self.file_size) * 100 + .5)
|
||||
if pct >= last_percent + 2:
|
||||
last_percent += 2
|
||||
output("#")
|
||||
ver_hex = ver_sha.hexdigest().upper()
|
||||
fw_hex = self.fw_sha.hexdigest().upper()
|
||||
if ver_hex != fw_hex:
|
||||
raise FlashCanError("Checksum mismatch: Expected %s, Received %s"
|
||||
% (fw_hex, ver_hex))
|
||||
output_line("]\n\nVerification Complete: SHA = %s" % (ver_hex))
|
||||
|
||||
async def finish(self):
|
||||
await self.send_command("COMPLETE")
|
||||
|
||||
|
||||
class CanNode:
|
||||
def __init__(self, node_id: int, cansocket: CanSocket) -> None:
|
||||
self.node_id = node_id
|
||||
self._reader = asyncio.StreamReader(CAN_READER_LIMIT)
|
||||
self._cansocket = cansocket
|
||||
|
||||
async def read(
|
||||
self, n: int = -1, timeout: Optional[float] = 2
|
||||
) -> bytes:
|
||||
return await asyncio.wait_for(self._reader.read(n), timeout)
|
||||
|
||||
async def readexactly(
|
||||
self, n: int, timeout: Optional[float] = 2
|
||||
) -> bytes:
|
||||
return await asyncio.wait_for(self._reader.readexactly(n), timeout)
|
||||
|
||||
async def readuntil(
|
||||
self, sep: bytes = b"\x03", timeout: Optional[float] = 2
|
||||
) -> bytes:
|
||||
return await asyncio.wait_for(self._reader.readuntil(sep), timeout)
|
||||
|
||||
def write(self, payload: Union[bytes, bytearray]) -> None:
|
||||
if isinstance(payload, bytearray):
|
||||
payload = bytes(payload)
|
||||
self._cansocket.send(self.node_id, payload)
|
||||
|
||||
async def write_with_response(
|
||||
self,
|
||||
payload: Union[bytearray, bytes],
|
||||
resp_length: int,
|
||||
timeout: Optional[float] = 2.
|
||||
) -> bytes:
|
||||
self.write(payload)
|
||||
return await self.readexactly(resp_length, timeout)
|
||||
|
||||
def feed_data(self, data: bytes) -> None:
|
||||
self._reader.feed_data(data)
|
||||
|
||||
def close(self) -> None:
|
||||
self._reader.feed_eof()
|
||||
|
||||
class CanSocket:
|
||||
def __init__(self, loop: asyncio.AbstractEventLoop):
|
||||
self._loop = loop
|
||||
self.cansock = socket.socket(socket.PF_CAN, socket.SOCK_RAW,
|
||||
socket.CAN_RAW)
|
||||
self.admin_node = CanNode(CANBUS_ID_ADMIN, self)
|
||||
self.nodes: Dict[int, CanNode] = {
|
||||
CANBUS_ID_ADMIN_RESP: self.admin_node
|
||||
}
|
||||
|
||||
self.input_buffer = b""
|
||||
self.output_packets: List[bytes] = []
|
||||
self.input_busy = False
|
||||
self.output_busy = False
|
||||
self.closed = True
|
||||
|
||||
def _handle_can_response(self) -> None:
|
||||
try:
|
||||
data = self.cansock.recv(4096)
|
||||
except socket.error as e:
|
||||
# If bad file descriptor allow connection to be
|
||||
# closed by the data check
|
||||
if e.errno == errno.EBADF:
|
||||
logging.exception("Can Socket Read Error, closing")
|
||||
data = b''
|
||||
else:
|
||||
return
|
||||
if not data:
|
||||
# socket closed
|
||||
self.close()
|
||||
return
|
||||
self.input_buffer += data
|
||||
if self.input_busy:
|
||||
return
|
||||
self.input_busy = True
|
||||
while len(self.input_buffer) >= 16:
|
||||
packet = self.input_buffer[:16]
|
||||
self._process_packet(packet)
|
||||
self.input_buffer = self.input_buffer[16:]
|
||||
self.input_busy = False
|
||||
|
||||
def _process_packet(self, packet: bytes) -> None:
|
||||
can_id, length, data = struct.unpack(CAN_FMT, packet)
|
||||
can_id &= socket.CAN_EFF_MASK
|
||||
payload = data[:length]
|
||||
node = self.nodes.get(can_id)
|
||||
if node is not None:
|
||||
node.feed_data(payload)
|
||||
|
||||
def send(self, can_id: int, payload: bytes = b"") -> None:
|
||||
if can_id > 0x7FF:
|
||||
can_id |= socket.CAN_EFF_FLAG
|
||||
if not payload:
|
||||
packet = struct.pack(CAN_FMT, can_id, 0, b"")
|
||||
self.output_packets.append(packet)
|
||||
else:
|
||||
while payload:
|
||||
length = min(len(payload), 8)
|
||||
pkt_data = payload[:length]
|
||||
payload = payload[length:]
|
||||
packet = struct.pack(
|
||||
CAN_FMT, can_id, length, pkt_data)
|
||||
self.output_packets.append(packet)
|
||||
if self.output_busy:
|
||||
return
|
||||
self.output_busy = True
|
||||
asyncio.create_task(self._do_can_send())
|
||||
|
||||
async def _do_can_send(self):
|
||||
while self.output_packets:
|
||||
packet = self.output_packets.pop(0)
|
||||
try:
|
||||
await self._loop.sock_sendall(self.cansock, packet)
|
||||
except socket.error:
|
||||
logging.info("Socket Write Error, closing")
|
||||
self.close()
|
||||
break
|
||||
self.output_busy = False
|
||||
|
||||
def _jump_to_bootloader(self, uuid: int):
|
||||
# TODO: Send Klipper Admin command to jump to bootloader.
|
||||
# It will need to be implemented
|
||||
output_line("Sending bootloader jump command...")
|
||||
plist = [(uuid >> ((5 - i) * 8)) & 0xFF for i in range(6)]
|
||||
plist.insert(0, KLIPPER_REBOOT_CMD)
|
||||
self.send(KLIPPER_ADMIN_ID, bytes(plist))
|
||||
|
||||
async def _query_uuids(self) -> List[int]:
|
||||
output_line("Checking for canboot nodes...")
|
||||
payload = bytes([CANBUS_CMD_QUERY_UNASSIGNED])
|
||||
self.admin_node.write(payload)
|
||||
curtime = self._loop.time()
|
||||
endtime = curtime + 2.
|
||||
self.uuids: List[int] = []
|
||||
while curtime < endtime:
|
||||
diff = endtime - curtime
|
||||
try:
|
||||
resp = await self.admin_node.readexactly(8, diff)
|
||||
except asyncio.TimeoutError:
|
||||
break
|
||||
finally:
|
||||
curtime = self._loop.time()
|
||||
if resp[0] != CANBUS_RESP_NEED_NODEID:
|
||||
continue
|
||||
app_names = {
|
||||
KLIPPER_SET_NODE_CMD: "Klipper",
|
||||
CANBUS_CMD_SET_NODEID: "CanBoot"
|
||||
}
|
||||
app = app_names.get(resp[7], "Unknown")
|
||||
data = resp[1:7]
|
||||
output_line(f"Detected UUID: {data.hex()}, Application: {app}")
|
||||
uuid = sum([v << ((5 - i) * 8) for i, v in enumerate(data)])
|
||||
if uuid not in self.uuids and app == "CanBoot":
|
||||
self.uuids.append(uuid)
|
||||
return self.uuids
|
||||
|
||||
def _reset_nodes(self) -> None:
|
||||
output_line("Resetting all bootloader node IDs...")
|
||||
payload = bytes([CANBUS_CMD_CLEAR_NODE_ID])
|
||||
self.admin_node.write(payload)
|
||||
|
||||
def _set_node_id(self, uuid: int) -> CanNode:
|
||||
# Convert ID to a list
|
||||
plist = [(uuid >> ((5 - i) * 8)) & 0xFF for i in range(6)]
|
||||
plist.insert(0, CANBUS_CMD_SET_NODEID)
|
||||
node_id = len(self.nodes) + CANBUS_NODEID_OFFSET
|
||||
plist.append(node_id)
|
||||
payload = bytes(plist)
|
||||
self.admin_node.write(payload)
|
||||
decoded_id = node_id * 2 + 0x100
|
||||
node = CanNode(decoded_id, self)
|
||||
self.nodes[decoded_id + 1] = node
|
||||
return node
|
||||
|
||||
async def run(self, intf: str, uuid: int, fw_path: pathlib.Path) -> None:
|
||||
if not fw_path.is_file():
|
||||
raise FlashCanError("Invalid firmware path '%s'" % (fw_path))
|
||||
try:
|
||||
self.cansock.bind((intf,))
|
||||
except Exception:
|
||||
raise FlashCanError("Unable to bind socket to can0")
|
||||
self.closed = False
|
||||
self.cansock.setblocking(False)
|
||||
self._loop.add_reader(
|
||||
self.cansock.fileno(), self._handle_can_response)
|
||||
self._jump_to_bootloader(uuid)
|
||||
await asyncio.sleep(.5)
|
||||
self._reset_nodes()
|
||||
await asyncio.sleep(.5)
|
||||
id_list = await self._query_uuids()
|
||||
if uuid not in id_list:
|
||||
raise FlashCanError(
|
||||
f"Unable to find node matching UUID: {uuid:06x}"
|
||||
)
|
||||
node = self._set_node_id(uuid)
|
||||
flasher = CanFlasher(node, fw_path)
|
||||
await asyncio.sleep(.5)
|
||||
try:
|
||||
await flasher.connect_btl()
|
||||
await flasher.verify_canbus_uuid(uuid)
|
||||
await flasher.send_file()
|
||||
await flasher.verify_file()
|
||||
finally:
|
||||
# always attempt to send the complete command. If
|
||||
# there is an error it will exit the bootloader
|
||||
# unless comms were broken
|
||||
await flasher.finish()
|
||||
|
||||
async def run_query(self, intf: str):
|
||||
try:
|
||||
self.cansock.bind((intf,))
|
||||
except Exception:
|
||||
raise FlashCanError("Unable to bind socket to can0")
|
||||
self.closed = False
|
||||
self.cansock.setblocking(False)
|
||||
self._loop.add_reader(
|
||||
self.cansock.fileno(), self._handle_can_response)
|
||||
self._reset_nodes()
|
||||
await asyncio.sleep(.5)
|
||||
await self._query_uuids()
|
||||
|
||||
def close(self):
|
||||
if self.closed:
|
||||
return
|
||||
self.closed = True
|
||||
for node in self.nodes.values():
|
||||
node.close()
|
||||
self._loop.remove_reader(self.cansock.fileno())
|
||||
self.cansock.close()
|
||||
|
||||
class SerialSocket:
|
||||
def __init__(self, loop: asyncio.AbstractEventLoop):
|
||||
self._loop = loop
|
||||
self.serial = self.serial_error = None
|
||||
self.node = CanNode(0, self)
|
||||
|
||||
def _handle_response(self) -> None:
|
||||
try:
|
||||
data = self.serial.read(4096)
|
||||
except self.serial_error as e:
|
||||
logging.exception("Error on serial read")
|
||||
self.close()
|
||||
self.node.feed_data(data)
|
||||
|
||||
def send(self, can_id: int, payload: bytes = b"") -> None:
|
||||
try:
|
||||
self.serial.write(payload)
|
||||
except self.serial_error as e:
|
||||
logging.exception("Error on serial write")
|
||||
self.close()
|
||||
|
||||
async def run(self, intf: str, baud: int, fw_path: pathlib.Path) -> None:
|
||||
if not fw_path.is_file():
|
||||
raise FlashCanError("Invalid firmware path '%s'" % (fw_path))
|
||||
import serial
|
||||
self.serial_error = serial.SerialException
|
||||
try:
|
||||
serial_dev = serial.Serial(baudrate=baud, timeout=0,
|
||||
exclusive=True)
|
||||
serial_dev.port = intf
|
||||
serial_dev.open()
|
||||
except (OSError, IOError, self.serial_error) as e:
|
||||
raise FlashCanError("Unable to open serial port: %s" % (e,))
|
||||
self.serial = serial_dev
|
||||
self._loop.add_reader(self.serial.fileno(), self._handle_response)
|
||||
flasher = CanFlasher(self.node, fw_path)
|
||||
try:
|
||||
await flasher.connect_btl()
|
||||
await flasher.send_file()
|
||||
await flasher.verify_file()
|
||||
finally:
|
||||
# always attempt to send the complete command. If
|
||||
# there is an error it will exit the bootloader
|
||||
# unless comms were broken
|
||||
await flasher.finish()
|
||||
|
||||
def close(self):
|
||||
if self.serial is None:
|
||||
return
|
||||
self._loop.remove_reader(self.serial.fileno())
|
||||
self.serial.close()
|
||||
self.serial = None
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(
|
||||
description="Can Bootloader Flash Utility")
|
||||
parser.add_argument(
|
||||
"-d", "--device", metavar='<serial device>',
|
||||
help="Serial Device"
|
||||
)
|
||||
parser.add_argument(
|
||||
"-b", "--baud", default=250000, metavar='<baud rate>',
|
||||
help="Serial baud rate"
|
||||
)
|
||||
parser.add_argument(
|
||||
"-i", "--interface", default="can0", metavar='<can interface>',
|
||||
help="Can Interface"
|
||||
)
|
||||
parser.add_argument(
|
||||
"-f", "--firmware", metavar="<klipper.bin>",
|
||||
default="~/klipper/out/klipper.bin",
|
||||
help="Path to Klipper firmware file")
|
||||
parser.add_argument(
|
||||
"-u", "--uuid", metavar="<uuid>", default=None,
|
||||
help="Can device uuid"
|
||||
)
|
||||
parser.add_argument(
|
||||
"-q", "--query", action="store_true",
|
||||
help="Query Bootloader Device IDs"
|
||||
)
|
||||
parser.add_argument(
|
||||
"-v", "--verbose", action="store_true",
|
||||
help="Enable verbose responses"
|
||||
)
|
||||
|
||||
args = parser.parse_args()
|
||||
if not args.verbose:
|
||||
logging.getLogger().setLevel(logging.ERROR)
|
||||
intf = args.interface
|
||||
fpath = pathlib.Path(args.firmware).expanduser().resolve()
|
||||
loop = asyncio.get_event_loop()
|
||||
iscan = args.device is None
|
||||
sock = None
|
||||
try:
|
||||
if iscan:
|
||||
sock = CanSocket(loop)
|
||||
if args.query:
|
||||
loop.run_until_complete(sock.run_query(intf))
|
||||
else:
|
||||
if args.uuid is None:
|
||||
raise FlashCanError(
|
||||
"The 'uuid' option must be specified to flash a device"
|
||||
)
|
||||
uuid = int(args.uuid, 16)
|
||||
loop.run_until_complete(sock.run(intf, uuid, fpath))
|
||||
else:
|
||||
if args.device is None:
|
||||
raise FlashCanError(
|
||||
"The 'device' option must be specified to flash a device"
|
||||
)
|
||||
sock = SerialSocket(loop)
|
||||
loop.run_until_complete(sock.run(args.device, args.baud, fpath))
|
||||
except Exception as e:
|
||||
logging.exception("Can Flash Error")
|
||||
sys.exit(-1)
|
||||
finally:
|
||||
if sock is not None:
|
||||
sock.close()
|
||||
if args.query:
|
||||
output_line("Query Complete")
|
||||
else:
|
||||
output_line("CAN Flash Success")
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
main()
|
||||
@@ -0,0 +1,411 @@
|
||||
/******************************************************************************
|
||||
* @file cachel1_armv7.h
|
||||
* @brief CMSIS Level 1 Cache API for Armv7-M and later
|
||||
* @version V1.0.0
|
||||
* @date 03. March 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_CACHEL1_ARMV7_H
|
||||
#define ARM_CACHEL1_ARMV7_H
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_CacheFunctions Cache Functions
|
||||
\brief Functions that configure Instruction and Data cache.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Cache Size ID Register Macros */
|
||||
#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos)
|
||||
#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos )
|
||||
|
||||
#ifndef __SCB_DCACHE_LINE_SIZE
|
||||
#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||
#endif
|
||||
|
||||
#ifndef __SCB_ICACHE_LINE_SIZE
|
||||
#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */
|
||||
#endif
|
||||
|
||||
/**
|
||||
\brief Enable I-Cache
|
||||
\details Turns on I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable I-Cache
|
||||
\details Turns off I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */
|
||||
SCB->ICIALLU = 0UL; /* invalidate I-Cache */
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate I-Cache
|
||||
\details Invalidates I-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache (void)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
__DSB();
|
||||
__ISB();
|
||||
SCB->ICIALLU = 0UL;
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief I-Cache Invalidate by address
|
||||
\details Invalidates I-Cache for the given address.
|
||||
I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
I-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] isize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize)
|
||||
{
|
||||
#if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
|
||||
if ( isize > 0 ) {
|
||||
int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_ICACHE_LINE_SIZE;
|
||||
op_size -= __SCB_ICACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Enable D-Cache
|
||||
\details Turns on D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_EnableDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
__DSB();
|
||||
|
||||
SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable D-Cache
|
||||
\details Turns off D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_DisableDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean & invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Invalidate D-Cache
|
||||
\details Invalidates D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) |
|
||||
((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean D-Cache
|
||||
\details Cleans D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) |
|
||||
((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clean & Invalidate D-Cache
|
||||
\details Cleans and Invalidates D-Cache
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
uint32_t ccsidr;
|
||||
uint32_t sets;
|
||||
uint32_t ways;
|
||||
|
||||
SCB->CSSELR = 0U; /* select Level 1 data cache */
|
||||
__DSB();
|
||||
|
||||
ccsidr = SCB->CCSIDR;
|
||||
|
||||
/* clean & invalidate D-Cache */
|
||||
sets = (uint32_t)(CCSIDR_SETS(ccsidr));
|
||||
do {
|
||||
ways = (uint32_t)(CCSIDR_WAYS(ccsidr));
|
||||
do {
|
||||
SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) |
|
||||
((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) );
|
||||
#if defined ( __CC_ARM )
|
||||
__schedule_barrier();
|
||||
#endif
|
||||
} while (ways-- != 0U);
|
||||
} while(sets-- != 0U);
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Invalidate by address
|
||||
\details Invalidates D-Cache for the given address.
|
||||
D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are invalidated.
|
||||
\param[in] addr address
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean by address
|
||||
\details Cleans D-Cache for the given address
|
||||
D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are cleaned.
|
||||
\param[in] addr address
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief D-Cache Clean and Invalidate by address
|
||||
\details Cleans and invalidates D_Cache for the given address
|
||||
D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity.
|
||||
D-Cache memory blocks which are part of given address + given size are cleaned and invalidated.
|
||||
\param[in] addr address (aligned to 32-byte boundary)
|
||||
\param[in] dsize size of memory block (in number of bytes)
|
||||
*/
|
||||
__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize)
|
||||
{
|
||||
#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
|
||||
if ( dsize > 0 ) {
|
||||
int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U));
|
||||
uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */;
|
||||
|
||||
__DSB();
|
||||
|
||||
do {
|
||||
SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */
|
||||
op_addr += __SCB_DCACHE_LINE_SIZE;
|
||||
op_size -= __SCB_DCACHE_LINE_SIZE;
|
||||
} while ( op_size > 0 );
|
||||
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_CacheFunctions */
|
||||
|
||||
#endif /* ARM_CACHEL1_ARMV7_H */
|
||||
@@ -0,0 +1,283 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_compiler.h
|
||||
* @brief CMSIS compiler generic header file
|
||||
* @version V5.1.0
|
||||
* @date 09. October 2018
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef __CMSIS_COMPILER_H
|
||||
#define __CMSIS_COMPILER_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/*
|
||||
* Arm Compiler 4/5
|
||||
*/
|
||||
#if defined ( __CC_ARM )
|
||||
#include "cmsis_armcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* Arm Compiler 6.6 LTM (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100)
|
||||
#include "cmsis_armclang_ltm.h"
|
||||
|
||||
/*
|
||||
* Arm Compiler above 6.10.1 (armclang)
|
||||
*/
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
|
||||
#include "cmsis_armclang.h"
|
||||
|
||||
|
||||
/*
|
||||
* GNU Compiler
|
||||
*/
|
||||
#elif defined ( __GNUC__ )
|
||||
#include "cmsis_gcc.h"
|
||||
|
||||
|
||||
/*
|
||||
* IAR Compiler
|
||||
*/
|
||||
#elif defined ( __ICCARM__ )
|
||||
#include <cmsis_iccarm.h>
|
||||
|
||||
|
||||
/*
|
||||
* TI Arm Compiler
|
||||
*/
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#include <cmsis_ccs.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __attribute__((packed))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __attribute__((packed)) T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __attribute__((aligned(x)))
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#define __RESTRICT __restrict
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* TASKING Compiler
|
||||
*/
|
||||
#elif defined ( __TASKING__ )
|
||||
/*
|
||||
* The CMSIS functions have been implemented as intrinsics in the compiler.
|
||||
* Please use "carm -?i" to get an up to date list of all intrinsics,
|
||||
* Including the CMSIS ones.
|
||||
*/
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM __asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
#define __NO_RETURN __attribute__((noreturn))
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#define __USED __attribute__((used))
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __attribute__((weak))
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT struct __packed__
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION union __packed__
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
struct __packed__ T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#define __ALIGNED(x) __align(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* COSMIC Compiler
|
||||
*/
|
||||
#elif defined ( __CSMC__ )
|
||||
#include <cmsis_csm.h>
|
||||
|
||||
#ifndef __ASM
|
||||
#define __ASM _asm
|
||||
#endif
|
||||
#ifndef __INLINE
|
||||
#define __INLINE inline
|
||||
#endif
|
||||
#ifndef __STATIC_INLINE
|
||||
#define __STATIC_INLINE static inline
|
||||
#endif
|
||||
#ifndef __STATIC_FORCEINLINE
|
||||
#define __STATIC_FORCEINLINE __STATIC_INLINE
|
||||
#endif
|
||||
#ifndef __NO_RETURN
|
||||
// NO RETURN is automatically detected hence no warning here
|
||||
#define __NO_RETURN
|
||||
#endif
|
||||
#ifndef __USED
|
||||
#warning No compiler specific solution for __USED. __USED is ignored.
|
||||
#define __USED
|
||||
#endif
|
||||
#ifndef __WEAK
|
||||
#define __WEAK __weak
|
||||
#endif
|
||||
#ifndef __PACKED
|
||||
#define __PACKED @packed
|
||||
#endif
|
||||
#ifndef __PACKED_STRUCT
|
||||
#define __PACKED_STRUCT @packed struct
|
||||
#endif
|
||||
#ifndef __PACKED_UNION
|
||||
#define __PACKED_UNION @packed union
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32 /* deprecated */
|
||||
@packed struct T_UINT32 { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_WRITE
|
||||
__PACKED_STRUCT T_UINT16_WRITE { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT16_READ
|
||||
__PACKED_STRUCT T_UINT16_READ { uint16_t v; };
|
||||
#define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_WRITE
|
||||
__PACKED_STRUCT T_UINT32_WRITE { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val))
|
||||
#endif
|
||||
#ifndef __UNALIGNED_UINT32_READ
|
||||
__PACKED_STRUCT T_UINT32_READ { uint32_t v; };
|
||||
#define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v)
|
||||
#endif
|
||||
#ifndef __ALIGNED
|
||||
#warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored.
|
||||
#define __ALIGNED(x)
|
||||
#endif
|
||||
#ifndef __RESTRICT
|
||||
#warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored.
|
||||
#define __RESTRICT
|
||||
#endif
|
||||
#ifndef __COMPILER_BARRIER
|
||||
#warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored.
|
||||
#define __COMPILER_BARRIER() (void)0
|
||||
#endif
|
||||
|
||||
|
||||
#else
|
||||
#error Unknown compiler.
|
||||
#endif
|
||||
|
||||
|
||||
#endif /* __CMSIS_COMPILER_H */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,39 @@
|
||||
/**************************************************************************//**
|
||||
* @file cmsis_version.h
|
||||
* @brief CMSIS Core(M) Version definitions
|
||||
* @version V5.0.4
|
||||
* @date 23. July 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 ARM Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CMSIS_VERSION_H
|
||||
#define __CMSIS_VERSION_H
|
||||
|
||||
/* CMSIS Version definitions */
|
||||
#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */
|
||||
#define __CM_CMSIS_VERSION_SUB ( 4U) /*!< [15:0] CMSIS Core(M) sub version */
|
||||
#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */
|
||||
#endif
|
||||
@@ -0,0 +1,952 @@
|
||||
/**************************************************************************//**
|
||||
* @file core_cm0.h
|
||||
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
|
||||
* @version V5.0.8
|
||||
* @date 21. August 2019
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef __CORE_CM0_H_GENERIC
|
||||
#define __CORE_CM0_H_GENERIC
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
|
||||
CMSIS violates the following MISRA-C:2004 rules:
|
||||
|
||||
\li Required Rule 8.5, object/function definition in header file.<br>
|
||||
Function definitions in header files are used to allow 'inlining'.
|
||||
|
||||
\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
|
||||
Unions are used for effective representation of core registers.
|
||||
|
||||
\li Advisory Rule 19.7, Function-like macro defined.<br>
|
||||
Function-like macros are used to allow more efficient code.
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* CMSIS definitions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\ingroup Cortex_M0
|
||||
@{
|
||||
*/
|
||||
|
||||
#include "cmsis_version.h"
|
||||
|
||||
/* CMSIS CM0 definitions */
|
||||
#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */
|
||||
#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */
|
||||
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \
|
||||
__CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */
|
||||
|
||||
#define __CORTEX_M (0U) /*!< Cortex-M Core */
|
||||
|
||||
/** __FPU_USED indicates whether an FPU is used or not.
|
||||
This core does not support an FPU at all
|
||||
*/
|
||||
#define __FPU_USED 0U
|
||||
|
||||
#if defined ( __CC_ARM )
|
||||
#if defined __TARGET_FPU_VFP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
|
||||
#if defined __ARM_FP
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __GNUC__ )
|
||||
#if defined (__VFP_FP__) && !defined(__SOFTFP__)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __ICCARM__ )
|
||||
#if defined __ARMVFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TI_ARM__ )
|
||||
#if defined __TI_VFP_SUPPORT__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __TASKING__ )
|
||||
#if defined __FPU_VFP__
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#elif defined ( __CSMC__ )
|
||||
#if ( __CSMC__ & 0x400U)
|
||||
#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_GENERIC */
|
||||
|
||||
#ifndef __CMSIS_GENERIC
|
||||
|
||||
#ifndef __CORE_CM0_H_DEPENDANT
|
||||
#define __CORE_CM0_H_DEPENDANT
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* check device defines and use defaults */
|
||||
#if defined __CHECK_DEVICE_DEFINES
|
||||
#ifndef __CM0_REV
|
||||
#define __CM0_REV 0x0000U
|
||||
#warning "__CM0_REV not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __NVIC_PRIO_BITS
|
||||
#define __NVIC_PRIO_BITS 2U
|
||||
#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
|
||||
#endif
|
||||
|
||||
#ifndef __Vendor_SysTickConfig
|
||||
#define __Vendor_SysTickConfig 0U
|
||||
#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* IO definitions (access restrictions to peripheral registers) */
|
||||
/**
|
||||
\defgroup CMSIS_glob_defs CMSIS Global Defines
|
||||
|
||||
<strong>IO Type Qualifiers</strong> are used
|
||||
\li to specify the access to peripheral variables.
|
||||
\li for automatic generation of peripheral register debug information.
|
||||
*/
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /*!< Defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /*!< Defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /*!< Defines 'write only' permissions */
|
||||
#define __IO volatile /*!< Defines 'read / write' permissions */
|
||||
|
||||
/* following defines should be used for structure members */
|
||||
#define __IM volatile const /*! Defines 'read only' structure member permissions */
|
||||
#define __OM volatile /*! Defines 'write only' structure member permissions */
|
||||
#define __IOM volatile /*! Defines 'read / write' structure member permissions */
|
||||
|
||||
/*@} end of group Cortex_M0 */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Register Abstraction
|
||||
Core Register contain:
|
||||
- Core Register
|
||||
- Core NVIC Register
|
||||
- Core SCB Register
|
||||
- Core SysTick Register
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_core_register Defines and Type Definitions
|
||||
\brief Type definitions and defines for Cortex-M processor based devices.
|
||||
*/
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CORE Status and Control Registers
|
||||
\brief Core Register type definitions.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Union type to access the Application Program Status Register (APSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} APSR_Type;
|
||||
|
||||
/* APSR Register Definitions */
|
||||
#define APSR_N_Pos 31U /*!< APSR: N Position */
|
||||
#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
|
||||
|
||||
#define APSR_Z_Pos 30U /*!< APSR: Z Position */
|
||||
#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
|
||||
|
||||
#define APSR_C_Pos 29U /*!< APSR: C Position */
|
||||
#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
|
||||
|
||||
#define APSR_V_Pos 28U /*!< APSR: V Position */
|
||||
#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Interrupt Program Status Register (IPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} IPSR_Type;
|
||||
|
||||
/* IPSR Register Definitions */
|
||||
#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */
|
||||
#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
|
||||
uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
|
||||
uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
|
||||
uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
|
||||
uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
|
||||
uint32_t C:1; /*!< bit: 29 Carry condition code flag */
|
||||
uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
|
||||
uint32_t N:1; /*!< bit: 31 Negative condition code flag */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} xPSR_Type;
|
||||
|
||||
/* xPSR Register Definitions */
|
||||
#define xPSR_N_Pos 31U /*!< xPSR: N Position */
|
||||
#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
|
||||
|
||||
#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */
|
||||
#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
|
||||
|
||||
#define xPSR_C_Pos 29U /*!< xPSR: C Position */
|
||||
#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
|
||||
|
||||
#define xPSR_V_Pos 28U /*!< xPSR: V Position */
|
||||
#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
|
||||
|
||||
#define xPSR_T_Pos 24U /*!< xPSR: T Position */
|
||||
#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
|
||||
|
||||
#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */
|
||||
#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
|
||||
|
||||
|
||||
/**
|
||||
\brief Union type to access the Control Registers (CONTROL).
|
||||
*/
|
||||
typedef union
|
||||
{
|
||||
struct
|
||||
{
|
||||
uint32_t _reserved0:1; /*!< bit: 0 Reserved */
|
||||
uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
|
||||
uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
|
||||
} b; /*!< Structure used for bit access */
|
||||
uint32_t w; /*!< Type used for word access */
|
||||
} CONTROL_Type;
|
||||
|
||||
/* CONTROL Register Definitions */
|
||||
#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */
|
||||
#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
|
||||
|
||||
/*@} end of group CMSIS_CORE */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
|
||||
\brief Type definitions for the NVIC Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
|
||||
uint32_t RESERVED0[31U];
|
||||
__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
|
||||
uint32_t RESERVED1[31U];
|
||||
__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
|
||||
uint32_t RESERVED2[31U];
|
||||
__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
|
||||
uint32_t RESERVED3[31U];
|
||||
uint32_t RESERVED4[64U];
|
||||
__IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
|
||||
} NVIC_Type;
|
||||
|
||||
/*@} end of group CMSIS_NVIC */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SCB System Control Block (SCB)
|
||||
\brief Type definitions for the System Control Block Registers
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Control Block (SCB).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
|
||||
__IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
|
||||
uint32_t RESERVED0;
|
||||
__IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
|
||||
__IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
|
||||
__IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
|
||||
uint32_t RESERVED1;
|
||||
__IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
|
||||
__IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
|
||||
} SCB_Type;
|
||||
|
||||
/* SCB CPUID Register Definitions */
|
||||
#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */
|
||||
#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
|
||||
|
||||
#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */
|
||||
#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
|
||||
|
||||
#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */
|
||||
#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
|
||||
|
||||
#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */
|
||||
#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
|
||||
|
||||
#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */
|
||||
#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
|
||||
|
||||
/* SCB Interrupt Control State Register Definitions */
|
||||
#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */
|
||||
#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */
|
||||
#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */
|
||||
#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */
|
||||
#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
|
||||
|
||||
#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */
|
||||
#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */
|
||||
#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
|
||||
|
||||
#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */
|
||||
#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */
|
||||
#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
|
||||
|
||||
#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */
|
||||
#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
|
||||
|
||||
/* SCB Application Interrupt and Reset Control Register Definitions */
|
||||
#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */
|
||||
#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */
|
||||
#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
|
||||
|
||||
#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */
|
||||
#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
|
||||
|
||||
#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */
|
||||
#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
|
||||
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */
|
||||
#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
|
||||
|
||||
/* SCB System Control Register Definitions */
|
||||
#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */
|
||||
#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */
|
||||
#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
|
||||
|
||||
#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */
|
||||
#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
|
||||
|
||||
/* SCB Configuration Control Register Definitions */
|
||||
#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */
|
||||
#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
|
||||
|
||||
#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */
|
||||
#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
|
||||
|
||||
/* SCB System Handler Control and State Register Definitions */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */
|
||||
#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
|
||||
|
||||
/*@} end of group CMSIS_SCB */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_SysTick System Tick Timer (SysTick)
|
||||
\brief Type definitions for the System Timer Registers.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Structure type to access the System Timer (SysTick).
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
__IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
|
||||
__IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
|
||||
__IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
|
||||
__IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
|
||||
} SysTick_Type;
|
||||
|
||||
/* SysTick Control / Status Register Definitions */
|
||||
#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */
|
||||
#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
|
||||
|
||||
#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */
|
||||
#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
|
||||
|
||||
#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */
|
||||
#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
|
||||
|
||||
#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */
|
||||
#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
|
||||
|
||||
/* SysTick Reload Register Definitions */
|
||||
#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */
|
||||
#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
|
||||
|
||||
/* SysTick Current Register Definitions */
|
||||
#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */
|
||||
#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
|
||||
|
||||
/* SysTick Calibration Register Definitions */
|
||||
#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */
|
||||
#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
|
||||
|
||||
#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */
|
||||
#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
|
||||
|
||||
#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */
|
||||
#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
|
||||
|
||||
/*@} end of group CMSIS_SysTick */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
|
||||
\brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor.
|
||||
Therefore they are not covered by the Cortex-M0 header file.
|
||||
@{
|
||||
*/
|
||||
/*@} end of group CMSIS_CoreDebug */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_bitfield Core register bit field macros
|
||||
\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief Mask and shift a bit field value for use in a register bit range.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted value.
|
||||
*/
|
||||
#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
|
||||
|
||||
/**
|
||||
\brief Mask and shift a register value to extract a bit filed value.
|
||||
\param[in] field Name of the register bit field.
|
||||
\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
|
||||
\return Masked and shifted bit field value.
|
||||
*/
|
||||
#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
|
||||
|
||||
/*@} end of group CMSIS_core_bitfield */
|
||||
|
||||
|
||||
/**
|
||||
\ingroup CMSIS_core_register
|
||||
\defgroup CMSIS_core_base Core Definitions
|
||||
\brief Definitions for base addresses, unions, and structures.
|
||||
@{
|
||||
*/
|
||||
|
||||
/* Memory mapping of Core Hardware */
|
||||
#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
|
||||
#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
|
||||
#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
|
||||
#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
|
||||
|
||||
#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
|
||||
#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
|
||||
#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
|
||||
|
||||
|
||||
/*@} */
|
||||
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Hardware Abstraction Layer
|
||||
Core Function Interface contains:
|
||||
- Core NVIC Functions
|
||||
- Core SysTick Functions
|
||||
- Core Register Access Functions
|
||||
******************************************************************************/
|
||||
/**
|
||||
\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* ########################## NVIC functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_NVICFunctions NVIC Functions
|
||||
\brief Functions that manage interrupts and exceptions via the NVIC.
|
||||
@{
|
||||
*/
|
||||
|
||||
#ifdef CMSIS_NVIC_VIRTUAL
|
||||
#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
|
||||
#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
|
||||
#define NVIC_EnableIRQ __NVIC_EnableIRQ
|
||||
#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
|
||||
#define NVIC_DisableIRQ __NVIC_DisableIRQ
|
||||
#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
|
||||
#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
|
||||
#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
|
||||
/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */
|
||||
#define NVIC_SetPriority __NVIC_SetPriority
|
||||
#define NVIC_GetPriority __NVIC_GetPriority
|
||||
#define NVIC_SystemReset __NVIC_SystemReset
|
||||
#endif /* CMSIS_NVIC_VIRTUAL */
|
||||
|
||||
#ifdef CMSIS_VECTAB_VIRTUAL
|
||||
#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
|
||||
#endif
|
||||
#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
|
||||
#else
|
||||
#define NVIC_SetVector __NVIC_SetVector
|
||||
#define NVIC_GetVector __NVIC_GetVector
|
||||
#endif /* (CMSIS_VECTAB_VIRTUAL) */
|
||||
|
||||
#define NVIC_USER_IRQ_OFFSET 16
|
||||
|
||||
|
||||
/* The following EXC_RETURN values are saved the LR on exception entry */
|
||||
#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
|
||||
#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
|
||||
|
||||
|
||||
/* Interrupt Priorities are WORD accessible only under Armv6-M */
|
||||
/* The following MACROS handle generation of the register offset and byte masks */
|
||||
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||
|
||||
#define __NVIC_SetPriorityGrouping(X) (void)(X)
|
||||
#define __NVIC_GetPriorityGrouping() (0U)
|
||||
|
||||
/**
|
||||
\brief Enable Interrupt
|
||||
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
__COMPILER_BARRIER();
|
||||
NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__COMPILER_BARRIER();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Enable status
|
||||
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt is not enabled.
|
||||
\return 1 Interrupt is enabled.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Disable Interrupt
|
||||
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Pending Interrupt
|
||||
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\return 0 Interrupt status is not pending.
|
||||
\return 1 Interrupt status is pending.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||
}
|
||||
else
|
||||
{
|
||||
return(0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Pending Interrupt
|
||||
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Clear Pending Interrupt
|
||||
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||
\param [in] IRQn Device specific interrupt number.
|
||||
\note IRQn must not be negative.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Priority
|
||||
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\param [in] priority Priority to set.
|
||||
\note The priority cannot be set for every processor exception.
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||
{
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
else
|
||||
{
|
||||
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Priority
|
||||
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Interrupt Priority.
|
||||
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
|
||||
{
|
||||
|
||||
if ((int32_t)(IRQn) >= 0)
|
||||
{
|
||||
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
else
|
||||
{
|
||||
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Encode Priority
|
||||
\details Encodes the priority for an interrupt with the given priority group,
|
||||
preemptive priority value, and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [in] PreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [in] SubPriority Subpriority value (starting from 0).
|
||||
\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
|
||||
*/
|
||||
__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
return (
|
||||
((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
|
||||
((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
|
||||
);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Decode Priority
|
||||
\details Decodes an interrupt priority value with a given priority group to
|
||||
preemptive priority value and subpriority value.
|
||||
In case of a conflict between priority grouping and available
|
||||
priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
|
||||
\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
|
||||
\param [in] PriorityGroup Used priority group.
|
||||
\param [out] pPreemptPriority Preemptive priority value (starting from 0).
|
||||
\param [out] pSubPriority Subpriority value (starting from 0).
|
||||
*/
|
||||
__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
|
||||
{
|
||||
uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
|
||||
uint32_t PreemptPriorityBits;
|
||||
uint32_t SubPriorityBits;
|
||||
|
||||
PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
|
||||
SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
|
||||
|
||||
*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
|
||||
*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
\brief Set Interrupt Vector
|
||||
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
Address 0 must be mapped to SRAM.
|
||||
\param [in] IRQn Interrupt number
|
||||
\param [in] vector Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
|
||||
*(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
|
||||
/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief Get Interrupt Vector
|
||||
\details Reads an interrupt vector from interrupt vector table.
|
||||
The interrupt number can be positive to specify a device specific interrupt,
|
||||
or negative to specify a processor exception.
|
||||
\param [in] IRQn Interrupt number.
|
||||
\return Address of interrupt handler function
|
||||
*/
|
||||
__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
|
||||
return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
\brief System Reset
|
||||
\details Initiates a system reset request to reset the MCU.
|
||||
*/
|
||||
__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
|
||||
{
|
||||
__DSB(); /* Ensure all outstanding memory accesses included
|
||||
buffered write are completed before reset */
|
||||
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||
__DSB(); /* Ensure completion of memory access */
|
||||
|
||||
for(;;) /* wait until reset */
|
||||
{
|
||||
__NOP();
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of CMSIS_Core_NVICFunctions */
|
||||
|
||||
|
||||
/* ########################## FPU functions #################################### */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_FpuFunctions FPU Functions
|
||||
\brief Function that provides FPU type.
|
||||
@{
|
||||
*/
|
||||
|
||||
/**
|
||||
\brief get FPU type
|
||||
\details returns the FPU type
|
||||
\returns
|
||||
- \b 0: No FPU
|
||||
- \b 1: Single precision FPU
|
||||
- \b 2: Double + Single precision FPU
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SCB_GetFPUType(void)
|
||||
{
|
||||
return 0U; /* No FPU */
|
||||
}
|
||||
|
||||
|
||||
/*@} end of CMSIS_Core_FpuFunctions */
|
||||
|
||||
|
||||
|
||||
/* ################################## SysTick function ############################################ */
|
||||
/**
|
||||
\ingroup CMSIS_Core_FunctionInterface
|
||||
\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
|
||||
\brief Functions that configure the System.
|
||||
@{
|
||||
*/
|
||||
|
||||
#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
|
||||
|
||||
/**
|
||||
\brief System Tick Configuration
|
||||
\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
|
||||
Counter is in free running mode to generate periodic interrupts.
|
||||
\param [in] ticks Number of ticks between two interrupts.
|
||||
\return 0 Function succeeded.
|
||||
\return 1 Function failed.
|
||||
\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
|
||||
function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
|
||||
must contain a vendor-specific implementation of this function.
|
||||
*/
|
||||
__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
|
||||
{
|
||||
if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
|
||||
{
|
||||
return (1UL); /* Reload value impossible */
|
||||
}
|
||||
|
||||
SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
|
||||
NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
|
||||
SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
|
||||
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
|
||||
SysTick_CTRL_TICKINT_Msk |
|
||||
SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
|
||||
return (0UL); /* Function successful */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
/*@} end of CMSIS_Core_SysTickFunctions */
|
||||
|
||||
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CORE_CM0_H_DEPENDANT */
|
||||
|
||||
#endif /* __CMSIS_GENERIC */
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,275 @@
|
||||
/******************************************************************************
|
||||
* @file mpu_armv7.h
|
||||
* @brief CMSIS MPU API for Armv7-M MPU
|
||||
* @version V5.1.1
|
||||
* @date 10. February 2020
|
||||
******************************************************************************/
|
||||
/*
|
||||
* Copyright (c) 2017-2020 Arm Limited. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#if defined ( __ICCARM__ )
|
||||
#pragma system_include /* treat file as system include file for MISRA check */
|
||||
#elif defined (__clang__)
|
||||
#pragma clang system_header /* treat file as system include file */
|
||||
#endif
|
||||
|
||||
#ifndef ARM_MPU_ARMV7_H
|
||||
#define ARM_MPU_ARMV7_H
|
||||
|
||||
#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
|
||||
#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
|
||||
#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
|
||||
#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
|
||||
#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
|
||||
#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
|
||||
#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
|
||||
#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
|
||||
|
||||
#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
|
||||
#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
|
||||
#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
|
||||
#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
|
||||
#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
|
||||
#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
|
||||
|
||||
/** MPU Region Base Address Register Value
|
||||
*
|
||||
* \param Region The region to be configured, number 0 to 15.
|
||||
* \param BaseAddress The base address for the region.
|
||||
*/
|
||||
#define ARM_MPU_RBAR(Region, BaseAddress) \
|
||||
(((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
|
||||
((Region) & MPU_RBAR_REGION_Msk) | \
|
||||
(MPU_RBAR_VALID_Msk))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attributes
|
||||
*
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
|
||||
((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
|
||||
(((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
|
||||
(((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
|
||||
(((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
|
||||
((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
|
||||
(((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
|
||||
(((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
|
||||
(((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
|
||||
(((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
|
||||
(((MPU_RASR_ENABLE_Msk))))
|
||||
|
||||
/**
|
||||
* MPU Region Attribute and Size Register Value
|
||||
*
|
||||
* \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
|
||||
* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
|
||||
* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
|
||||
* \param IsShareable Region is shareable between multiple bus masters.
|
||||
* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
|
||||
* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
|
||||
* \param SubRegionDisable Sub-region disable field.
|
||||
* \param Size Region size of the region to be configured, for example 4K, 8K.
|
||||
*/
|
||||
#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
|
||||
ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for strongly ordered memory.
|
||||
* - TEX: 000b
|
||||
* - Shareable
|
||||
* - Non-cacheable
|
||||
* - Non-bufferable
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for device memory.
|
||||
* - TEX: 000b (if shareable) or 010b (if non-shareable)
|
||||
* - Shareable or non-shareable
|
||||
* - Non-cacheable
|
||||
* - Bufferable (if shareable) or non-bufferable (if non-shareable)
|
||||
*
|
||||
* \param IsShareable Configures the device memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute for normal memory.
|
||||
* - TEX: 1BBb (reflecting outer cacheability rules)
|
||||
* - Shareable or non-shareable
|
||||
* - Cacheable or non-cacheable (reflecting inner cacheability rules)
|
||||
* - Bufferable or non-bufferable (reflecting inner cacheability rules)
|
||||
*
|
||||
* \param OuterCp Configures the outer cache policy.
|
||||
* \param InnerCp Configures the inner cache policy.
|
||||
* \param IsShareable Configures the memory as shareable or non-shareable.
|
||||
*/
|
||||
#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U))
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute non-cacheable policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_NOCACHE 0U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, write and read allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_WRA 1U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-through, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WT_NWA 2U
|
||||
|
||||
/**
|
||||
* MPU Memory Access Attribute write-back, no write allocate policy.
|
||||
*/
|
||||
#define ARM_MPU_CACHEP_WB_NWA 3U
|
||||
|
||||
|
||||
/**
|
||||
* Struct for a single MPU Region
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t RBAR; //!< The region base address register value (RBAR)
|
||||
uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
|
||||
} ARM_MPU_Region_t;
|
||||
|
||||
/** Enable the MPU.
|
||||
* \param MPU_Control Default access permissions for unconfigured regions.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
|
||||
{
|
||||
__DMB();
|
||||
MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Disable the MPU.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Disable(void)
|
||||
{
|
||||
__DMB();
|
||||
#ifdef SCB_SHCSR_MEMFAULTENA_Msk
|
||||
SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
|
||||
#endif
|
||||
MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/** Clear and disable the given MPU region.
|
||||
* \param rnr Region number to be cleared.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RASR = 0U;
|
||||
}
|
||||
|
||||
/** Configure an MPU region.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Configure the given MPU region.
|
||||
* \param rnr Region number to be configured.
|
||||
* \param rbar Value for RBAR register.
|
||||
* \param rsar Value for RSAR register.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
|
||||
{
|
||||
MPU->RNR = rnr;
|
||||
MPU->RBAR = rbar;
|
||||
MPU->RASR = rasr;
|
||||
}
|
||||
|
||||
/** Memcopy with strictly ordered memory access, e.g. for register targets.
|
||||
* \param dst Destination data is copied to.
|
||||
* \param src Source data is copied from.
|
||||
* \param len Amount of data words to be copied.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
|
||||
{
|
||||
uint32_t i;
|
||||
for (i = 0U; i < len; ++i)
|
||||
{
|
||||
dst[i] = src[i];
|
||||
}
|
||||
}
|
||||
|
||||
/** Load the given number of MPU regions from a table.
|
||||
* \param table Pointer to the MPU configuration table.
|
||||
* \param cnt Amount of regions to be configured.
|
||||
*/
|
||||
__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
|
||||
{
|
||||
const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
|
||||
while (cnt > MPU_TYPE_RALIASES) {
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
|
||||
table += MPU_TYPE_RALIASES;
|
||||
cnt -= MPU_TYPE_RALIASES;
|
||||
}
|
||||
ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,75 @@
|
||||
/* The MIT License
|
||||
|
||||
Copyright (C) 2012 Zilong Tan (eric.zltan@gmail.com)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person
|
||||
obtaining a copy of this software and associated documentation
|
||||
files (the "Software"), to deal in the Software without
|
||||
restriction, including without limitation the rights to use, copy,
|
||||
modify, merge, publish, distribute, sublicense, and/or sell copies
|
||||
of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be
|
||||
included in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "fasthash.h"
|
||||
|
||||
// Compression function for Merkle-Damgard construction.
|
||||
// This function is generated using the framework provided.
|
||||
#define mix(h) ({ \
|
||||
(h) ^= (h) >> 23; \
|
||||
(h) *= 0x2127599bf4325c37ULL; \
|
||||
(h) ^= (h) >> 47; })
|
||||
|
||||
uint64_t fasthash64(const void *buf, size_t len, uint64_t seed)
|
||||
{
|
||||
const uint64_t m = 0x880355f21e6d1965ULL;
|
||||
const uint64_t *pos = (const uint64_t *)buf;
|
||||
const uint64_t *end = pos + (len / 8);
|
||||
const unsigned char *pos2;
|
||||
uint64_t h = seed ^ (len * m);
|
||||
uint64_t v;
|
||||
|
||||
while (pos != end) {
|
||||
v = *pos++;
|
||||
h ^= mix(v);
|
||||
h *= m;
|
||||
}
|
||||
|
||||
pos2 = (const unsigned char*)pos;
|
||||
v = 0;
|
||||
|
||||
switch (len & 7) {
|
||||
case 7: v ^= (uint64_t)pos2[6] << 48;
|
||||
case 6: v ^= (uint64_t)pos2[5] << 40;
|
||||
case 5: v ^= (uint64_t)pos2[4] << 32;
|
||||
case 4: v ^= (uint64_t)pos2[3] << 24;
|
||||
case 3: v ^= (uint64_t)pos2[2] << 16;
|
||||
case 2: v ^= (uint64_t)pos2[1] << 8;
|
||||
case 1: v ^= (uint64_t)pos2[0];
|
||||
h ^= mix(v);
|
||||
h *= m;
|
||||
}
|
||||
|
||||
return mix(h);
|
||||
}
|
||||
|
||||
uint32_t fasthash32(const void *buf, size_t len, uint32_t seed)
|
||||
{
|
||||
// the following trick converts the 64-bit hashcode to Fermat
|
||||
// residue, which shall retain information from both the higher
|
||||
// and lower parts of hashcode.
|
||||
uint64_t h = fasthash64(buf, len, seed);
|
||||
return h - (h >> 32);
|
||||
}
|
||||
@@ -0,0 +1,56 @@
|
||||
/* The MIT License
|
||||
|
||||
Copyright (C) 2012 Zilong Tan (eric.zltan@gmail.com)
|
||||
|
||||
Permission is hereby granted, free of charge, to any person
|
||||
obtaining a copy of this software and associated documentation
|
||||
files (the "Software"), to deal in the Software without
|
||||
restriction, including without limitation the rights to use, copy,
|
||||
modify, merge, publish, distribute, sublicense, and/or sell copies
|
||||
of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be
|
||||
included in all copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
|
||||
EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
|
||||
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
|
||||
NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
|
||||
ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
|
||||
CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _FASTHASH_H
|
||||
#define _FASTHASH_H
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* fasthash32 - 32-bit implementation of fasthash
|
||||
* @buf: data buffer
|
||||
* @len: data size
|
||||
* @seed: the seed
|
||||
*/
|
||||
uint32_t fasthash32(const void *buf, size_t len, uint32_t seed);
|
||||
|
||||
/**
|
||||
* fasthash64 - 64-bit implementation of fasthash
|
||||
* @buf: data buffer
|
||||
* @len: data size
|
||||
* @seed: the seed
|
||||
*/
|
||||
uint64_t fasthash64(const void *buf, size_t len, uint64_t seed);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,24 @@
|
||||
FatFs License
|
||||
|
||||
FatFs has being developped as a personal project of the author, ChaN. It is free from the code anyone else wrote at current release. Following code block shows a copy of the FatFs license document that heading the source files.
|
||||
|
||||
/*----------------------------------------------------------------------------/
|
||||
/ FatFs - Generic FAT Filesystem Module Rx.xx /
|
||||
/-----------------------------------------------------------------------------/
|
||||
/
|
||||
/ Copyright (C) 20xx, ChaN, all right reserved.
|
||||
/
|
||||
/ FatFs module is an open source software. Redistribution and use of FatFs in
|
||||
/ source and binary forms, with or without modification, are permitted provided
|
||||
/ that the following condition is met:
|
||||
/
|
||||
/ 1. Redistributions of source code must retain the above copyright notice,
|
||||
/ this condition and the following disclaimer.
|
||||
/
|
||||
/ This software is provided by the copyright holder and contributors "AS IS"
|
||||
/ and any warranties related to this software are DISCLAIMED.
|
||||
/ The copyright owner or contributors be NOT LIABLE for any damages caused
|
||||
/ by use of this software.
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
Therefore FatFs license is one of the BSD-style licenses, but there is a significant feature. FatFs is mainly intended for embedded systems. In order to extend the usability for commercial products, the redistributions of FatFs in binary form, such as embedded code, binary library and any forms without source code, do not need to include about FatFs in the documentations. This is equivalent to the 1-clause BSD license. Of course FatFs is compatible with the most of open source software licenses include GNU GPL. When you redistribute the FatFs source code with changes or create a fork, the license can also be changed to GNU GPL, BSD-style license or any open source software license that not conflict with FatFs license.
|
||||
@@ -0,0 +1,77 @@
|
||||
/*-----------------------------------------------------------------------/
|
||||
/ Low level disk interface modlue include file (C)ChaN, 2019 /
|
||||
/-----------------------------------------------------------------------*/
|
||||
|
||||
#ifndef _DISKIO_DEFINED
|
||||
#define _DISKIO_DEFINED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* Status of Disk Functions */
|
||||
typedef BYTE DSTATUS;
|
||||
|
||||
/* Results of Disk Functions */
|
||||
typedef enum {
|
||||
RES_OK = 0, /* 0: Successful */
|
||||
RES_ERROR, /* 1: R/W Error */
|
||||
RES_WRPRT, /* 2: Write Protected */
|
||||
RES_NOTRDY, /* 3: Not Ready */
|
||||
RES_PARERR /* 4: Invalid Parameter */
|
||||
} DRESULT;
|
||||
|
||||
|
||||
/*---------------------------------------*/
|
||||
/* Prototypes for disk control functions */
|
||||
|
||||
|
||||
DSTATUS disk_initialize (BYTE pdrv);
|
||||
DSTATUS disk_status (BYTE pdrv);
|
||||
DRESULT disk_read (BYTE pdrv, BYTE* buff, LBA_t sector, UINT count);
|
||||
DRESULT disk_write (BYTE pdrv, const BYTE* buff, LBA_t sector, UINT count);
|
||||
DRESULT disk_ioctl (BYTE pdrv, BYTE cmd, void* buff);
|
||||
|
||||
|
||||
/* Disk Status Bits (DSTATUS) */
|
||||
|
||||
#define STA_NOINIT 0x01 /* Drive not initialized */
|
||||
#define STA_NODISK 0x02 /* No medium in the drive */
|
||||
#define STA_PROTECT 0x04 /* Write protected */
|
||||
|
||||
|
||||
/* Command code for disk_ioctrl fucntion */
|
||||
|
||||
/* Generic command (Used by FatFs) */
|
||||
#define CTRL_SYNC 0 /* Complete pending write process (needed at FF_FS_READONLY == 0) */
|
||||
#define GET_SECTOR_COUNT 1 /* Get media size (needed at FF_USE_MKFS == 1) */
|
||||
#define GET_SECTOR_SIZE 2 /* Get sector size (needed at FF_MAX_SS != FF_MIN_SS) */
|
||||
#define GET_BLOCK_SIZE 3 /* Get erase block size (needed at FF_USE_MKFS == 1) */
|
||||
#define CTRL_TRIM 4 /* Inform device that the data on the block of sectors is no longer used (needed at FF_USE_TRIM == 1) */
|
||||
|
||||
/* Generic command (Not used by FatFs) */
|
||||
#define CTRL_POWER 5 /* Get/Set power status */
|
||||
#define CTRL_LOCK 6 /* Lock/Unlock media removal */
|
||||
#define CTRL_EJECT 7 /* Eject media */
|
||||
#define CTRL_FORMAT 8 /* Create physical format on the media */
|
||||
|
||||
/* MMC/SDC specific ioctl command */
|
||||
#define MMC_GET_TYPE 10 /* Get card type */
|
||||
#define MMC_GET_CSD 11 /* Get CSD */
|
||||
#define MMC_GET_CID 12 /* Get CID */
|
||||
#define MMC_GET_OCR 13 /* Get OCR */
|
||||
#define MMC_GET_SDSTAT 14 /* Get SD status */
|
||||
#define ISDIO_READ 55 /* Read data form SD iSDIO register */
|
||||
#define ISDIO_WRITE 56 /* Write data to SD iSDIO register */
|
||||
#define ISDIO_MRITE 57 /* Masked write data to SD iSDIO register */
|
||||
|
||||
/* ATA/CF specific ioctl command */
|
||||
#define ATA_GET_REV 20 /* Get F/W revision */
|
||||
#define ATA_GET_MODEL 21 /* Get model name */
|
||||
#define ATA_GET_SN 22 /* Get serial number */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
+6874
File diff suppressed because it is too large
Load Diff
+422
@@ -0,0 +1,422 @@
|
||||
/*----------------------------------------------------------------------------/
|
||||
/ FatFs - Generic FAT Filesystem module R0.14a /
|
||||
/-----------------------------------------------------------------------------/
|
||||
/
|
||||
/ Copyright (C) 2020, ChaN, all right reserved.
|
||||
/
|
||||
/ FatFs module is an open source software. Redistribution and use of FatFs in
|
||||
/ source and binary forms, with or without modification, are permitted provided
|
||||
/ that the following condition is met:
|
||||
|
||||
/ 1. Redistributions of source code must retain the above copyright notice,
|
||||
/ this condition and the following disclaimer.
|
||||
/
|
||||
/ This software is provided by the copyright holder and contributors "AS IS"
|
||||
/ and any warranties related to this software are DISCLAIMED.
|
||||
/ The copyright owner or contributors be NOT LIABLE for any damages caused
|
||||
/ by use of this software.
|
||||
/
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#ifndef FF_DEFINED
|
||||
#define FF_DEFINED 80196 /* Revision ID */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ffconf.h" /* FatFs configuration options */
|
||||
|
||||
#if FF_DEFINED != FFCONF_DEF
|
||||
#error Wrong configuration file (ffconf.h).
|
||||
#endif
|
||||
|
||||
|
||||
/* Integer types used for FatFs API */
|
||||
|
||||
#if defined(_WIN32) /* Main development platform */
|
||||
#define FF_INTDEF 2
|
||||
#include <windows.h>
|
||||
typedef unsigned __int64 QWORD;
|
||||
#elif (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || defined(__cplusplus) /* C99 or later */
|
||||
#define FF_INTDEF 2
|
||||
#include <stdint.h>
|
||||
typedef unsigned int UINT; /* int must be 16-bit or 32-bit */
|
||||
typedef unsigned char BYTE; /* char must be 8-bit */
|
||||
typedef uint16_t WORD; /* 16-bit unsigned integer */
|
||||
typedef uint32_t DWORD; /* 32-bit unsigned integer */
|
||||
typedef uint64_t QWORD; /* 64-bit unsigned integer */
|
||||
typedef WORD WCHAR; /* UTF-16 character type */
|
||||
#else /* Earlier than C99 */
|
||||
#define FF_INTDEF 1
|
||||
typedef unsigned int UINT; /* int must be 16-bit or 32-bit */
|
||||
typedef unsigned char BYTE; /* char must be 8-bit */
|
||||
typedef unsigned short WORD; /* 16-bit unsigned integer */
|
||||
typedef unsigned long DWORD; /* 32-bit unsigned integer */
|
||||
typedef WORD WCHAR; /* UTF-16 character type */
|
||||
#endif
|
||||
|
||||
|
||||
/* Definitions of volume management */
|
||||
|
||||
#if FF_MULTI_PARTITION /* Multiple partition configuration */
|
||||
typedef struct {
|
||||
BYTE pd; /* Physical drive number */
|
||||
BYTE pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
|
||||
} PARTITION;
|
||||
extern PARTITION VolToPart[]; /* Volume - Partition mapping table */
|
||||
#endif
|
||||
|
||||
#if FF_STR_VOLUME_ID
|
||||
#ifndef FF_VOLUME_STRS
|
||||
extern const char* VolumeStr[FF_VOLUMES]; /* User defied volume ID */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Type of path name strings on FatFs API */
|
||||
|
||||
#ifndef _INC_TCHAR
|
||||
#define _INC_TCHAR
|
||||
|
||||
#if FF_USE_LFN && FF_LFN_UNICODE == 1 /* Unicode in UTF-16 encoding */
|
||||
typedef WCHAR TCHAR;
|
||||
#define _T(x) L ## x
|
||||
#define _TEXT(x) L ## x
|
||||
#elif FF_USE_LFN && FF_LFN_UNICODE == 2 /* Unicode in UTF-8 encoding */
|
||||
typedef char TCHAR;
|
||||
#define _T(x) u8 ## x
|
||||
#define _TEXT(x) u8 ## x
|
||||
#elif FF_USE_LFN && FF_LFN_UNICODE == 3 /* Unicode in UTF-32 encoding */
|
||||
typedef DWORD TCHAR;
|
||||
#define _T(x) U ## x
|
||||
#define _TEXT(x) U ## x
|
||||
#elif FF_USE_LFN && (FF_LFN_UNICODE < 0 || FF_LFN_UNICODE > 3)
|
||||
#error Wrong FF_LFN_UNICODE setting
|
||||
#else /* ANSI/OEM code in SBCS/DBCS */
|
||||
typedef char TCHAR;
|
||||
#define _T(x) x
|
||||
#define _TEXT(x) x
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Type of file size and LBA variables */
|
||||
|
||||
#if FF_FS_EXFAT
|
||||
#if FF_INTDEF != 2
|
||||
#error exFAT feature wants C99 or later
|
||||
#endif
|
||||
typedef QWORD FSIZE_t;
|
||||
#if FF_LBA64
|
||||
typedef QWORD LBA_t;
|
||||
#else
|
||||
typedef DWORD LBA_t;
|
||||
#endif
|
||||
#else
|
||||
#if FF_LBA64
|
||||
#error exFAT needs to be enabled when enable 64-bit LBA
|
||||
#endif
|
||||
typedef DWORD FSIZE_t;
|
||||
typedef DWORD LBA_t;
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Filesystem object structure (FATFS) */
|
||||
|
||||
typedef struct {
|
||||
BYTE fs_type; /* Filesystem type (0:not mounted) */
|
||||
BYTE pdrv; /* Associated physical drive */
|
||||
BYTE n_fats; /* Number of FATs (1 or 2) */
|
||||
BYTE wflag; /* win[] flag (b0:dirty) */
|
||||
BYTE fsi_flag; /* FSINFO flags (b7:disabled, b0:dirty) */
|
||||
WORD id; /* Volume mount ID */
|
||||
WORD n_rootdir; /* Number of root directory entries (FAT12/16) */
|
||||
WORD csize; /* Cluster size [sectors] */
|
||||
#if FF_MAX_SS != FF_MIN_SS
|
||||
WORD ssize; /* Sector size (512, 1024, 2048 or 4096) */
|
||||
#endif
|
||||
#if FF_USE_LFN
|
||||
WCHAR* lfnbuf; /* LFN working buffer */
|
||||
#endif
|
||||
#if FF_FS_EXFAT
|
||||
BYTE* dirbuf; /* Directory entry block scratchpad buffer for exFAT */
|
||||
#endif
|
||||
#if FF_FS_REENTRANT
|
||||
FF_SYNC_t sobj; /* Identifier of sync object */
|
||||
#endif
|
||||
#if !FF_FS_READONLY
|
||||
DWORD last_clst; /* Last allocated cluster */
|
||||
DWORD free_clst; /* Number of free clusters */
|
||||
#endif
|
||||
#if FF_FS_RPATH
|
||||
DWORD cdir; /* Current directory start cluster (0:root) */
|
||||
#if FF_FS_EXFAT
|
||||
DWORD cdc_scl; /* Containing directory start cluster (invalid when cdir is 0) */
|
||||
DWORD cdc_size; /* b31-b8:Size of containing directory, b7-b0: Chain status */
|
||||
DWORD cdc_ofs; /* Offset in the containing directory (invalid when cdir is 0) */
|
||||
#endif
|
||||
#endif
|
||||
DWORD n_fatent; /* Number of FAT entries (number of clusters + 2) */
|
||||
DWORD fsize; /* Size of an FAT [sectors] */
|
||||
LBA_t volbase; /* Volume base sector */
|
||||
LBA_t fatbase; /* FAT base sector */
|
||||
LBA_t dirbase; /* Root directory base sector/cluster */
|
||||
LBA_t database; /* Data base sector */
|
||||
#if FF_FS_EXFAT
|
||||
LBA_t bitbase; /* Allocation bitmap base sector */
|
||||
#endif
|
||||
LBA_t winsect; /* Current sector appearing in the win[] */
|
||||
BYTE win[FF_MAX_SS]; /* Disk access window for Directory, FAT (and file data at tiny cfg) */
|
||||
} FATFS;
|
||||
|
||||
|
||||
|
||||
/* Object ID and allocation information (FFOBJID) */
|
||||
|
||||
typedef struct {
|
||||
FATFS* fs; /* Pointer to the hosting volume of this object */
|
||||
WORD id; /* Hosting volume mount ID */
|
||||
BYTE attr; /* Object attribute */
|
||||
BYTE stat; /* Object chain status (b1-0: =0:not contiguous, =2:contiguous, =3:fragmented in this session, b2:sub-directory stretched) */
|
||||
DWORD sclust; /* Object data start cluster (0:no cluster or root directory) */
|
||||
FSIZE_t objsize; /* Object size (valid when sclust != 0) */
|
||||
#if FF_FS_EXFAT
|
||||
DWORD n_cont; /* Size of first fragment - 1 (valid when stat == 3) */
|
||||
DWORD n_frag; /* Size of last fragment needs to be written to FAT (valid when not zero) */
|
||||
DWORD c_scl; /* Containing directory start cluster (valid when sclust != 0) */
|
||||
DWORD c_size; /* b31-b8:Size of containing directory, b7-b0: Chain status (valid when c_scl != 0) */
|
||||
DWORD c_ofs; /* Offset in the containing directory (valid when file object and sclust != 0) */
|
||||
#endif
|
||||
#if FF_FS_LOCK
|
||||
UINT lockid; /* File lock ID origin from 1 (index of file semaphore table Files[]) */
|
||||
#endif
|
||||
} FFOBJID;
|
||||
|
||||
|
||||
|
||||
/* File object structure (FIL) */
|
||||
|
||||
typedef struct {
|
||||
FFOBJID obj; /* Object identifier (must be the 1st member to detect invalid object pointer) */
|
||||
BYTE flag; /* File status flags */
|
||||
BYTE err; /* Abort flag (error code) */
|
||||
FSIZE_t fptr; /* File read/write pointer (Zeroed on file open) */
|
||||
DWORD clust; /* Current cluster of fpter (invalid when fptr is 0) */
|
||||
LBA_t sect; /* Sector number appearing in buf[] (0:invalid) */
|
||||
#if !FF_FS_READONLY
|
||||
LBA_t dir_sect; /* Sector number containing the directory entry (not used at exFAT) */
|
||||
BYTE* dir_ptr; /* Pointer to the directory entry in the win[] (not used at exFAT) */
|
||||
#endif
|
||||
#if FF_USE_FASTSEEK
|
||||
DWORD* cltbl; /* Pointer to the cluster link map table (nulled on open, set by application) */
|
||||
#endif
|
||||
#if !FF_FS_TINY
|
||||
BYTE buf[FF_MAX_SS]; /* File private data read/write window */
|
||||
#endif
|
||||
} FIL;
|
||||
|
||||
|
||||
|
||||
/* Directory object structure (DIR) */
|
||||
|
||||
typedef struct {
|
||||
FFOBJID obj; /* Object identifier */
|
||||
DWORD dptr; /* Current read/write offset */
|
||||
DWORD clust; /* Current cluster */
|
||||
LBA_t sect; /* Current sector (0:Read operation has terminated) */
|
||||
BYTE* dir; /* Pointer to the directory item in the win[] */
|
||||
BYTE fn[12]; /* SFN (in/out) {body[8],ext[3],status[1]} */
|
||||
#if FF_USE_LFN
|
||||
DWORD blk_ofs; /* Offset of current entry block being processed (0xFFFFFFFF:Invalid) */
|
||||
#endif
|
||||
#if FF_USE_FIND
|
||||
const TCHAR* pat; /* Pointer to the name matching pattern */
|
||||
#endif
|
||||
} DIR;
|
||||
|
||||
|
||||
|
||||
/* File information structure (FILINFO) */
|
||||
|
||||
typedef struct {
|
||||
FSIZE_t fsize; /* File size */
|
||||
WORD fdate; /* Modified date */
|
||||
WORD ftime; /* Modified time */
|
||||
BYTE fattrib; /* File attribute */
|
||||
#if FF_USE_LFN
|
||||
TCHAR altname[FF_SFN_BUF + 1];/* Altenative file name */
|
||||
TCHAR fname[FF_LFN_BUF + 1]; /* Primary file name */
|
||||
#else
|
||||
TCHAR fname[12 + 1]; /* File name */
|
||||
#endif
|
||||
} FILINFO;
|
||||
|
||||
|
||||
|
||||
/* Format parameter structure (MKFS_PARM) */
|
||||
|
||||
typedef struct {
|
||||
BYTE fmt; /* Format option (FM_FAT, FM_FAT32, FM_EXFAT and FM_SFD) */
|
||||
BYTE n_fat; /* Number of FATs */
|
||||
UINT align; /* Data area alignment (sector) */
|
||||
UINT n_root; /* Number of root directory entries */
|
||||
DWORD au_size; /* Cluster size (byte) */
|
||||
} MKFS_PARM;
|
||||
|
||||
|
||||
|
||||
/* File function return code (FRESULT) */
|
||||
|
||||
typedef enum {
|
||||
FR_OK = 0, /* (0) Succeeded */
|
||||
FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
|
||||
FR_INT_ERR, /* (2) Assertion failed */
|
||||
FR_NOT_READY, /* (3) The physical drive cannot work */
|
||||
FR_NO_FILE, /* (4) Could not find the file */
|
||||
FR_NO_PATH, /* (5) Could not find the path */
|
||||
FR_INVALID_NAME, /* (6) The path name format is invalid */
|
||||
FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
|
||||
FR_EXIST, /* (8) Access denied due to prohibited access */
|
||||
FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
|
||||
FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
|
||||
FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
|
||||
FR_NOT_ENABLED, /* (12) The volume has no work area */
|
||||
FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
|
||||
FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any problem */
|
||||
FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
|
||||
FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
|
||||
FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
|
||||
FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > FF_FS_LOCK */
|
||||
FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
|
||||
} FRESULT;
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* FatFs module application interface */
|
||||
|
||||
FRESULT f_open (FIL* fp, const TCHAR* path, BYTE mode); /* Open or create a file */
|
||||
FRESULT f_close (FIL* fp); /* Close an open file object */
|
||||
FRESULT f_read (FIL* fp, void* buff, UINT btr, UINT* br); /* Read data from the file */
|
||||
FRESULT f_write (FIL* fp, const void* buff, UINT btw, UINT* bw); /* Write data to the file */
|
||||
FRESULT f_lseek (FIL* fp, FSIZE_t ofs); /* Move file pointer of the file object */
|
||||
FRESULT f_truncate (FIL* fp); /* Truncate the file */
|
||||
FRESULT f_sync (FIL* fp); /* Flush cached data of the writing file */
|
||||
FRESULT f_opendir (DIR* dp, const TCHAR* path); /* Open a directory */
|
||||
FRESULT f_closedir (DIR* dp); /* Close an open directory */
|
||||
FRESULT f_readdir (DIR* dp, FILINFO* fno); /* Read a directory item */
|
||||
FRESULT f_findfirst (DIR* dp, FILINFO* fno, const TCHAR* path, const TCHAR* pattern); /* Find first file */
|
||||
FRESULT f_findnext (DIR* dp, FILINFO* fno); /* Find next file */
|
||||
FRESULT f_mkdir (const TCHAR* path); /* Create a sub directory */
|
||||
FRESULT f_unlink (const TCHAR* path); /* Delete an existing file or directory */
|
||||
FRESULT f_rename (const TCHAR* path_old, const TCHAR* path_new); /* Rename/Move a file or directory */
|
||||
FRESULT f_stat (const TCHAR* path, FILINFO* fno); /* Get file status */
|
||||
FRESULT f_chmod (const TCHAR* path, BYTE attr, BYTE mask); /* Change attribute of a file/dir */
|
||||
FRESULT f_utime (const TCHAR* path, const FILINFO* fno); /* Change timestamp of a file/dir */
|
||||
FRESULT f_chdir (const TCHAR* path); /* Change current directory */
|
||||
FRESULT f_chdrive (const TCHAR* path); /* Change current drive */
|
||||
FRESULT f_getcwd (TCHAR* buff, UINT len); /* Get current directory */
|
||||
FRESULT f_getfree (const TCHAR* path, DWORD* nclst, FATFS** fatfs); /* Get number of free clusters on the drive */
|
||||
FRESULT f_getlabel (const TCHAR* path, TCHAR* label, DWORD* vsn); /* Get volume label */
|
||||
FRESULT f_setlabel (const TCHAR* label); /* Set volume label */
|
||||
FRESULT f_forward (FIL* fp, UINT(*func)(const BYTE*,UINT), UINT btf, UINT* bf); /* Forward data to the stream */
|
||||
FRESULT f_expand (FIL* fp, FSIZE_t fsz, BYTE opt); /* Allocate a contiguous block to the file */
|
||||
FRESULT f_mount (FATFS* fs, const TCHAR* path, BYTE opt); /* Mount/Unmount a logical drive */
|
||||
FRESULT f_mkfs (const TCHAR* path, const MKFS_PARM* opt, void* work, UINT len); /* Create a FAT volume */
|
||||
FRESULT f_fdisk (BYTE pdrv, const LBA_t ptbl[], void* work); /* Divide a physical drive into some partitions */
|
||||
FRESULT f_setcp (WORD cp); /* Set current code page */
|
||||
int f_putc (TCHAR c, FIL* fp); /* Put a character to the file */
|
||||
int f_puts (const TCHAR* str, FIL* cp); /* Put a string to the file */
|
||||
int f_printf (FIL* fp, const TCHAR* str, ...); /* Put a formatted string to the file */
|
||||
TCHAR* f_gets (TCHAR* buff, int len, FIL* fp); /* Get a string from the file */
|
||||
|
||||
#define f_eof(fp) ((int)((fp)->fptr == (fp)->obj.objsize))
|
||||
#define f_error(fp) ((fp)->err)
|
||||
#define f_tell(fp) ((fp)->fptr)
|
||||
#define f_size(fp) ((fp)->obj.objsize)
|
||||
#define f_rewind(fp) f_lseek((fp), 0)
|
||||
#define f_rewinddir(dp) f_readdir((dp), 0)
|
||||
#define f_rmdir(path) f_unlink(path)
|
||||
#define f_unmount(path) f_mount(0, path, 0)
|
||||
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* Additional user defined functions */
|
||||
|
||||
/* RTC function */
|
||||
#if !FF_FS_READONLY && !FF_FS_NORTC
|
||||
DWORD get_fattime (void);
|
||||
#endif
|
||||
|
||||
/* LFN support functions */
|
||||
#if FF_USE_LFN >= 1 /* Code conversion (defined in unicode.c) */
|
||||
WCHAR ff_oem2uni (WCHAR oem, WORD cp); /* OEM code to Unicode conversion */
|
||||
WCHAR ff_uni2oem (DWORD uni, WORD cp); /* Unicode to OEM code conversion */
|
||||
DWORD ff_wtoupper (DWORD uni); /* Unicode upper-case conversion */
|
||||
#endif
|
||||
#if FF_USE_LFN == 3 /* Dynamic memory allocation */
|
||||
void* ff_memalloc (UINT msize); /* Allocate memory block */
|
||||
void ff_memfree (void* mblock); /* Free memory block */
|
||||
#endif
|
||||
|
||||
/* Sync functions */
|
||||
#if FF_FS_REENTRANT
|
||||
int ff_cre_syncobj (BYTE vol, FF_SYNC_t* sobj); /* Create a sync object */
|
||||
int ff_req_grant (FF_SYNC_t sobj); /* Lock sync object */
|
||||
void ff_rel_grant (FF_SYNC_t sobj); /* Unlock sync object */
|
||||
int ff_del_syncobj (FF_SYNC_t sobj); /* Delete a sync object */
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* Flags and offset address */
|
||||
|
||||
|
||||
/* File access mode and open method flags (3rd argument of f_open) */
|
||||
#define FA_READ 0x01
|
||||
#define FA_WRITE 0x02
|
||||
#define FA_OPEN_EXISTING 0x00
|
||||
#define FA_CREATE_NEW 0x04
|
||||
#define FA_CREATE_ALWAYS 0x08
|
||||
#define FA_OPEN_ALWAYS 0x10
|
||||
#define FA_OPEN_APPEND 0x30
|
||||
|
||||
/* Fast seek controls (2nd argument of f_lseek) */
|
||||
#define CREATE_LINKMAP ((FSIZE_t)0 - 1)
|
||||
|
||||
/* Format options (2nd argument of f_mkfs) */
|
||||
#define FM_FAT 0x01
|
||||
#define FM_FAT32 0x02
|
||||
#define FM_EXFAT 0x04
|
||||
#define FM_ANY 0x07
|
||||
#define FM_SFD 0x08
|
||||
|
||||
/* Filesystem type (FATFS.fs_type) */
|
||||
#define FS_FAT12 1
|
||||
#define FS_FAT16 2
|
||||
#define FS_FAT32 3
|
||||
#define FS_EXFAT 4
|
||||
|
||||
/* File attribute bits for directory entry (FILINFO.fattrib) */
|
||||
#define AM_RDO 0x01 /* Read only */
|
||||
#define AM_HID 0x02 /* Hidden */
|
||||
#define AM_SYS 0x04 /* System */
|
||||
#define AM_DIR 0x10 /* Directory */
|
||||
#define AM_ARC 0x20 /* Archive */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* FF_DEFINED */
|
||||
@@ -0,0 +1,298 @@
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ FatFs Functional Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FFCONF_DEF 80196 /* Revision ID */
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Function Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FF_FS_READONLY 0
|
||||
/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
|
||||
/ Read-only configuration removes writing API functions, f_write(), f_sync(),
|
||||
/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
|
||||
/ and optional writing functions as well. */
|
||||
|
||||
|
||||
#define FF_FS_MINIMIZE 0
|
||||
/* This option defines minimization level to remove some basic API functions.
|
||||
/
|
||||
/ 0: Basic functions are fully enabled.
|
||||
/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
|
||||
/ are removed.
|
||||
/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
|
||||
/ 3: f_lseek() function is removed in addition to 2. */
|
||||
|
||||
|
||||
#define FF_USE_STRFUNC 0
|
||||
/* This option switches string functions, f_gets(), f_putc(), f_puts() and f_printf().
|
||||
/
|
||||
/ 0: Disable string functions.
|
||||
/ 1: Enable without LF-CRLF conversion.
|
||||
/ 2: Enable with LF-CRLF conversion. */
|
||||
|
||||
|
||||
#define FF_USE_FIND 0
|
||||
/* This option switches filtered directory read functions, f_findfirst() and
|
||||
/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
|
||||
|
||||
|
||||
#define FF_USE_MKFS 0
|
||||
/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#define FF_USE_FASTSEEK 0
|
||||
/* This option switches fast seek function. (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#define FF_USE_EXPAND 0
|
||||
/* This option switches f_expand function. (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#define FF_USE_CHMOD 0
|
||||
/* This option switches attribute manipulation functions, f_chmod() and f_utime().
|
||||
/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
|
||||
|
||||
|
||||
#define FF_USE_LABEL 1
|
||||
/* This option switches volume label functions, f_getlabel() and f_setlabel().
|
||||
/ (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
#define FF_USE_FORWARD 0
|
||||
/* This option switches f_forward() function. (0:Disable or 1:Enable) */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Locale and Namespace Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FF_CODE_PAGE 437
|
||||
/* This option specifies the OEM code page to be used on the target system.
|
||||
/ Incorrect code page setting can cause a file open failure.
|
||||
/
|
||||
/ 437 - U.S.
|
||||
/ 720 - Arabic
|
||||
/ 737 - Greek
|
||||
/ 771 - KBL
|
||||
/ 775 - Baltic
|
||||
/ 850 - Latin 1
|
||||
/ 852 - Latin 2
|
||||
/ 855 - Cyrillic
|
||||
/ 857 - Turkish
|
||||
/ 860 - Portuguese
|
||||
/ 861 - Icelandic
|
||||
/ 862 - Hebrew
|
||||
/ 863 - Canadian French
|
||||
/ 864 - Arabic
|
||||
/ 865 - Nordic
|
||||
/ 866 - Russian
|
||||
/ 869 - Greek 2
|
||||
/ 932 - Japanese (DBCS)
|
||||
/ 936 - Simplified Chinese (DBCS)
|
||||
/ 949 - Korean (DBCS)
|
||||
/ 950 - Traditional Chinese (DBCS)
|
||||
/ 0 - Include all code pages above and configured by f_setcp()
|
||||
*/
|
||||
|
||||
|
||||
#define FF_USE_LFN 0
|
||||
#define FF_MAX_LFN 255
|
||||
/* The FF_USE_LFN switches the support for LFN (long file name).
|
||||
/
|
||||
/ 0: Disable LFN. FF_MAX_LFN has no effect.
|
||||
/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
|
||||
/ 2: Enable LFN with dynamic working buffer on the STACK.
|
||||
/ 3: Enable LFN with dynamic working buffer on the HEAP.
|
||||
/
|
||||
/ To enable the LFN, ffunicode.c needs to be added to the project. The LFN function
|
||||
/ requiers certain internal working buffer occupies (FF_MAX_LFN + 1) * 2 bytes and
|
||||
/ additional (FF_MAX_LFN + 44) / 15 * 32 bytes when exFAT is enabled.
|
||||
/ The FF_MAX_LFN defines size of the working buffer in UTF-16 code unit and it can
|
||||
/ be in range of 12 to 255. It is recommended to be set it 255 to fully support LFN
|
||||
/ specification.
|
||||
/ When use stack for the working buffer, take care on stack overflow. When use heap
|
||||
/ memory for the working buffer, memory management functions, ff_memalloc() and
|
||||
/ ff_memfree() exemplified in ffsystem.c, need to be added to the project. */
|
||||
|
||||
|
||||
#define FF_LFN_UNICODE 0
|
||||
/* This option switches the character encoding on the API when LFN is enabled.
|
||||
/
|
||||
/ 0: ANSI/OEM in current CP (TCHAR = char)
|
||||
/ 1: Unicode in UTF-16 (TCHAR = WCHAR)
|
||||
/ 2: Unicode in UTF-8 (TCHAR = char)
|
||||
/ 3: Unicode in UTF-32 (TCHAR = DWORD)
|
||||
/
|
||||
/ Also behavior of string I/O functions will be affected by this option.
|
||||
/ When LFN is not enabled, this option has no effect. */
|
||||
|
||||
|
||||
#define FF_LFN_BUF 255
|
||||
#define FF_SFN_BUF 12
|
||||
/* This set of options defines size of file name members in the FILINFO structure
|
||||
/ which is used to read out directory items. These values should be suffcient for
|
||||
/ the file names to read. The maximum possible length of the read file name depends
|
||||
/ on character encoding. When LFN is not enabled, these options have no effect. */
|
||||
|
||||
|
||||
#define FF_STRF_ENCODE 3
|
||||
/* When FF_LFN_UNICODE >= 1 with LFN enabled, string I/O functions, f_gets(),
|
||||
/ f_putc(), f_puts and f_printf() convert the character encoding in it.
|
||||
/ This option selects assumption of character encoding ON THE FILE to be
|
||||
/ read/written via those functions.
|
||||
/
|
||||
/ 0: ANSI/OEM in current CP
|
||||
/ 1: Unicode in UTF-16LE
|
||||
/ 2: Unicode in UTF-16BE
|
||||
/ 3: Unicode in UTF-8
|
||||
*/
|
||||
|
||||
|
||||
#define FF_FS_RPATH 0
|
||||
/* This option configures support for relative path.
|
||||
/
|
||||
/ 0: Disable relative path and remove related functions.
|
||||
/ 1: Enable relative path. f_chdir() and f_chdrive() are available.
|
||||
/ 2: f_getcwd() function is available in addition to 1.
|
||||
*/
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Drive/Volume Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FF_VOLUMES 1
|
||||
/* Number of volumes (logical drives) to be used. (1-10) */
|
||||
|
||||
|
||||
#define FF_STR_VOLUME_ID 0
|
||||
#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3"
|
||||
/* FF_STR_VOLUME_ID switches support for volume ID in arbitrary strings.
|
||||
/ When FF_STR_VOLUME_ID is set to 1 or 2, arbitrary strings can be used as drive
|
||||
/ number in the path name. FF_VOLUME_STRS defines the volume ID strings for each
|
||||
/ logical drives. Number of items must not be less than FF_VOLUMES. Valid
|
||||
/ characters for the volume ID strings are A-Z, a-z and 0-9, however, they are
|
||||
/ compared in case-insensitive. If FF_STR_VOLUME_ID >= 1 and FF_VOLUME_STRS is
|
||||
/ not defined, a user defined volume string table needs to be defined as:
|
||||
/
|
||||
/ const char* VolumeStr[FF_VOLUMES] = {"ram","flash","sd","usb",...
|
||||
*/
|
||||
|
||||
|
||||
#define FF_MULTI_PARTITION 0
|
||||
/* This option switches support for multiple volumes on the physical drive.
|
||||
/ By default (0), each logical drive number is bound to the same physical drive
|
||||
/ number and only an FAT volume found on the physical drive will be mounted.
|
||||
/ When this function is enabled (1), each logical drive number can be bound to
|
||||
/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
|
||||
/ funciton will be available. */
|
||||
|
||||
|
||||
#define FF_MIN_SS 512
|
||||
#define FF_MAX_SS 512
|
||||
/* This set of options configures the range of sector size to be supported. (512,
|
||||
/ 1024, 2048 or 4096) Always set both 512 for most systems, generic memory card and
|
||||
/ harddisk. But a larger value may be required for on-board flash memory and some
|
||||
/ type of optical media. When FF_MAX_SS is larger than FF_MIN_SS, FatFs is configured
|
||||
/ for variable sector size mode and disk_ioctl() function needs to implement
|
||||
/ GET_SECTOR_SIZE command. */
|
||||
|
||||
|
||||
#define FF_LBA64 0
|
||||
/* This option switches support for 64-bit LBA. (0:Disable or 1:Enable)
|
||||
/ To enable the 64-bit LBA, also exFAT needs to be enabled. (FF_FS_EXFAT == 1) */
|
||||
|
||||
|
||||
#define FF_MIN_GPT 0x10000000
|
||||
/* Minimum number of sectors to switch GPT as partitioning format in f_mkfs and
|
||||
/ f_fdisk function. 0x100000000 max. This option has no effect when FF_LBA64 == 0. */
|
||||
|
||||
|
||||
#define FF_USE_TRIM 0
|
||||
/* This option switches support for ATA-TRIM. (0:Disable or 1:Enable)
|
||||
/ To enable Trim function, also CTRL_TRIM command should be implemented to the
|
||||
/ disk_ioctl() function. */
|
||||
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ System Configurations
|
||||
/---------------------------------------------------------------------------*/
|
||||
|
||||
#define FF_FS_TINY 0
|
||||
/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
|
||||
/ At the tiny configuration, size of file object (FIL) is shrinked FF_MAX_SS bytes.
|
||||
/ Instead of private sector buffer eliminated from the file object, common sector
|
||||
/ buffer in the filesystem object (FATFS) is used for the file data transfer. */
|
||||
|
||||
|
||||
#define FF_FS_EXFAT 0
|
||||
/* This option switches support for exFAT filesystem. (0:Disable or 1:Enable)
|
||||
/ To enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1)
|
||||
/ Note that enabling exFAT discards ANSI C (C89) compatibility. */
|
||||
|
||||
|
||||
#define FF_FS_NORTC 0
|
||||
#define FF_NORTC_MON 1
|
||||
#define FF_NORTC_MDAY 1
|
||||
#define FF_NORTC_YEAR 2020
|
||||
/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have
|
||||
/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
|
||||
/ the timestamp function. Every object modified by FatFs will have a fixed timestamp
|
||||
/ defined by FF_NORTC_MON, FF_NORTC_MDAY and FF_NORTC_YEAR in local time.
|
||||
/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
|
||||
/ added to the project to read current time form real-time clock. FF_NORTC_MON,
|
||||
/ FF_NORTC_MDAY and FF_NORTC_YEAR have no effect.
|
||||
/ These options have no effect in read-only configuration (FF_FS_READONLY = 1). */
|
||||
|
||||
|
||||
#define FF_FS_NOFSINFO 0
|
||||
/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
|
||||
/ option, and f_getfree() function at first time after volume mount will force
|
||||
/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
|
||||
/
|
||||
/ bit0=0: Use free cluster count in the FSINFO if available.
|
||||
/ bit0=1: Do not trust free cluster count in the FSINFO.
|
||||
/ bit1=0: Use last allocated cluster number in the FSINFO if available.
|
||||
/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
|
||||
*/
|
||||
|
||||
|
||||
#define FF_FS_LOCK 0
|
||||
/* The option FF_FS_LOCK switches file lock function to control duplicated file open
|
||||
/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
|
||||
/ is 1.
|
||||
/
|
||||
/ 0: Disable file lock function. To avoid volume corruption, application program
|
||||
/ should avoid illegal open, remove and rename to the open objects.
|
||||
/ >0: Enable file lock function. The value defines how many files/sub-directories
|
||||
/ can be opened simultaneously under file lock control. Note that the file
|
||||
/ lock control is independent of re-entrancy. */
|
||||
|
||||
|
||||
/* #include <somertos.h> // O/S definitions */
|
||||
#define FF_FS_REENTRANT 0
|
||||
#define FF_FS_TIMEOUT 1000
|
||||
#define FF_SYNC_t HANDLE
|
||||
/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
|
||||
/ module itself. Note that regardless of this option, file access to different
|
||||
/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
|
||||
/ and f_fdisk() function, are always not re-entrant. Only file/directory access
|
||||
/ to the same volume is under control of this function.
|
||||
/
|
||||
/ 0: Disable re-entrancy. FF_FS_TIMEOUT and FF_SYNC_t have no effect.
|
||||
/ 1: Enable re-entrancy. Also user provided synchronization handlers,
|
||||
/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
|
||||
/ function, must be added to the project. Samples are available in
|
||||
/ option/syscall.c.
|
||||
/
|
||||
/ The FF_FS_TIMEOUT defines timeout period in unit of time tick.
|
||||
/ The FF_SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
|
||||
/ SemaphoreHandle_t and etc. A header file for O/S definitions needs to be
|
||||
/ included somewhere in the scope of ff.h. */
|
||||
|
||||
|
||||
|
||||
/*--- End of configuration options ---*/
|
||||
@@ -0,0 +1,170 @@
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Sample Code of OS Dependent Functions for FatFs */
|
||||
/* (C)ChaN, 2018 */
|
||||
/*------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
#include "ff.h"
|
||||
|
||||
|
||||
#if FF_USE_LFN == 3 /* Dynamic memory allocation */
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Allocate a memory block */
|
||||
/*------------------------------------------------------------------------*/
|
||||
|
||||
void* ff_memalloc ( /* Returns pointer to the allocated memory block (null if not enough core) */
|
||||
UINT msize /* Number of bytes to allocate */
|
||||
)
|
||||
{
|
||||
return malloc(msize); /* Allocate a new memory block with POSIX API */
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Free a memory block */
|
||||
/*------------------------------------------------------------------------*/
|
||||
|
||||
void ff_memfree (
|
||||
void* mblock /* Pointer to the memory block to free (nothing to do if null) */
|
||||
)
|
||||
{
|
||||
free(mblock); /* Free the memory block with POSIX API */
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
#if FF_FS_REENTRANT /* Mutal exclusion */
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Create a Synchronization Object */
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* This function is called in f_mount() function to create a new
|
||||
/ synchronization object for the volume, such as semaphore and mutex.
|
||||
/ When a 0 is returned, the f_mount() function fails with FR_INT_ERR.
|
||||
*/
|
||||
|
||||
//const osMutexDef_t Mutex[FF_VOLUMES]; /* Table of CMSIS-RTOS mutex */
|
||||
|
||||
|
||||
int ff_cre_syncobj ( /* 1:Function succeeded, 0:Could not create the sync object */
|
||||
BYTE vol, /* Corresponding volume (logical drive number) */
|
||||
FF_SYNC_t* sobj /* Pointer to return the created sync object */
|
||||
)
|
||||
{
|
||||
/* Win32 */
|
||||
*sobj = CreateMutex(NULL, FALSE, NULL);
|
||||
return (int)(*sobj != INVALID_HANDLE_VALUE);
|
||||
|
||||
/* uITRON */
|
||||
// T_CSEM csem = {TA_TPRI,1,1};
|
||||
// *sobj = acre_sem(&csem);
|
||||
// return (int)(*sobj > 0);
|
||||
|
||||
/* uC/OS-II */
|
||||
// OS_ERR err;
|
||||
// *sobj = OSMutexCreate(0, &err);
|
||||
// return (int)(err == OS_NO_ERR);
|
||||
|
||||
/* FreeRTOS */
|
||||
// *sobj = xSemaphoreCreateMutex();
|
||||
// return (int)(*sobj != NULL);
|
||||
|
||||
/* CMSIS-RTOS */
|
||||
// *sobj = osMutexCreate(&Mutex[vol]);
|
||||
// return (int)(*sobj != NULL);
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Delete a Synchronization Object */
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* This function is called in f_mount() function to delete a synchronization
|
||||
/ object that created with ff_cre_syncobj() function. When a 0 is returned,
|
||||
/ the f_mount() function fails with FR_INT_ERR.
|
||||
*/
|
||||
|
||||
int ff_del_syncobj ( /* 1:Function succeeded, 0:Could not delete due to an error */
|
||||
FF_SYNC_t sobj /* Sync object tied to the logical drive to be deleted */
|
||||
)
|
||||
{
|
||||
/* Win32 */
|
||||
return (int)CloseHandle(sobj);
|
||||
|
||||
/* uITRON */
|
||||
// return (int)(del_sem(sobj) == E_OK);
|
||||
|
||||
/* uC/OS-II */
|
||||
// OS_ERR err;
|
||||
// OSMutexDel(sobj, OS_DEL_ALWAYS, &err);
|
||||
// return (int)(err == OS_NO_ERR);
|
||||
|
||||
/* FreeRTOS */
|
||||
// vSemaphoreDelete(sobj);
|
||||
// return 1;
|
||||
|
||||
/* CMSIS-RTOS */
|
||||
// return (int)(osMutexDelete(sobj) == osOK);
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Request Grant to Access the Volume */
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* This function is called on entering file functions to lock the volume.
|
||||
/ When a 0 is returned, the file function fails with FR_TIMEOUT.
|
||||
*/
|
||||
|
||||
int ff_req_grant ( /* 1:Got a grant to access the volume, 0:Could not get a grant */
|
||||
FF_SYNC_t sobj /* Sync object to wait */
|
||||
)
|
||||
{
|
||||
/* Win32 */
|
||||
return (int)(WaitForSingleObject(sobj, FF_FS_TIMEOUT) == WAIT_OBJECT_0);
|
||||
|
||||
/* uITRON */
|
||||
// return (int)(wai_sem(sobj) == E_OK);
|
||||
|
||||
/* uC/OS-II */
|
||||
// OS_ERR err;
|
||||
// OSMutexPend(sobj, FF_FS_TIMEOUT, &err));
|
||||
// return (int)(err == OS_NO_ERR);
|
||||
|
||||
/* FreeRTOS */
|
||||
// return (int)(xSemaphoreTake(sobj, FF_FS_TIMEOUT) == pdTRUE);
|
||||
|
||||
/* CMSIS-RTOS */
|
||||
// return (int)(osMutexWait(sobj, FF_FS_TIMEOUT) == osOK);
|
||||
}
|
||||
|
||||
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Release Grant to Access the Volume */
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* This function is called on leaving file functions to unlock the volume.
|
||||
*/
|
||||
|
||||
void ff_rel_grant (
|
||||
FF_SYNC_t sobj /* Sync object to be signaled */
|
||||
)
|
||||
{
|
||||
/* Win32 */
|
||||
ReleaseMutex(sobj);
|
||||
|
||||
/* uITRON */
|
||||
// sig_sem(sobj);
|
||||
|
||||
/* uC/OS-II */
|
||||
// OSMutexPost(sobj);
|
||||
|
||||
/* FreeRTOS */
|
||||
// xSemaphoreGive(sobj);
|
||||
|
||||
/* CMSIS-RTOS */
|
||||
// osMutexRelease(sobj);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
+15593
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,216 @@
|
||||
/*!
|
||||
\file gd32e23x.h
|
||||
\brief general definitions for GD32E23x
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_H
|
||||
#define GD32E23X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* define GD32E23x */
|
||||
#if !defined (GD32E23x)
|
||||
#define GD32E23x
|
||||
#endif /* define GD32E23x */
|
||||
#if !defined (GD32E23x)
|
||||
#error "Please select the target GD32E23x device used in your application (in gd32e23x.h file)"
|
||||
#endif /* undefine GD32E23x tip */
|
||||
|
||||
/* define GD32E23x device category */
|
||||
#if (!defined (GD32E230))
|
||||
#error "Please select GD32E23x device category( GD32E230 )"
|
||||
#endif /* undefine GD32E230 tip */
|
||||
|
||||
/* define value of high speed crystal oscillator (HXTAL) in Hz */
|
||||
#if !defined (HXTAL_VALUE)
|
||||
#define HXTAL_VALUE ((uint32_t)8000000)
|
||||
#endif /* high speed crystal oscillator value */
|
||||
|
||||
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
|
||||
#if !defined (HXTAL_STARTUP_TIMEOUT)
|
||||
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0FFFF)
|
||||
#endif /* high speed crystal oscillator startup timeout */
|
||||
|
||||
/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
|
||||
#if !defined (IRC8M_VALUE)
|
||||
#define IRC8M_VALUE ((uint32_t)8000000)
|
||||
#endif /* internal 8MHz RC oscillator value */
|
||||
|
||||
/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
|
||||
#if !defined (IRC8M_STARTUP_TIMEOUT)
|
||||
#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
|
||||
#endif /* internal 8MHz RC oscillator startup timeout */
|
||||
|
||||
/* define value of internal RC oscillator for ADC in Hz */
|
||||
#if !defined (IRC28M_VALUE)
|
||||
#define IRC28M_VALUE ((uint32_t)28000000)
|
||||
#endif /* IRC28M_VALUE */
|
||||
|
||||
#if !defined (IRC48M_VALUE)
|
||||
#define IRC48M_VALUE ((uint32_t)48000000)
|
||||
#endif /* IRC48M_VALUE */
|
||||
|
||||
/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
|
||||
#if !defined (IRC40K_VALUE)
|
||||
#define IRC40K_VALUE ((uint32_t)40000)
|
||||
#endif /* internal 40KHz RC oscillator value */
|
||||
|
||||
/* define value of low speed crystal oscillator (LXTAL)in Hz */
|
||||
#if !defined (LXTAL_VALUE)
|
||||
#define LXTAL_VALUE ((uint32_t)32768)
|
||||
#endif /* low speed crystal oscillator value */
|
||||
|
||||
/* GD32E23x firmware library version number V1.0 */
|
||||
#define __GD32E23x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __GD32E23x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __GD32E23x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __GD32E23x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __GD32E23x_STDPERIPH_VERSION ((__GD32E23x_STDPERIPH_VERSION_MAIN << 24)\
|
||||
|(__GD32E23x_STDPERIPH_VERSION_SUB1 << 16)\
|
||||
|(__GD32E23x_STDPERIPH_VERSION_SUB2 << 8)\
|
||||
|(__GD32E23x_STDPERIPH_VERSION_RC))
|
||||
|
||||
/* configuration of the Cortex-M23 processor and core peripherals */
|
||||
#define __CM23_REV 0x0100U /*!< Core revision r1p0 */
|
||||
#define __SAUREGION_PRESENT 0U /*!< SAU regions are not present */
|
||||
#define __MPU_PRESENT 0U /*!< MPU is present */
|
||||
#define __VTOR_PRESENT 1U /*!< VTOR is present */
|
||||
#define __NVIC_PRIO_BITS 2U /*!< Number of Bits used for Priority Levels */
|
||||
#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
|
||||
|
||||
/* define interrupt number */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/* Cortex-M23 processor exceptions numbers */
|
||||
NonMaskableInt_IRQn = -14, /*!< non maskable interrupt */
|
||||
HardFault_IRQn = -13, /*!< hardfault interrupt */
|
||||
|
||||
SVCall_IRQn = -5, /*!< sv call interrupt */
|
||||
|
||||
PendSV_IRQn = -2, /*!< pend sv interrupt */
|
||||
SysTick_IRQn = -1, /*!< system tick interrupt */
|
||||
/* interruput numbers */
|
||||
WWDGT_IRQn = 0, /*!< window watchdog timer interrupt */
|
||||
LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
|
||||
RTC_IRQn = 2, /*!< RTC through EXTI line interrupt */
|
||||
FMC_IRQn = 3, /*!< FMC interrupt */
|
||||
RCU_IRQn = 4, /*!< RCU interrupt */
|
||||
EXTI0_1_IRQn = 5, /*!< EXTI line 0 and 1 interrupts */
|
||||
EXTI2_3_IRQn = 6, /*!< EXTI line 2 and 3 interrupts */
|
||||
EXTI4_15_IRQn = 7, /*!< EXTI line 4 to 15 interrupts */
|
||||
DMA_Channel0_IRQn = 9, /*!< DMA channel 0 interrupt */
|
||||
DMA_Channel1_2_IRQn = 10, /*!< DMA channel 1 and channel 2 interrupts */
|
||||
DMA_Channel3_4_IRQn = 11, /*!< DMA channel 3 and channel 4 interrupts */
|
||||
ADC_CMP_IRQn = 12, /*!< ADC, CMP interrupts */
|
||||
TIMER0_BRK_UP_TRG_COM_IRQn = 13, /*!< TIMER0 break, update, trigger and commutation interrupts */
|
||||
TIMER0_Channel_IRQn = 14, /*!< TIMER0 channel capture compare interrupts */
|
||||
TIMER2_IRQn = 16, /*!< TIMER2 interrupt */
|
||||
TIMER5_IRQn = 17, /*!< TIMER5 interrupt */
|
||||
TIMER13_IRQn = 19, /*!< TIMER13 interrupt */
|
||||
TIMER14_IRQn = 20, /*!< TIMER14 interrupt */
|
||||
TIMER15_IRQn = 21, /*!< TIMER15 interrupt */
|
||||
TIMER16_IRQn = 22, /*!< TIMER16 interrupt */
|
||||
I2C0_EV_IRQn = 23, /*!< I2C0 event interrupt */
|
||||
I2C1_EV_IRQn = 24, /*!< I2C1 event interrupt */
|
||||
SPI0_IRQn = 25, /*!< SPI0 interrupt */
|
||||
SPI1_IRQn = 26, /*!< SPI1 interrupt */
|
||||
USART0_IRQn = 27, /*!< USART0 interrupt */
|
||||
USART1_IRQn = 28, /*!< USART1 interrupt */
|
||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||
} IRQn_Type;
|
||||
|
||||
/* includes */
|
||||
#include "core_cm23.h"
|
||||
#include "system_gd32e23x.h"
|
||||
#include <stdint.h>
|
||||
|
||||
/* enum definitions */
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
|
||||
|
||||
/* bit operations */
|
||||
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
|
||||
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
|
||||
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
|
||||
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
|
||||
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
|
||||
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
|
||||
|
||||
/* main flash and SRAM memory map */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address */
|
||||
/* SRAM and peripheral base bit-band region */
|
||||
#define SRAM_BB_BASE ((uint32_t)0x22000000U) /*!< SRAM bit-band base address */
|
||||
#define PERIPH_BB_BASE ((uint32_t)0x42000000U) /*!< peripheral bit-band base address */
|
||||
/* peripheral memory map */
|
||||
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
|
||||
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
|
||||
#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
|
||||
#define AHB2_BUS_BASE ((uint32_t)0x48000000U) /*!< ahb2 base address */
|
||||
/* advanced peripheral bus 1 memory map */
|
||||
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
|
||||
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
|
||||
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
|
||||
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
|
||||
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
|
||||
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
|
||||
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
|
||||
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
|
||||
/* advanced peripheral bus 2 memory map */
|
||||
#define SYSCFG_BASE (APB2_BUS_BASE + 0x00000000U) /*!< SYSCFG base address */
|
||||
#define CMP_BASE (APB2_BUS_BASE + 0x0000001CU) /*!< CMP base address */
|
||||
#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
|
||||
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
|
||||
/* advanced high performance bus 1 memory map */
|
||||
#define DMA_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< DMA base address */
|
||||
#define DMA_CHANNEL_BASE (DMA_BASE + 0x00000008U) /*!< DMA channel base address */
|
||||
#define RCU_BASE (AHB1_BUS_BASE + 0x00001000U) /*!< RCU base address */
|
||||
#define FMC_BASE (AHB1_BUS_BASE + 0x00002000U) /*!< FMC base address */
|
||||
#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
|
||||
/* advanced high performance bus 2 memory map */
|
||||
#define GPIO_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< GPIO base address */
|
||||
/* option byte and debug memory map */
|
||||
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
|
||||
#define DBG_BASE ((uint32_t)0x40015800U) /*!< DBG base address */
|
||||
|
||||
#include "gd32e23x_libopt.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* GD32E23X_H */
|
||||
@@ -0,0 +1,350 @@
|
||||
/*!
|
||||
\file gd32e23x_adc.h
|
||||
\brief definitions for the ADC
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_ADC_H
|
||||
#define GD32E23X_ADC_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* ADC definitions */
|
||||
#define ADC ADC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define ADC_STAT REG32(ADC + 0x00U) /*!< ADC status register */
|
||||
#define ADC_CTL0 REG32(ADC + 0x04U) /*!< ADC control register 0 */
|
||||
#define ADC_CTL1 REG32(ADC + 0x08U) /*!< ADC control register 1 */
|
||||
#define ADC_SAMPT0 REG32(ADC + 0x0CU) /*!< ADC sampling time register 0 */
|
||||
#define ADC_SAMPT1 REG32(ADC + 0x10U) /*!< ADC sampling time register 1 */
|
||||
#define ADC_IOFF0 REG32(ADC + 0x14U) /*!< ADC inserted channel data offset register 0 */
|
||||
#define ADC_IOFF1 REG32(ADC + 0x18U) /*!< ADC inserted channel data offset register 1 */
|
||||
#define ADC_IOFF2 REG32(ADC + 0x1CU) /*!< ADC inserted channel data offset register 2 */
|
||||
#define ADC_IOFF3 REG32(ADC + 0x20U) /*!< ADC inserted channel data offset register 3 */
|
||||
#define ADC_WDHT REG32(ADC + 0x24U) /*!< ADC watchdog high threshold register */
|
||||
#define ADC_WDLT REG32(ADC + 0x28U) /*!< ADC watchdog low threshold register */
|
||||
#define ADC_RSQ0 REG32(ADC + 0x2CU) /*!< ADC regular sequence register 0 */
|
||||
#define ADC_RSQ1 REG32(ADC + 0x30U) /*!< ADC regular sequence register 1 */
|
||||
#define ADC_RSQ2 REG32(ADC + 0x34U) /*!< ADC regular sequence register 2 */
|
||||
#define ADC_ISQ REG32(ADC + 0x38U) /*!< ADC inserted sequence register */
|
||||
#define ADC_IDATA0 REG32(ADC + 0x3CU) /*!< ADC inserted data register 0 */
|
||||
#define ADC_IDATA1 REG32(ADC + 0x40U) /*!< ADC inserted data register 1 */
|
||||
#define ADC_IDATA2 REG32(ADC + 0x44U) /*!< ADC inserted data register 2 */
|
||||
#define ADC_IDATA3 REG32(ADC + 0x48U) /*!< ADC inserted data register 3 */
|
||||
#define ADC_RDATA REG32(ADC + 0x4CU) /*!< ADC regular data register */
|
||||
#define ADC_OVSAMPCTL REG32(ADC + 0x80U) /*!< ADC oversampling control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* ADC_STAT */
|
||||
#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */
|
||||
#define ADC_STAT_EOC BIT(1) /*!< end of conversion flag */
|
||||
#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion flag */
|
||||
#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
|
||||
#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
|
||||
|
||||
/* ADC_CTL0 */
|
||||
#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
|
||||
#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
|
||||
#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
|
||||
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
|
||||
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
|
||||
#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
|
||||
#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */
|
||||
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
|
||||
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
|
||||
#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
|
||||
#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
|
||||
#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */
|
||||
#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */
|
||||
|
||||
/* ADC_CTL1 */
|
||||
#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
|
||||
#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
|
||||
#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
|
||||
#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
|
||||
#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
|
||||
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
|
||||
#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */
|
||||
#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */
|
||||
#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */
|
||||
#define ADC_CTL1_ETERC BIT(20) /*!< external trigger enable for regular channel */
|
||||
#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */
|
||||
#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */
|
||||
#define ADC_CTL1_TSVREN BIT(23) /*!< enable channel 16 and 17 */
|
||||
|
||||
/* ADC_SAMPTx x=0,1 */
|
||||
#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel n(n=0..9,16 and 17) sample time selection */
|
||||
|
||||
/* ADC_IOFFx x=0..3 */
|
||||
#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */
|
||||
|
||||
/* ADC_WDHT */
|
||||
#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */
|
||||
|
||||
/* ADC_WDLT */
|
||||
#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
|
||||
|
||||
/* ADC_RSQx x=0..2 */
|
||||
#define ADC_RSQX_RSQN BITS(0,4) /*!< n conversion in regular sequence */
|
||||
#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */
|
||||
|
||||
/* ADC_ISQ */
|
||||
#define ADC_ISQ_ISQN BITS(0,4) /*!< n conversion in regular sequence */
|
||||
#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
|
||||
|
||||
/* ADC_IDATAx x=0..3*/
|
||||
#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted channel x conversion data */
|
||||
|
||||
/* ADC_RDATA */
|
||||
#define ADC_RDATA_RDATA BITS(0,15) /*!< regular channel data */
|
||||
|
||||
/* ADC_OVSAMPCTL */
|
||||
#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */
|
||||
#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */
|
||||
#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */
|
||||
#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */
|
||||
|
||||
/* constants definitions */
|
||||
/* ADC flag definitions */
|
||||
#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */
|
||||
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion flag */
|
||||
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted channel group conversion flag */
|
||||
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< start flag of inserted channel group */
|
||||
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< start flag of regular channel group */
|
||||
|
||||
/* adc_ctl0 register value */
|
||||
#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< number of conversions in discontinuous mode */
|
||||
|
||||
/* ADC special function */
|
||||
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
|
||||
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */
|
||||
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
|
||||
|
||||
/* ADC data alignment */
|
||||
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< right alignment */
|
||||
#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< left alignment */
|
||||
|
||||
/* external trigger select for regular channel */
|
||||
#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
|
||||
#define ADC_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */
|
||||
#define ADC_EXTTRIG_REGULAR_T14_CH0 CTL1_ETSRC(5) /*!< TIMER14 CH0 event select */
|
||||
#define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */
|
||||
#define ADC_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */
|
||||
|
||||
/* external trigger select for inserted channel */
|
||||
#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12))
|
||||
#define ADC_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */
|
||||
#define ADC_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */
|
||||
#define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */
|
||||
#define ADC_EXTTRIG_INSERTED_T14_TRGO CTL1_ETSIC(5) /*!< TIMER14 TRGO event select */
|
||||
#define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */
|
||||
#define ADC_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */
|
||||
|
||||
/* adc_samptx register value */
|
||||
#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||
#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */
|
||||
|
||||
/* ADC data offset for inserted channel x */
|
||||
#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* ADC analog watchdog high threshold */
|
||||
#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* ADC analog watchdog low threshold */
|
||||
#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* ADC regular channel group length */
|
||||
#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
|
||||
|
||||
/* ADC inserted channel group length */
|
||||
#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
|
||||
|
||||
/* ADC resolution definitions */
|
||||
#define CTL0_DRES(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) /*!< ADC resolution */
|
||||
#define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */
|
||||
|
||||
/* ADC oversampling shift */
|
||||
#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5))
|
||||
#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */
|
||||
|
||||
/* ADC oversampling ratio */
|
||||
#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2))
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */
|
||||
|
||||
/* ADC triggered oversampling */
|
||||
#define ADC_OVERSAMPLING_ALL_CONVERT 0U /*!< all oversampled conversions for a channel are done consecutively after a trigger */
|
||||
#define ADC_OVERSAMPLING_ONE_CONVERT 1U /*!< each oversampled conversion for a channel needs a trigger */
|
||||
|
||||
/* ADC channel group definitions */
|
||||
#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */
|
||||
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */
|
||||
#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */
|
||||
#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */
|
||||
|
||||
/* ADC inserted channel definitions */
|
||||
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */
|
||||
#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */
|
||||
#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */
|
||||
#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */
|
||||
|
||||
/* ADC channel definitions */
|
||||
#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
|
||||
#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
|
||||
#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
|
||||
#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
|
||||
#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
|
||||
#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
|
||||
#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
|
||||
#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
|
||||
#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
|
||||
#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
|
||||
#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
|
||||
#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
|
||||
|
||||
/* ADC interrupt definitions */
|
||||
#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
|
||||
#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */
|
||||
#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */
|
||||
|
||||
/* ADC interrupt flag */
|
||||
#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */
|
||||
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */
|
||||
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */
|
||||
|
||||
/* function declarations */
|
||||
/* reset ADC */
|
||||
void adc_deinit(void);
|
||||
/* enable ADC interface */
|
||||
void adc_enable(void);
|
||||
/* disable ADC interface */
|
||||
void adc_disable(void);
|
||||
|
||||
/* ADC calibration and reset calibration */
|
||||
void adc_calibration_enable(void);
|
||||
/* enable DMA request */
|
||||
void adc_dma_mode_enable(void);
|
||||
/* disable DMA request */
|
||||
void adc_dma_mode_disable(void);
|
||||
|
||||
/* enable the temperature sensor and Vrefint channel */
|
||||
void adc_tempsensor_vrefint_enable(void);
|
||||
/* disable the temperature sensor and Vrefint channel */
|
||||
void adc_tempsensor_vrefint_disable(void);
|
||||
|
||||
/* configure ADC discontinuous mode */
|
||||
void adc_discontinuous_mode_config(uint8_t channel_group, uint8_t length);
|
||||
/* configure ADC special function */
|
||||
void adc_special_function_config(uint32_t function, ControlStatus newvalue);
|
||||
|
||||
/* configure ADC data alignment */
|
||||
void adc_data_alignment_config(uint32_t data_alignment);
|
||||
/* configure the length of regular channel group or inserted channel group */
|
||||
void adc_channel_length_config(uint8_t channel_group, uint32_t length);
|
||||
/* configure ADC regular channel */
|
||||
void adc_regular_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
|
||||
/* configure ADC inserted channel */
|
||||
void adc_inserted_channel_config(uint8_t rank, uint8_t channel, uint32_t sample_time);
|
||||
/* configure ADC inserted channel offset */
|
||||
void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset);
|
||||
/* enable ADC external trigger */
|
||||
void adc_external_trigger_config(uint8_t channel_group, ControlStatus newvalue);
|
||||
/* configure ADC external trigger source */
|
||||
void adc_external_trigger_source_config(uint8_t channel_group, uint32_t external_trigger_source);
|
||||
/* enable ADC software trigger */
|
||||
void adc_software_trigger_enable(uint8_t channel_group);
|
||||
|
||||
/* read ADC regular group data register */
|
||||
uint16_t adc_regular_data_read(void);
|
||||
/* read ADC inserted group data register */
|
||||
uint16_t adc_inserted_data_read(uint8_t inserted_channel);
|
||||
|
||||
/* get the ADC flag bits */
|
||||
FlagStatus adc_flag_get(uint32_t flag);
|
||||
/* clear the ADC flag bits */
|
||||
void adc_flag_clear(uint32_t flag);
|
||||
/* get the ADC interrupt bits */
|
||||
FlagStatus adc_interrupt_flag_get(uint32_t flag);
|
||||
/* clear the ADC flag */
|
||||
void adc_interrupt_flag_clear(uint32_t flag);
|
||||
/* enable ADC interrupt */
|
||||
void adc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable ADC interrupt */
|
||||
void adc_interrupt_disable(uint32_t interrupt);
|
||||
|
||||
/* configure ADC analog watchdog single channel */
|
||||
void adc_watchdog_single_channel_enable(uint8_t channel);
|
||||
/* configure ADC analog watchdog group channel */
|
||||
void adc_watchdog_group_channel_enable(uint8_t channel_group);
|
||||
/* disable ADC analog watchdog */
|
||||
void adc_watchdog_disable(void);
|
||||
/* configure ADC analog watchdog threshold */
|
||||
void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold);
|
||||
|
||||
/* configure ADC resolution */
|
||||
void adc_resolution_config(uint32_t resolution);
|
||||
/* configure ADC oversample mode */
|
||||
void adc_oversample_mode_config(uint8_t mode, uint16_t shift, uint8_t ratio);
|
||||
/* enable ADC oversample mode */
|
||||
void adc_oversample_mode_enable(void);
|
||||
/* disable ADC oversample mode */
|
||||
void adc_oversample_mode_disable(void);
|
||||
|
||||
#endif /* GD32E23X_ADC_H */
|
||||
@@ -0,0 +1,162 @@
|
||||
/*!
|
||||
\file gd32e23x_cmp.h
|
||||
\brief definitions for the CMP
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
\version 2021-05-19, V1.1.1, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_CMP_H
|
||||
#define GD32E23X_CMP_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* CMP definitions */
|
||||
#define CMP CMP_BASE /*!< CMP base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define CMP_CS REG32((CMP) + 0x00U) /*!< CMP control and status register */
|
||||
|
||||
/* CMP_CS bits definitions */
|
||||
#define CMP_CS_CMPEN BIT(0) /*!< CMP enable */
|
||||
#define CMP_CS_CMPSW BIT(1) /*!< CMP switch */
|
||||
#define CMP_CS_CMPM BITS(2,3) /*!< CMP mode */
|
||||
#define CMP_CS_CMPMSEL BITS(4,6) /*!< COMP_M input selection */
|
||||
#define CMP_CS_CMPOSEL BITS(8,10) /*!< CMP output selection */
|
||||
#define CMP_CS_CMPPL BIT(11) /*!< polarity of CMP output */
|
||||
#define CMP_CS_CMPHST BITS(12,13) /*!< CMP hysteresis */
|
||||
#define CMP_CS_CMPO BIT(14) /*!< CMP output */
|
||||
#define CMP_CS_CMPLK BIT(15) /*!< CMP lock */
|
||||
|
||||
/* consts definitions */
|
||||
/* operating mode */
|
||||
typedef enum{
|
||||
CMP_HIGHSPEED = 0, /*!< high speed mode */
|
||||
CMP_MIDDLESPEED, /*!< medium speed mode */
|
||||
CMP_LOWSPEED, /*!< low speed mode */
|
||||
CMP_VERYLOWSPEED /*!< very-low speed mode */
|
||||
}operating_mode_enum;
|
||||
|
||||
/* inverting input */
|
||||
typedef enum{
|
||||
CMP_1_4VREFINT = 0, /*!< VREFINT /4 input */
|
||||
CMP_1_2VREFINT, /*!< VREFINT /2 input */
|
||||
CMP_3_4VREFINT, /*!< VREFINT *3/4 input */
|
||||
CMP_VREFINT, /*!< VREFINT input */
|
||||
CMP_PA4, /*!< PA4 input */
|
||||
CMP_PA5, /*!< PA5 input */
|
||||
CMP_PA0, /*!< PA0 input */
|
||||
CMP_PA2 /*!< PA2 input */
|
||||
}inverting_input_enum;
|
||||
|
||||
/* hysteresis */
|
||||
typedef enum{
|
||||
CMP_HYSTERESIS_NO = 0, /*!< output no hysteresis */
|
||||
CMP_HYSTERESIS_LOW, /*!< output low hysteresis */
|
||||
CMP_HYSTERESIS_MIDDLE, /*!< output middle hysteresis */
|
||||
CMP_HYSTERESIS_HIGH /*!< output high hysteresis */
|
||||
}cmp_hysteresis_enum;
|
||||
|
||||
/* output */
|
||||
typedef enum{
|
||||
CMP_OUTPUT_NONE = 0x0U, /*!< output no selection */
|
||||
CMP_OUTPUT_TIMER0BKIN = 0x1U, /*!< TIMER 0 break input */
|
||||
CMP_OUTPUT_TIMER0IC0 = 0x2U, /*!< TIMER 0 channel0 input capture */
|
||||
CMP_OUTPUT_TIMER0OCPRECLR = 0x3U, /*!< TIMER 0 OCPRE_CLR input */
|
||||
CMP_OUTPUT_TIMER2IC0 = 0x06U, /*!< TIMER 2 channel0 input capture */
|
||||
CMP_OUTPUT_TIMER2OCPRECLR = 0x7U /*!< TIMER 2 OCPRE_CLR input */
|
||||
}cmp_output_enum;
|
||||
|
||||
/* CMP mode */
|
||||
#define CS_CMPM(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
|
||||
#define CS_CMPM_HIGHSPEED CS_CMPM(0) /*!< CMP mode high speed */
|
||||
#define CS_CMPM_MIDDLESPEED CS_CMPM(1) /*!< CMP mode middle speed */
|
||||
#define CS_CMPM_LOWSPEED CS_CMPM(2) /*!< CMP mode low speed */
|
||||
#define CS_CMPM_VERYLOWSPEED CS_CMPM(3) /*!< CMP mode very low speed */
|
||||
|
||||
/* comparator inverting input */
|
||||
#define CS_CMPMSEL(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
|
||||
#define CS_CMPMSEL_1_4VREFINT CS_CMPMSEL(0) /*!< CMP inverting input 1/4 Vrefint */
|
||||
#define CS_CMPMSEL_1_2VREFINT CS_CMPMSEL(1) /*!< CMP inverting input 1/2 Vrefint */
|
||||
#define CS_CMPMSEL_3_4VREFINT CS_CMPMSEL(2) /*!< CMP inverting input 3/4 Vrefint */
|
||||
#define CS_CMPMSEL_VREFINT CS_CMPMSEL(3) /*!< CMP inverting input Vrefint */
|
||||
#define CS_CMPMSEL_PA4 CS_CMPMSEL(4) /*!< CMP inverting input PA4*/
|
||||
#define CS_CMPMSEL_PA5 CS_CMPMSEL(5) /*!< CMP inverting input PA5*/
|
||||
#define CS_CMPMSEL_PA0 CS_CMPMSEL(6) /*!< CMP inverting input PA0*/
|
||||
#define CS_CMPMSEL_PA2 CS_CMPMSEL(7) /*!< CMP inverting input PA2*/
|
||||
|
||||
/* CMP output */
|
||||
#define CS_CMPOSEL(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
|
||||
#define CS_CMPOSEL_OUTPUT_NONE CS_CMPOSEL(0) /*!< CMP output none */
|
||||
#define CS_CMPOSEL_OUTPUT_TIMER0BKIN CS_CMPOSEL(1) /*!< CMP output TIMER 0 break input */
|
||||
#define CS_CMPOSEL_OUTPUT_TIMER0IC0 CS_CMPOSEL(2) /*!< CMP output TIMER 0 channel 0 input capture */
|
||||
#define CS_CMPOSEL_OUTPUT_TIMER0OCPRECLR CS_CMPOSEL(3) /*!< CMP output TIMER 0 ocpreclear input */
|
||||
#define CS_CMPOSEL_OUTPUT_TIMER2IC0 CS_CMPOSEL(6) /*!< CMP output TIMER 2 channle 0 input capture */
|
||||
#define CS_CMPOSEL_OUTPUT_TIMER2OCPRECLR CS_CMPOSEL(7) /*!< CMP output TIMER 2 ocpreclear input */
|
||||
|
||||
/* CMP hysteresis */
|
||||
#define CS_CMPHST(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
|
||||
#define CS_CMPHST_HYSTERESIS_NO CS_CMPHST(0) /*!< CMP output no hysteresis */
|
||||
#define CS_CMPHST_HYSTERESIS_LOW CS_CMPHST(1) /*!< CMP output low hysteresis */
|
||||
#define CS_CMPHST_HYSTERESIS_MIDDLE CS_CMPHST(2) /*!< CMP output middle hysteresis */
|
||||
#define CS_CMPHST_HYSTERESIS_HIGH CS_CMPHST(3) /*!< CMP output high hysteresis */
|
||||
|
||||
/* CMP output level */
|
||||
#define CMP_OUTPUTLEVEL_HIGH ((uint32_t)0x00000001) /*!< comparator output high */
|
||||
#define CMP_OUTPUTLEVEL_LOW ((uint32_t)0x00000000) /*!< comparator output low */
|
||||
|
||||
/* output polarity of comparator */
|
||||
#define CMP_OUTPUT_POLARITY_INVERTED ((uint32_t)0x00000001) /*!< output is inverted */
|
||||
#define CMP_OUTPUT_POLARITY_NOINVERTED ((uint32_t)0x00000000) /*!< output is not inverted */
|
||||
|
||||
/* function declarations */
|
||||
|
||||
/* initialization functions */
|
||||
/* CMP deinit */
|
||||
void cmp_deinit(void);
|
||||
/* CMP mode init */
|
||||
void cmp_mode_init(operating_mode_enum operating_mode, inverting_input_enum inverting_input, cmp_hysteresis_enum output_hysteresis);
|
||||
/* CMP output init */
|
||||
void cmp_output_init(cmp_output_enum output_selection, uint32_t output_polarity);
|
||||
/* enable CMP */
|
||||
void cmp_enable(void);
|
||||
/* disable CMP */
|
||||
void cmp_disable(void);
|
||||
/* enable CMP switch */
|
||||
void cmp_switch_enable(void);
|
||||
/* disable CMP switch */
|
||||
void cmp_switch_disable(void);
|
||||
/* get output level */
|
||||
uint32_t cmp_output_level_get(void);
|
||||
/* lock the CMP */
|
||||
void cmp_lock_enable(void);
|
||||
|
||||
#endif /* GD32E23X_CMP_H */
|
||||
@@ -0,0 +1,124 @@
|
||||
/*!
|
||||
\file gd32e23x_crc.h
|
||||
\brief definitions for the CRC
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_CRC_H
|
||||
#define GD32E23X_CRC_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* CRC definitions */
|
||||
#define CRC CRC_BASE /*!< CRC bsae address */
|
||||
|
||||
/* registers definitions */
|
||||
#define CRC_DATA REG32((CRC) + 0x00000000U) /*!< CRC data register */
|
||||
#define CRC_FDATA REG32((CRC) + 0x00000004U) /*!< CRC free data register */
|
||||
#define CRC_CTL REG32((CRC) + 0x00000008U) /*!< CRC control register */
|
||||
#define CRC_IDATA REG32((CRC) + 0x00000010U) /*!< CRC initialization data register */
|
||||
#define CRC_POLY REG32((CRC) + 0x00000014U) /*!< CRC polynomial register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CRC_DATA */
|
||||
#define CRC_DATA_DATA BITS(0,31) /*!< CRC data bits */
|
||||
|
||||
/* CRC_FDATA */
|
||||
#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
|
||||
|
||||
/* CRC_CTL */
|
||||
#define CRC_CTL_RST BIT(0) /*!< CRC reset bit */
|
||||
#define CRC_CTL_PS BITS(3,4) /*!< size of polynomial function bits */
|
||||
#define CRC_CTL_REV_I BITS(5,6) /*!< input data reverse function bits */
|
||||
#define CRC_CTL_REV_O BIT(7) /*!< output data reverse function bit */
|
||||
|
||||
/* CRC_INIT */
|
||||
#define CRC_IDATA_IDATA BITS(0,31) /*!< CRC initialization data bits */
|
||||
|
||||
/* CRC_POLY */
|
||||
#define CRC_POLY_POLY BITS(0,31) /*!< CRC polynomial value bits */
|
||||
|
||||
/* constants definitions */
|
||||
/* size of polynomial function */
|
||||
#define CTL_PS(regval) (BITS(3, 4) & ((regval) << 3))
|
||||
#define CRC_CTL_PS_32 CTL_PS(0) /*!< 32-bit polynomial for CRC calculation */
|
||||
#define CRC_CTL_PS_16 CTL_PS(1) /*!< 16-bit polynomial for CRC calculation */
|
||||
#define CRC_CTL_PS_8 CTL_PS(2) /*!< 8-bit polynomial for CRC calculation */
|
||||
#define CRC_CTL_PS_7 CTL_PS(3) /*!< 7-bit polynomial for CRC calculation */
|
||||
|
||||
/* input data reverse function */
|
||||
#define CTL_REV_I(regval) (BITS(5, 6) & ((regval) << 5))
|
||||
#define CRC_INPUT_DATA_NOT CTL_REV_I(0) /*!< input data not reverse */
|
||||
#define CRC_INPUT_DATA_BYTE CTL_REV_I(1) /*!< input data reversed by byte type */
|
||||
#define CRC_INPUT_DATA_HALFWORD CTL_REV_I(2) /*!< input data reversed by half-word type */
|
||||
#define CRC_INPUT_DATA_WORD CTL_REV_I(3) /*!< input data reversed by word type */
|
||||
|
||||
/* input data format */
|
||||
#define INPUT_FORMAT_WORD 0U /*!< input data in word format */
|
||||
#define INPUT_FORMAT_HALFWORD 1U /*!< input data in half-word format */
|
||||
#define INPUT_FORMAT_BYTE 2U /*!< input data in byte format */
|
||||
|
||||
/* function declarations */
|
||||
/* deinit CRC calculation unit */
|
||||
void crc_deinit(void);
|
||||
|
||||
/* enable the reverse operation of output data */
|
||||
void crc_reverse_output_data_enable(void);
|
||||
/* disable the reverse operation of output data */
|
||||
void crc_reverse_output_data_disable(void);
|
||||
|
||||
/* reset data register to the value of initialization data register */
|
||||
void crc_data_register_reset(void);
|
||||
/* read the data register */
|
||||
uint32_t crc_data_register_read(void);
|
||||
|
||||
/* read the free data register */
|
||||
uint8_t crc_free_data_register_read(void);
|
||||
/* write the free data register */
|
||||
void crc_free_data_register_write(uint8_t free_data);
|
||||
|
||||
/* write the initial value register */
|
||||
void crc_init_data_register_write(uint32_t init_data);
|
||||
/* configure the CRC input data function */
|
||||
void crc_input_data_reverse_config(uint32_t data_reverse);
|
||||
|
||||
/* configure the CRC size of polynomial function */
|
||||
void crc_polynomial_size_set(uint32_t poly_size);
|
||||
/* configure the CRC polynomial value function */
|
||||
void crc_polynomial_set(uint32_t poly);
|
||||
|
||||
/* CRC calculate single data */
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata, uint8_t data_format);
|
||||
/* CRC calculate a data array */
|
||||
uint32_t crc_block_data_calculate(void *array, uint32_t size, uint8_t data_format);
|
||||
|
||||
#endif /* GD32E23X_CRC_H */
|
||||
@@ -0,0 +1,122 @@
|
||||
/*!
|
||||
\file gd32e23x_dbg.h
|
||||
\brief definitions for the DBG
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_DBG_H
|
||||
#define GD32E23X_DBG_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* DBG definitions */
|
||||
#define DBG DBG_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
|
||||
#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */
|
||||
#define DBG_CTL1 REG32(DBG + 0x08U) /*!< DBG control register 1 */
|
||||
|
||||
/* bits definitions */
|
||||
/* DBG_ID */
|
||||
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
|
||||
|
||||
/* DBG_CTL0 */
|
||||
#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
|
||||
#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
|
||||
#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
|
||||
#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< TIMER0 counter kept when core is halted */
|
||||
#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< TIMER2 counter kept when core is halted */
|
||||
#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
|
||||
#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
|
||||
#define DBG_CTL0_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */
|
||||
#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */
|
||||
|
||||
/* DBG_CTL1 */
|
||||
#define DBG_CTL1_RTC_HOLD BIT(10) /*!< hold RTC calendar and wakeup counter when core is halted */
|
||||
#define DBG_CTL1_TIMER14_HOLD BIT(16) /*!< hold TIMER14 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER15_HOLD BIT(17) /*!< hold TIMER15 counter when core is halted */
|
||||
#define DBG_CTL1_TIMER16_HOLD BIT(18) /*!< hold TIMER16 counter when core is halted */
|
||||
|
||||
/* constants definitions */
|
||||
#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
|
||||
|
||||
/* define the peripheral debug hold bit position and its register index offset */
|
||||
#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
|
||||
#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
|
||||
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
|
||||
/* register index */
|
||||
enum dbg_reg_idx
|
||||
{
|
||||
DBG_IDX_CTL0 = 0x04U,
|
||||
DBG_IDX_CTL1 = 0x08U,
|
||||
};
|
||||
|
||||
/* peripherals hold bit */
|
||||
typedef enum
|
||||
{
|
||||
DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< FWDGT hold bit */
|
||||
DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< WWDGT hold bit */
|
||||
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), /*!< TIMER0 hold bit */
|
||||
DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< TIMER2 hold bit */
|
||||
DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U), /*!< TIMER5 hold bit */
|
||||
DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), /*!< TIMER13 hold bit */
|
||||
DBG_TIMER14_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 16U), /*!< TIMER14 hold bit */
|
||||
DBG_TIMER15_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 17U), /*!< TIMER15 hold bit */
|
||||
DBG_TIMER16_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 18U), /*!< TIMER16 hold bit */
|
||||
DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< I2C0 hold bit */
|
||||
DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< I2C1 hold bit */
|
||||
DBG_RTC_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL1, 10U), /*!< RTC hold bit */
|
||||
}dbg_periph_enum;
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize the DBG */
|
||||
void dbg_deinit(void);
|
||||
/* read DBG_ID code register */
|
||||
uint32_t dbg_id_get(void);
|
||||
|
||||
/* enable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power);
|
||||
/* disable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power);
|
||||
|
||||
/* enable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph);
|
||||
/* disable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph);
|
||||
|
||||
#endif /* GD32E23X_DBG_H */
|
||||
@@ -0,0 +1,263 @@
|
||||
/*!
|
||||
\file gd32e23x_dma.h
|
||||
\brief definitions for the DMA
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_DMA_H
|
||||
#define GD32E23X_DMA_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* DMA definitions */
|
||||
#define DMA DMA_BASE /*!< DMA base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define DMA_INTF REG32(DMA + 0x00U) /*!< DMA interrupt flag register */
|
||||
#define DMA_INTC REG32(DMA + 0x04U) /*!< DMA interrupt flag clear register */
|
||||
#define DMA_CH0CTL REG32(DMA + 0x08U) /*!< DMA channel 0 control register */
|
||||
#define DMA_CH0CNT REG32(DMA + 0x0CU) /*!< DMA channel 0 counter register */
|
||||
#define DMA_CH0PADDR REG32(DMA + 0x10U) /*!< DMA channel 0 peripheral base address register */
|
||||
#define DMA_CH0MADDR REG32(DMA + 0x14U) /*!< DMA channel 0 memory base address register */
|
||||
#define DMA_CH1CTL REG32(DMA + 0x1CU) /*!< DMA channel 1 control register */
|
||||
#define DMA_CH1CNT REG32(DMA + 0x20U) /*!< DMA channel 1 counter register */
|
||||
#define DMA_CH1PADDR REG32(DMA + 0x24U) /*!< DMA channel 1 peripheral base address register */
|
||||
#define DMA_CH1MADDR REG32(DMA + 0x28U) /*!< DMA channel 1 memory base address register */
|
||||
#define DMA_CH2CTL REG32(DMA + 0x30U) /*!< DMA channel 2 control register */
|
||||
#define DMA_CH2CNT REG32(DMA + 0x34U) /*!< DMA channel 2 counter register */
|
||||
#define DMA_CH2PADDR REG32(DMA + 0x38U) /*!< DMA channel 2 peripheral base address register */
|
||||
#define DMA_CH2MADDR REG32(DMA + 0x3CU) /*!< DMA channel 2 memory base address register */
|
||||
#define DMA_CH3CTL REG32(DMA + 0x44U) /*!< DMA channel 3 control register */
|
||||
#define DMA_CH3CNT REG32(DMA + 0x48U) /*!< DMA channel 3 counter register */
|
||||
#define DMA_CH3PADDR REG32(DMA + 0x4CU) /*!< DMA channel 3 peripheral base address register */
|
||||
#define DMA_CH3MADDR REG32(DMA + 0x50U) /*!< DMA channel 3 memory base address register */
|
||||
#define DMA_CH4CTL REG32(DMA + 0x58U) /*!< DMA channel 4 control register */
|
||||
#define DMA_CH4CNT REG32(DMA + 0x5CU) /*!< DMA channel 4 counter register */
|
||||
#define DMA_CH4PADDR REG32(DMA + 0x60U) /*!< DMA channel 4 peripheral base address register */
|
||||
#define DMA_CH4MADDR REG32(DMA + 0x64U) /*!< DMA channel 4 memory base address register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DMA_INTF */
|
||||
#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */
|
||||
#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */
|
||||
#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */
|
||||
#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */
|
||||
|
||||
/* DMA_INTC */
|
||||
#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */
|
||||
#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */
|
||||
#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */
|
||||
#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */
|
||||
|
||||
/* DMA_CHxCTL,x=0..4 */
|
||||
#define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */
|
||||
#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel x transfer complete interrupt */
|
||||
#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel x transfer half complete interrupt */
|
||||
#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel x error interrupt */
|
||||
#define DMA_CHXCTL_DIR BIT(4) /*!< direction of the data transfer on the channel */
|
||||
#define DMA_CHXCTL_CMEN BIT(5) /*!< circulation mode */
|
||||
#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */
|
||||
#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */
|
||||
#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data size of peripheral */
|
||||
#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data size of memory */
|
||||
#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level of channelx */
|
||||
#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */
|
||||
|
||||
/* DMA_CHxCNT,x=0..4 */
|
||||
#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */
|
||||
|
||||
/* DMA_CHxPADDR,x=0..4 */
|
||||
#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
|
||||
|
||||
/* DMA_CHxMADDR,x=0..4 */
|
||||
#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */
|
||||
|
||||
/* constants definitions */
|
||||
/* DMA channel select */
|
||||
typedef enum
|
||||
{
|
||||
DMA_CH0 = 0, /*!< DMA Channel0 */
|
||||
DMA_CH1, /*!< DMA Channel1 */
|
||||
DMA_CH2, /*!< DMA Channel2 */
|
||||
DMA_CH3, /*!< DMA Channel3 */
|
||||
DMA_CH4, /*!< DMA Channel4 */
|
||||
} dma_channel_enum;
|
||||
|
||||
/* DMA initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t periph_addr; /*!< peripheral base address */
|
||||
uint32_t periph_width; /*!< transfer data size of peripheral */
|
||||
uint32_t memory_addr; /*!< memory base address */
|
||||
uint32_t memory_width; /*!< transfer data size of memory */
|
||||
uint32_t number; /*!< channel transfer number */
|
||||
uint32_t priority; /*!< channel priority level */
|
||||
uint8_t periph_inc; /*!< peripheral increasing mode */
|
||||
uint8_t memory_inc; /*!< memory increasing mode */
|
||||
uint8_t direction; /*!< channel data transfer direction */
|
||||
} dma_parameter_struct;
|
||||
|
||||
/* DMA reset value */
|
||||
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
|
||||
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
|
||||
#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \
|
||||
DMA_INTF_HTFIF | DMA_INTF_ERRIF)
|
||||
|
||||
#define DMA_FLAG_ADD(flag,shift) ((flag) << ((uint32_t)(shift) * 4U)) /*!< DMA channel flag shift */
|
||||
|
||||
/* DMA_CHCTL base address */
|
||||
#define DMA_CHXCTL_BASE (DMA + 0x08U) /*!< the base address of DMA channel CHXCTL register */
|
||||
#define DMA_CHXCNT_BASE (DMA + 0x0CU) /*!< the base address of DMA channel CHXCNT register */
|
||||
#define DMA_CHXPADDR_BASE (DMA + 0x10U) /*!< the base address of DMA channel CHXPADDR register */
|
||||
#define DMA_CHXMADDR_BASE (DMA + 0x14U) /*!< the base address of DMA channel CHXMADDR register */
|
||||
|
||||
/* DMA channel shift bit */
|
||||
#define DMA_CHCTL(channel) REG32(DMA_CHXCTL_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR(channel) REG32(DMA_CHXPADDR_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */
|
||||
#define DMA_CHMADDR(channel) REG32(DMA_CHXMADDR_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */
|
||||
|
||||
/* DMA_INTF register */
|
||||
/* interrupt flag bits */
|
||||
#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */
|
||||
|
||||
/* flag bits */
|
||||
#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
|
||||
#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */
|
||||
#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */
|
||||
#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */
|
||||
|
||||
/* DMA_CHxCTL register */
|
||||
/* interrupt enable bits */
|
||||
#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */
|
||||
#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */
|
||||
#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */
|
||||
|
||||
/* transfer direction */
|
||||
#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x00U) /*!< read from peripheral and write to memory */
|
||||
#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x01U) /*!< read from memory and write to peripheral */
|
||||
|
||||
/* peripheral increasing mode */
|
||||
#define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of peripheral is fixed address mode */
|
||||
#define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of peripheral is increasing address mode */
|
||||
|
||||
/* memory increasing mode */
|
||||
#define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of memory is fixed address mode */
|
||||
#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of memory is increasing address mode */
|
||||
|
||||
/* transfer data size of peripheral */
|
||||
#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */
|
||||
#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */
|
||||
#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */
|
||||
#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */
|
||||
|
||||
/* transfer data size of memory */
|
||||
#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */
|
||||
#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */
|
||||
#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */
|
||||
#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */
|
||||
|
||||
/* channel priority level */
|
||||
#define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */
|
||||
#define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */
|
||||
#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */
|
||||
#define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */
|
||||
#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */
|
||||
|
||||
/* DMA_CHxCNT register */
|
||||
/* transfer counter */
|
||||
#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize DMA a channel registers */
|
||||
void dma_deinit(dma_channel_enum channelx);
|
||||
/* initialize the parameters of DMA struct with the default values */
|
||||
void dma_struct_para_init(dma_parameter_struct* init_struct);
|
||||
/* initialize DMA channel */
|
||||
void dma_init(dma_channel_enum channelx, dma_parameter_struct* init_struct);
|
||||
/* enable DMA circulation mode */
|
||||
void dma_circulation_enable(dma_channel_enum channelx);
|
||||
/* disable DMA circulation mode */
|
||||
void dma_circulation_disable(dma_channel_enum channelx);
|
||||
/* enable memory to memory mode */
|
||||
void dma_memory_to_memory_enable(dma_channel_enum channelx);
|
||||
/* disable memory to memory mode */
|
||||
void dma_memory_to_memory_disable(dma_channel_enum channelx);
|
||||
/* enable DMA channel */
|
||||
void dma_channel_enable(dma_channel_enum channelx);
|
||||
/* disable DMA channel */
|
||||
void dma_channel_disable(dma_channel_enum channelx);
|
||||
|
||||
/* set DMA peripheral base address */
|
||||
void dma_periph_address_config(dma_channel_enum channelx, uint32_t address);
|
||||
/* set DMA memory base address */
|
||||
void dma_memory_address_config(dma_channel_enum channelx, uint32_t address);
|
||||
/* set the number of remaining data to be transferred by the DMA */
|
||||
void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number);
|
||||
/* get the number of remaining data to be transferred by the DMA */
|
||||
uint32_t dma_transfer_number_get(dma_channel_enum channelx);
|
||||
/* configure priority level of DMA channel */
|
||||
void dma_priority_config(dma_channel_enum channelx, uint32_t priority);
|
||||
/* configure transfer data size of memory */
|
||||
void dma_memory_width_config (dma_channel_enum channelx, uint32_t mwidth);
|
||||
/* configure transfer data size of peripheral */
|
||||
void dma_periph_width_config (dma_channel_enum channelx, uint32_t pwidth);
|
||||
/* enable next address increasement algorithm of memory */
|
||||
void dma_memory_increase_enable(dma_channel_enum channelx);
|
||||
/* disable next address increasement algorithm of memory */
|
||||
void dma_memory_increase_disable(dma_channel_enum channelx);
|
||||
/* enable next address increasement algorithm of peripheral */
|
||||
void dma_periph_increase_enable(dma_channel_enum channelx);
|
||||
/* disable next address increasement algorithm of peripheral */
|
||||
void dma_periph_increase_disable(dma_channel_enum channelx);
|
||||
/* configure the direction of data transfer on the channel */
|
||||
void dma_transfer_direction_config(dma_channel_enum channelx, uint8_t direction);
|
||||
|
||||
/* check DMA flag is set or not */
|
||||
FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag);
|
||||
/* clear DMA a channel flag */
|
||||
void dma_flag_clear(dma_channel_enum channelx, uint32_t flag);
|
||||
/* check DMA flag and interrupt enable bit is set or not */
|
||||
FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t flag);
|
||||
/* clear DMA a channel flag */
|
||||
void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t flag);
|
||||
/* enable DMA interrupt */
|
||||
void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source);
|
||||
/* disable DMA interrupt */
|
||||
void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source);
|
||||
|
||||
#endif /* GD32E23X_DMA_H */
|
||||
@@ -0,0 +1,282 @@
|
||||
/*!
|
||||
\file gd32e23x_exti.h
|
||||
\brief definitions for the EXTI
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_EXTI_H
|
||||
#define GD32E23X_EXTI_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* EXTI definitions */
|
||||
#define EXTI EXTI_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define EXTI_INTEN REG32(EXTI + 0x00000000U) /*!< interrupt enable register */
|
||||
#define EXTI_EVEN REG32(EXTI + 0x00000004U) /*!< event enable register */
|
||||
#define EXTI_RTEN REG32(EXTI + 0x00000008U) /*!< rising edge trigger enable register */
|
||||
#define EXTI_FTEN REG32(EXTI + 0x0000000CU) /*!< falling trigger enable register */
|
||||
#define EXTI_SWIEV REG32(EXTI + 0x00000010U) /*!< software interrupt event register */
|
||||
#define EXTI_PD REG32(EXTI + 0x00000014U) /*!< pending register */
|
||||
|
||||
/* bits definitions */
|
||||
/* EXTI_INTEN */
|
||||
#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */
|
||||
#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */
|
||||
#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */
|
||||
#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */
|
||||
#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */
|
||||
#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */
|
||||
#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */
|
||||
#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */
|
||||
#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */
|
||||
#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */
|
||||
#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */
|
||||
#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */
|
||||
#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */
|
||||
#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */
|
||||
#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */
|
||||
#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */
|
||||
#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */
|
||||
#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */
|
||||
#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */
|
||||
#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */
|
||||
#define EXTI_INTEN_INTEN20 BIT(20) /*!< interrupt from line 20 */
|
||||
#define EXTI_INTEN_INTEN21 BIT(21) /*!< interrupt from line 21 */
|
||||
#define EXTI_INTEN_INTEN22 BIT(22) /*!< interrupt from line 22 */
|
||||
#define EXTI_INTEN_INTEN23 BIT(23) /*!< interrupt from line 23 */
|
||||
#define EXTI_INTEN_INTEN24 BIT(24) /*!< interrupt from line 24 */
|
||||
#define EXTI_INTEN_INTEN25 BIT(25) /*!< interrupt from line 25 */
|
||||
#define EXTI_INTEN_INTEN26 BIT(26) /*!< interrupt from line 26 */
|
||||
#define EXTI_INTEN_INTEN27 BIT(27) /*!< interrupt from line 27 */
|
||||
|
||||
/* EXTI_EVEN */
|
||||
#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */
|
||||
#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */
|
||||
#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */
|
||||
#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */
|
||||
#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */
|
||||
#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */
|
||||
#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */
|
||||
#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */
|
||||
#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */
|
||||
#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */
|
||||
#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */
|
||||
#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */
|
||||
#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */
|
||||
#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */
|
||||
#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */
|
||||
#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */
|
||||
#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */
|
||||
#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */
|
||||
#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */
|
||||
#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */
|
||||
#define EXTI_EVEN_EVEN20 BIT(20) /*!< event from line 20 */
|
||||
#define EXTI_EVEN_EVEN21 BIT(21) /*!< event from line 21 */
|
||||
#define EXTI_EVEN_EVEN22 BIT(22) /*!< event from line 22 */
|
||||
#define EXTI_EVEN_EVEN23 BIT(23) /*!< event from line 23 */
|
||||
#define EXTI_EVEN_EVEN24 BIT(24) /*!< event from line 24 */
|
||||
#define EXTI_EVEN_EVEN25 BIT(25) /*!< event from line 25 */
|
||||
#define EXTI_EVEN_EVEN26 BIT(26) /*!< event from line 26 */
|
||||
#define EXTI_EVEN_EVEN27 BIT(27) /*!< event from line 27 */
|
||||
|
||||
/* EXTI_RTEN */
|
||||
#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */
|
||||
#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */
|
||||
#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */
|
||||
#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */
|
||||
#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */
|
||||
#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */
|
||||
#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */
|
||||
#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */
|
||||
#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */
|
||||
#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */
|
||||
#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */
|
||||
#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */
|
||||
#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */
|
||||
#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */
|
||||
#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */
|
||||
#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */
|
||||
#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */
|
||||
#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */
|
||||
#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */
|
||||
#define EXTI_RTEN_RTEN21 BIT(21) /*!< rising edge from line 21 */
|
||||
|
||||
/* EXTI_FTEN */
|
||||
#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */
|
||||
#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */
|
||||
#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */
|
||||
#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */
|
||||
#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */
|
||||
#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */
|
||||
#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */
|
||||
#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */
|
||||
#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */
|
||||
#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */
|
||||
#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */
|
||||
#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */
|
||||
#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */
|
||||
#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */
|
||||
#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */
|
||||
#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */
|
||||
#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */
|
||||
#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */
|
||||
#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */
|
||||
#define EXTI_FTEN_FTEN21 BIT(21) /*!< falling edge from line 21 */
|
||||
|
||||
/* EXTI_SWIEV */
|
||||
#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */
|
||||
#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */
|
||||
#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */
|
||||
#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */
|
||||
#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */
|
||||
#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */
|
||||
#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */
|
||||
#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */
|
||||
#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */
|
||||
#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */
|
||||
#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */
|
||||
#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */
|
||||
#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */
|
||||
#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */
|
||||
#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */
|
||||
#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */
|
||||
#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */
|
||||
#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */
|
||||
#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */
|
||||
#define EXTI_SWIEV_SWIEV21 BIT(21) /*!< software interrupt/event request from line 21 */
|
||||
|
||||
/* EXTI_PD */
|
||||
#define EXTI_PD_PD0 BIT(0) /*!< interrupt/event pending status from line 0 */
|
||||
#define EXTI_PD_PD1 BIT(1) /*!< interrupt/event pending status from line 1 */
|
||||
#define EXTI_PD_PD2 BIT(2) /*!< interrupt/event pending status from line 2 */
|
||||
#define EXTI_PD_PD3 BIT(3) /*!< interrupt/event pending status from line 3 */
|
||||
#define EXTI_PD_PD4 BIT(4) /*!< interrupt/event pending status from line 4 */
|
||||
#define EXTI_PD_PD5 BIT(5) /*!< interrupt/event pending status from line 5 */
|
||||
#define EXTI_PD_PD6 BIT(6) /*!< interrupt/event pending status from line 6 */
|
||||
#define EXTI_PD_PD7 BIT(7) /*!< interrupt/event pending status from line 7 */
|
||||
#define EXTI_PD_PD8 BIT(8) /*!< interrupt/event pending status from line 8 */
|
||||
#define EXTI_PD_PD9 BIT(9) /*!< interrupt/event pending status from line 9 */
|
||||
#define EXTI_PD_PD10 BIT(10) /*!< interrupt/event pending status from line 10 */
|
||||
#define EXTI_PD_PD11 BIT(11) /*!< interrupt/event pending status from line 11 */
|
||||
#define EXTI_PD_PD12 BIT(12) /*!< interrupt/event pending status from line 12 */
|
||||
#define EXTI_PD_PD13 BIT(13) /*!< interrupt/event pending status from line 13 */
|
||||
#define EXTI_PD_PD14 BIT(14) /*!< interrupt/event pending status from line 14 */
|
||||
#define EXTI_PD_PD15 BIT(15) /*!< interrupt/event pending status from line 15 */
|
||||
#define EXTI_PD_PD16 BIT(16) /*!< interrupt/event pending status from line 16 */
|
||||
#define EXTI_PD_PD17 BIT(17) /*!< interrupt/event pending status from line 17 */
|
||||
#define EXTI_PD_PD19 BIT(19) /*!< interrupt/event pending status from line 19 */
|
||||
#define EXTI_PD_PD21 BIT(21) /*!< interrupt/event pending status from line 21 */
|
||||
|
||||
/* constants definitions */
|
||||
/* EXTI line number */
|
||||
typedef enum
|
||||
{
|
||||
EXTI_0 = BIT(0), /*!< EXTI line 0 */
|
||||
EXTI_1 = BIT(1), /*!< EXTI line 1 */
|
||||
EXTI_2 = BIT(2), /*!< EXTI line 2 */
|
||||
EXTI_3 = BIT(3), /*!< EXTI line 3 */
|
||||
EXTI_4 = BIT(4), /*!< EXTI line 4 */
|
||||
EXTI_5 = BIT(5), /*!< EXTI line 5 */
|
||||
EXTI_6 = BIT(6), /*!< EXTI line 6 */
|
||||
EXTI_7 = BIT(7), /*!< EXTI line 7 */
|
||||
EXTI_8 = BIT(8), /*!< EXTI line 8 */
|
||||
EXTI_9 = BIT(9), /*!< EXTI line 9 */
|
||||
EXTI_10 = BIT(10), /*!< EXTI line 10 */
|
||||
EXTI_11 = BIT(11), /*!< EXTI line 11 */
|
||||
EXTI_12 = BIT(12), /*!< EXTI line 12 */
|
||||
EXTI_13 = BIT(13), /*!< EXTI line 13 */
|
||||
EXTI_14 = BIT(14), /*!< EXTI line 14 */
|
||||
EXTI_15 = BIT(15), /*!< EXTI line 15 */
|
||||
EXTI_16 = BIT(16), /*!< EXTI line 16 */
|
||||
EXTI_17 = BIT(17), /*!< EXTI line 17 */
|
||||
EXTI_18 = BIT(18), /*!< EXTI line 18 */
|
||||
EXTI_19 = BIT(19), /*!< EXTI line 19 */
|
||||
EXTI_20 = BIT(20), /*!< EXTI line 20 */
|
||||
EXTI_21 = BIT(21), /*!< EXTI line 21 */
|
||||
EXTI_22 = BIT(22), /*!< EXTI line 22 */
|
||||
EXTI_23 = BIT(23), /*!< EXTI line 23 */
|
||||
EXTI_24 = BIT(24), /*!< EXTI line 24 */
|
||||
EXTI_25 = BIT(25), /*!< EXTI line 25 */
|
||||
EXTI_26 = BIT(26), /*!< EXTI line 26 */
|
||||
EXTI_27 = BIT(27), /*!< EXTI line 27 */
|
||||
}exti_line_enum;
|
||||
|
||||
/* external interrupt and event */
|
||||
typedef enum
|
||||
{
|
||||
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
|
||||
EXTI_EVENT /*!< EXTI event mode */
|
||||
}exti_mode_enum;
|
||||
|
||||
/* interrupt trigger mode */
|
||||
typedef enum
|
||||
{
|
||||
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
|
||||
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
|
||||
EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */
|
||||
EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */
|
||||
}exti_trig_type_enum;
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* reset the value of all EXTI registers with initial values */
|
||||
void exti_deinit(void);
|
||||
/* initialize EXTI line x */
|
||||
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
|
||||
|
||||
/* enable functions */
|
||||
/* enable the interrupts from EXTI line x */
|
||||
void exti_interrupt_enable(exti_line_enum linex);
|
||||
/* disable the interrupts from EXTI line x */
|
||||
void exti_interrupt_disable(exti_line_enum linex);
|
||||
/* enable the events from EXTI line x */
|
||||
void exti_event_enable(exti_line_enum linex);
|
||||
/* disable the events from EXTI line x */
|
||||
void exti_event_disable(exti_line_enum linex);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* enable EXTI software interrupt event */
|
||||
void exti_software_interrupt_enable(exti_line_enum linex);
|
||||
/* disable EXTI software interrupt event */
|
||||
void exti_software_interrupt_disable(exti_line_enum linex);
|
||||
/* get EXTI line x pending flag */
|
||||
FlagStatus exti_flag_get(exti_line_enum linex);
|
||||
/* clear EXTI lines pending flag */
|
||||
void exti_flag_clear(exti_line_enum linex);
|
||||
/* get EXTI lines flag when the interrupt flag is set */
|
||||
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
|
||||
/* clear EXTI lines pending flag */
|
||||
void exti_interrupt_flag_clear(exti_line_enum linex);
|
||||
|
||||
#endif /* GD32E23X_EXTI_H */
|
||||
@@ -0,0 +1,271 @@
|
||||
/*!
|
||||
\file gd32e23x_fmc.h
|
||||
\brief definitions for the FMC
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_FMC_H
|
||||
#define GD32E23X_FMC_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* FMC and option byte definition */
|
||||
#define FMC FMC_BASE /*!< FMC register base address */
|
||||
#define OB OB_BASE /*!< option byte base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */
|
||||
#define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */
|
||||
#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */
|
||||
#define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */
|
||||
#define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */
|
||||
#define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */
|
||||
#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */
|
||||
#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC write protection register */
|
||||
#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */
|
||||
|
||||
#define OB_SPC_USER REG32((OB) + 0x00U) /*!< option byte security protection value and user value */
|
||||
#define OB_DATA REG32((OB) + 0x04U) /*!< option byte data value*/
|
||||
#define OB_WP REG32((OB) + 0x08U) /*!< option byte write protection */
|
||||
|
||||
/* bits definitions */
|
||||
/* FMC_WS */
|
||||
#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */
|
||||
#define FMC_WS_PFEN BIT(4) /*!< pre-fetch enable */
|
||||
#define FMC_WS_PGW BIT(15) /*!< program width to flash memory */
|
||||
|
||||
/* FMC_KEY */
|
||||
#define FMC_KEY_KEY BITS(0,31) /*!< FMC main flash unlock key bits */
|
||||
|
||||
/* FMC_OBKEY */
|
||||
#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */
|
||||
|
||||
/* FMC_STAT */
|
||||
#define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */
|
||||
#define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */
|
||||
#define FMC_STAT_PGAERR BIT(3) /*!< program alignment error flag bit */
|
||||
#define FMC_STAT_WPERR BIT(4) /*!< flash write protection error flag bit */
|
||||
#define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */
|
||||
|
||||
/* FMC_CTL */
|
||||
#define FMC_CTL_PG BIT(0) /*!< main flash program command bit */
|
||||
#define FMC_CTL_PER BIT(1) /*!< main flash page erase bit */
|
||||
#define FMC_CTL_MER BIT(2) /*!< main flash mass erase bit */
|
||||
#define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */
|
||||
#define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */
|
||||
#define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */
|
||||
#define FMC_CTL_LK BIT(7) /*!< flash lock bit */
|
||||
#define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */
|
||||
#define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */
|
||||
#define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
|
||||
#define FMC_CTL_OBRLD BIT(13) /*!< option bytes reload bit */
|
||||
|
||||
/* FMC_ADDR */
|
||||
#define FMC_ADDR_ADDR BITS(0,31) /*!< flash command address bits */
|
||||
|
||||
/* FMC_OBSTAT */
|
||||
#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit */
|
||||
#define FMC_OBSTAT_PLEVEL_BIT0 BIT(1) /*!< protection level bit 0 */
|
||||
#define FMC_OBSTAT_PLEVEL_BIT1 BIT(2) /*!< protection level bit 1 */
|
||||
#define FMC_OBSTAT_USER BITS(8,15) /*!< option bytes user bits */
|
||||
#define FMC_OBSTAT_DATA BITS(16,31) /*!< option byte data bits */
|
||||
|
||||
/* FMC_WP */
|
||||
#define FMC_WP_WP BITS(0,15) /*!< store WP[15:0] of option byte block after system reset */
|
||||
|
||||
/* FMC_PID */
|
||||
#define FMC_PID_PID BITS(0,31) /*!< product ID bits */
|
||||
|
||||
/* constants definitions */
|
||||
/* fmc state */
|
||||
typedef enum
|
||||
{
|
||||
FMC_READY, /*!< the operation has been completed */
|
||||
FMC_BUSY, /*!< the operation is in progress */
|
||||
FMC_PGERR, /*!< program error */
|
||||
FMC_PGAERR, /*!< program alignment error */
|
||||
FMC_WPERR, /*!< erase/program protection error */
|
||||
FMC_TOERR, /*!< timeout error */
|
||||
FMC_OB_HSPC /*!< option byte security protection code high */
|
||||
}fmc_state_enum;
|
||||
|
||||
/* unlock key */
|
||||
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
|
||||
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
|
||||
|
||||
/* wait state counter value */
|
||||
#define WS_WSCNT_0 ((uint8_t)0x00U) /*!< 0 wait state added */
|
||||
#define WS_WSCNT_1 ((uint8_t)0x01U) /*!< 1 wait state added */
|
||||
#define WS_WSCNT_2 ((uint8_t)0x02U) /*!< 2 wait state added */
|
||||
|
||||
/* read protect configure */
|
||||
#define FMC_NSPC ((uint16_t)0x5AA5U) /*!< no security protection */
|
||||
#define FMC_LSPC ((uint16_t)0x44BBU) /*!< low security protection, any value except 0xA5 or 0xCC */
|
||||
#define FMC_HSPC ((uint16_t)0x33CCU) /*!< high security protection */
|
||||
|
||||
#define LOW_16BITS_MASK ((uint32_t)0x0000FFFFU) /*!< low 16 bits mask */
|
||||
#define HIGH_16BITS_MASK ((uint32_t)0xFFFF0000U) /*!< high 16 bits mask */
|
||||
|
||||
/* option byte address */
|
||||
#define OB_SPC_USER_ADDRESS ((uint32_t)0x1FFFF800U) /*!< address of option byte security protection and user */
|
||||
#define OB_DATA_ADDRESS ((uint32_t)0x1FFFF804U) /*!< address of option byte data */
|
||||
#define OB_WP_ADDRESS ((uint32_t)0x1FFFF808U) /*!< address of option byte write protection */
|
||||
|
||||
/* option byte write protection */
|
||||
#define OB_LWP ((uint32_t)0x000000FFU) /*!< write protection low bits */
|
||||
#define OB_HWP ((uint32_t)0x0000FF00U) /*!< write protection high bits */
|
||||
|
||||
/* option byte software/hardware free watchdog timer */
|
||||
#define OB_FWDGT_HW ((uint8_t)(~BIT(0))) /*!< hardware free watchdog timer */
|
||||
#define OB_FWDGT_SW ((uint8_t)BIT(0)) /*!< software free watchdog timer */
|
||||
|
||||
/* option byte reset or not entering deep sleep mode */
|
||||
#define OB_DEEPSLEEP_RST ((uint8_t)(~BIT(1))) /*!< generate a reset instead of entering deepsleep mode */
|
||||
#define OB_DEEPSLEEP_NRST ((uint8_t)BIT(1)) /*!< no reset when entering deepsleep mode */
|
||||
|
||||
/* option byte reset or not entering standby mode */
|
||||
#define OB_STDBY_RST ((uint8_t)(~BIT(2))) /*!< generate a reset instead of entering standby mode */
|
||||
#define OB_STDBY_NRST ((uint8_t)BIT(2)) /*!< no reset when entering deepsleep mode */
|
||||
|
||||
/* option byte OB_BOOT1_n set */
|
||||
#define OB_BOOT1_SET_1 ((uint8_t)(~BIT(4))) /*!< BOOT1 bit is 1 */
|
||||
#define OB_BOOT1_SET_0 ((uint8_t)BIT(4)) /*!< BOOT1 bit is 0 */
|
||||
|
||||
/* option byte VDDA monitor enable/disable */
|
||||
#define OB_VDDA_DISABLE ((uint8_t)(~BIT(5))) /*!< disable VDDA monitor */
|
||||
#define OB_VDDA_ENABLE ((uint8_t)BIT(5)) /*!< enable VDDA monitor */
|
||||
|
||||
/* option byte SRAM parity enable/disable */
|
||||
#define OB_SRAM_PARITY_ENABLE ((uint8_t)(~BIT(6))) /*!< enable SRAM parity check */
|
||||
#define OB_SRAM_PARITY_DISABLE ((uint8_t)BIT(6)) /*!< disable SRAM parity check */
|
||||
|
||||
/* option byte security protection level in FMC_OBSTAT register */
|
||||
#define OB_OBSTAT_PLEVEL_NO ((uint8_t)0x00U) /*!< no security protection */
|
||||
#define OB_OBSTAT_PLEVEL_LOW ((uint8_t)0x02U) /*!< low security protection */
|
||||
#define OB_OBSTAT_PLEVEL_HIGH ((uint8_t)0x06U) /*!< high security protection */
|
||||
|
||||
/* option byte user mask */
|
||||
#define OB_USER_MASK ((uint8_t)0x88U) /*!< OB_USER reserved bit mask */
|
||||
|
||||
/* option byte data address */
|
||||
#define OB_DATA_ADDR0 ((uint32_t)0x1FFFF804U) /*!< option byte data address 0 */
|
||||
#define OB_DATA_ADDR1 ((uint32_t)0x1FFFF806U) /*!< option byte data address 1 */
|
||||
|
||||
/* FMC flags */
|
||||
#define FMC_FLAG_BUSY FMC_STAT_BUSY /*!< FMC busy flag */
|
||||
#define FMC_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */
|
||||
#define FMC_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error flag */
|
||||
#define FMC_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */
|
||||
#define FMC_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */
|
||||
|
||||
/* FMC interrupt flags */
|
||||
#define FMC_INT_FLAG_PGERR FMC_STAT_PGERR /*!< FMC programming error flag */
|
||||
#define FMC_INT_FLAG_PGAERR FMC_STAT_PGAERR /*!< FMC program alignment error flag */
|
||||
#define FMC_INT_FLAG_WPERR FMC_STAT_WPERR /*!< FMC write protection error flag */
|
||||
#define FMC_INT_FLAG_END FMC_STAT_ENDF /*!< FMC end of programming flag */
|
||||
|
||||
/* FMC interrupt enable */
|
||||
#define FMC_INTEN_END FMC_CTL_ENDIE /*!< enable FMC end of operation interrupt */
|
||||
#define FMC_INTEN_ERR FMC_CTL_ERRIE /*!< enable FMC error interrupt */
|
||||
|
||||
/* FMC time out */
|
||||
#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< count to judge of FMC timeout */
|
||||
|
||||
/* function declarations */
|
||||
/* FMC main memory programming functions */
|
||||
/* unlock the main FMC operation */
|
||||
void fmc_unlock(void);
|
||||
/* lock the main FMC operation */
|
||||
void fmc_lock(void);
|
||||
/* set the wait state counter value */
|
||||
void fmc_wscnt_set(uint8_t wscnt);
|
||||
|
||||
/* pre-fetch enable */
|
||||
void fmc_prefetch_enable(void);
|
||||
/* pre-fetch disable */
|
||||
void fmc_prefetch_disable(void);
|
||||
/* FMC erase page */
|
||||
fmc_state_enum fmc_page_erase(uint32_t page_address);
|
||||
/* FMC erase whole chip */
|
||||
fmc_state_enum fmc_mass_erase(void);
|
||||
/* FMC program a double word at the corresponding address */
|
||||
fmc_state_enum fmc_doubleword_program(uint32_t address, uint64_t data);
|
||||
/* FMC program a word at the corresponding address */
|
||||
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
|
||||
|
||||
/* FMC option bytes programming functions */
|
||||
/* unlock the option byte operation */
|
||||
void ob_unlock(void);
|
||||
/* lock the option byte operation */
|
||||
void ob_lock(void);
|
||||
/* reload the option byte and generate a system reset */
|
||||
void ob_reset(void);
|
||||
/* get option byte value */
|
||||
uint32_t option_byte_value_get(uint32_t addr);
|
||||
/* erase option byte */
|
||||
fmc_state_enum ob_erase(void);
|
||||
/* enable option byte write protection (OB_WP) */
|
||||
fmc_state_enum ob_write_protection_enable(uint16_t ob_wp);
|
||||
/* configure read out protect */
|
||||
fmc_state_enum ob_security_protection_config(uint16_t ob_spc);
|
||||
/* write the FMC option byte user */
|
||||
fmc_state_enum ob_user_write(uint8_t ob_user);
|
||||
/* write the FMC option byte data */
|
||||
fmc_state_enum ob_data_program(uint16_t data);
|
||||
/* get the FMC option byte OB_USER */
|
||||
uint8_t ob_user_get(void);
|
||||
/* get the FMC option byte OB_DATA */
|
||||
uint16_t ob_data_get(void);
|
||||
/* get the FMC option byte write protection */
|
||||
uint16_t ob_write_protection_get(void);
|
||||
/* get the value of FMC option byte security protection level (PLEVEL) in FMC_OBSTAT register */
|
||||
uint32_t ob_obstat_plevel_get(void);
|
||||
|
||||
/* FMC interrupts and flags management functions */
|
||||
/* enable FMC interrupt */
|
||||
void fmc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable FMC interrupt */
|
||||
void fmc_interrupt_disable(uint32_t interrupt);
|
||||
/* get flag set or reset */
|
||||
FlagStatus fmc_flag_get(uint32_t flag);
|
||||
/* clear the FMC pending flag */
|
||||
void fmc_flag_clear(uint32_t flag);
|
||||
/* get intrrupt flag set or reset */
|
||||
FlagStatus fmc_interrupt_flag_get(uint32_t int_flag);
|
||||
/* clear the FMC interrupt pending flag by writing 1 */
|
||||
void fmc_interrupt_flag_clear(uint32_t int_flag);
|
||||
/* return the FMC state */
|
||||
fmc_state_enum fmc_state_get(void);
|
||||
/* check FMC ready or not */
|
||||
fmc_state_enum fmc_ready_wait(uint32_t timeout);
|
||||
|
||||
#endif /* GD32E23X_FMC_H */
|
||||
@@ -0,0 +1,125 @@
|
||||
/*!
|
||||
\file gd32e23x_fwdgt.h
|
||||
\brief definitions for the FWDGT
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_FWDGT_H
|
||||
#define GD32E23X_FWDGT_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* FWDGT definitions */
|
||||
#define FWDGT FWDGT_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define FWDGT_CTL REG32((FWDGT) + 0x00000000U) /*!< FWDGT control register */
|
||||
#define FWDGT_PSC REG32((FWDGT) + 0x00000004U) /*!< FWDGT prescaler register */
|
||||
#define FWDGT_RLD REG32((FWDGT) + 0x00000008U) /*!< FWDGT reload register */
|
||||
#define FWDGT_STAT REG32((FWDGT) + 0x0000000CU) /*!< FWDGT status register */
|
||||
#define FWDGT_WND REG32((FWDGT) + 0x00000010U) /*!< FWDGT window register */
|
||||
|
||||
/* bits definitions */
|
||||
/* FWDGT_CTL */
|
||||
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
|
||||
|
||||
/* FWDGT_PSC */
|
||||
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
|
||||
|
||||
/* FWDGT_RLD */
|
||||
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
|
||||
|
||||
/* FWDGT_STAT */
|
||||
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
|
||||
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
|
||||
#define FWDGT_STAT_WUD BIT(2) /*!< FWDGT counter window value update */
|
||||
|
||||
/* FWDGT_WND */
|
||||
#define FWDGT_WND_WND BITS(0,11) /*!< FWDGT counter window value */
|
||||
|
||||
/* constants definitions */
|
||||
/* FWDGT_PSC register value */
|
||||
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0U))
|
||||
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
|
||||
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
|
||||
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
|
||||
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
|
||||
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
|
||||
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
|
||||
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
|
||||
|
||||
/* control value */
|
||||
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x00005555U) /*!< FWDGT_CTL bits write access enable value */
|
||||
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x00000000U) /*!< FWDGT_CTL bits write access disable value */
|
||||
#define FWDGT_KEY_RELOAD ((uint16_t)0x0000AAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
|
||||
#define FWDGT_KEY_ENABLE ((uint16_t)0x0000CCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
|
||||
|
||||
/* FWDGT timeout value */
|
||||
#define FWDGT_WND_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_WND register write operation state flag timeout */
|
||||
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
|
||||
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
|
||||
|
||||
/* FWDGT flag definitions */
|
||||
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< a write operation to FWDGT_PSC register is on going */
|
||||
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< a write operation to FWDGT_RLD register is on going */
|
||||
#define FWDGT_FLAG_WUD FWDGT_STAT_WUD /*!< a write operation to FWDGT_WND register is on going */
|
||||
|
||||
/* write value to FWDGT_RLD_RLD bit field */
|
||||
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
/* write value to FWDGT_WND_WND bit field */
|
||||
#define WND_WND(regval) (BITS(0,11) & ((uint32_t)(regval) << 0U))
|
||||
|
||||
/* function declarations */
|
||||
/* enable write access to FWDGT_PSC and FWDGT_RLD and FWDGT_WND */
|
||||
void fwdgt_write_enable(void);
|
||||
/* disable write access to FWDGT_PSC,FWDGT_RLD and FWDGT_WND */
|
||||
void fwdgt_write_disable(void);
|
||||
/* start the free watchdog timer counter */
|
||||
void fwdgt_enable(void);
|
||||
|
||||
/* configure the free watchdog timer counter prescaler value */
|
||||
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value);
|
||||
/* configure the free watchdog timer counter reload value */
|
||||
ErrStatus fwdgt_reload_value_config(uint16_t reload_value);
|
||||
/* configure the free watchdog timer counter window value */
|
||||
ErrStatus fwdgt_window_value_config(uint16_t window_value);
|
||||
/* reload the counter of FWDGT */
|
||||
void fwdgt_counter_reload(void);
|
||||
/* configure counter reload value, and prescaler divider value */
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
|
||||
|
||||
/* get flag state of FWDGT */
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag);
|
||||
|
||||
#endif /* GD32E23X_FWDGT_H */
|
||||
@@ -0,0 +1,388 @@
|
||||
/*!
|
||||
\file gd32e23x_gpio.h
|
||||
\brief definitions for the GPIO
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2019, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_GPIO_H
|
||||
#define GD32E23X_GPIO_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* GPIOx(x=A,B,C,F) definitions */
|
||||
#define GPIOA (GPIO_BASE + 0x00000000U)
|
||||
#define GPIOB (GPIO_BASE + 0x00000400U)
|
||||
#define GPIOC (GPIO_BASE + 0x00000800U)
|
||||
#define GPIOF (GPIO_BASE + 0x00001400U)
|
||||
|
||||
/* registers definitions */
|
||||
#define GPIO_CTL(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register */
|
||||
#define GPIO_OMODE(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port output mode register */
|
||||
#define GPIO_OSPD(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port output speed register */
|
||||
#define GPIO_PUD(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port pull-up/pull-down register */
|
||||
#define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port input status register */
|
||||
#define GPIO_OCTL(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO port output control register */
|
||||
#define GPIO_BOP(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port bit operation register */
|
||||
#define GPIO_LOCK(gpiox) REG32((gpiox) + 0x1CU) /*!< GPIO port configuration lock register */
|
||||
#define GPIO_AFSEL0(gpiox) REG32((gpiox) + 0x20U) /*!< GPIO alternate function selected register 0 */
|
||||
#define GPIO_AFSEL1(gpiox) REG32((gpiox) + 0x24U) /*!< GPIO alternate function selected register 1 */
|
||||
#define GPIO_BC(gpiox) REG32((gpiox) + 0x28U) /*!< GPIO bit clear register */
|
||||
#define GPIO_TG(gpiox) REG32((gpiox) + 0x2CU) /*!< GPIO port bit toggle register */
|
||||
|
||||
/* bits definitions */
|
||||
/* GPIO_CTL */
|
||||
#define GPIO_CTL_CTL0 BITS(0,1) /*!< pin 0 configuration bits */
|
||||
#define GPIO_CTL_CTL1 BITS(2,3) /*!< pin 1 configuration bits */
|
||||
#define GPIO_CTL_CTL2 BITS(4,5) /*!< pin 2 configuration bits */
|
||||
#define GPIO_CTL_CTL3 BITS(6,7) /*!< pin 3 configuration bits */
|
||||
#define GPIO_CTL_CTL4 BITS(8,9) /*!< pin 4 configuration bits */
|
||||
#define GPIO_CTL_CTL5 BITS(10,11) /*!< pin 5 configuration bits */
|
||||
#define GPIO_CTL_CTL6 BITS(12,13) /*!< pin 6 configuration bits */
|
||||
#define GPIO_CTL_CTL7 BITS(14,15) /*!< pin 7 configuration bits */
|
||||
#define GPIO_CTL_CTL8 BITS(16,17) /*!< pin 8 configuration bits */
|
||||
#define GPIO_CTL_CTL9 BITS(18,19) /*!< pin 9 configuration bits */
|
||||
#define GPIO_CTL_CTL10 BITS(20,21) /*!< pin 10 configuration bits */
|
||||
#define GPIO_CTL_CTL11 BITS(22,23) /*!< pin 11 configuration bits */
|
||||
#define GPIO_CTL_CTL12 BITS(24,25) /*!< pin 12 configuration bits */
|
||||
#define GPIO_CTL_CTL13 BITS(26,27) /*!< pin 13 configuration bits */
|
||||
#define GPIO_CTL_CTL14 BITS(28,29) /*!< pin 14 configuration bits */
|
||||
#define GPIO_CTL_CTL15 BITS(30,31) /*!< pin 15 configuration bits */
|
||||
|
||||
/* GPIO_OMODE */
|
||||
#define GPIO_OMODE_OM0 BIT(0) /*!< pin 0 output mode bit */
|
||||
#define GPIO_OMODE_OM1 BIT(1) /*!< pin 1 output mode bit */
|
||||
#define GPIO_OMODE_OM2 BIT(2) /*!< pin 2 output mode bit */
|
||||
#define GPIO_OMODE_OM3 BIT(3) /*!< pin 3 output mode bit */
|
||||
#define GPIO_OMODE_OM4 BIT(4) /*!< pin 4 output mode bit */
|
||||
#define GPIO_OMODE_OM5 BIT(5) /*!< pin 5 output mode bit */
|
||||
#define GPIO_OMODE_OM6 BIT(6) /*!< pin 6 output mode bit */
|
||||
#define GPIO_OMODE_OM7 BIT(7) /*!< pin 7 output mode bit */
|
||||
#define GPIO_OMODE_OM8 BIT(8) /*!< pin 8 output mode bit */
|
||||
#define GPIO_OMODE_OM9 BIT(9) /*!< pin 9 output mode bit */
|
||||
#define GPIO_OMODE_OM10 BIT(10) /*!< pin 10 output mode bit */
|
||||
#define GPIO_OMODE_OM11 BIT(11) /*!< pin 11 output mode bit */
|
||||
#define GPIO_OMODE_OM12 BIT(12) /*!< pin 12 output mode bit */
|
||||
#define GPIO_OMODE_OM13 BIT(13) /*!< pin 13 output mode bit */
|
||||
#define GPIO_OMODE_OM14 BIT(14) /*!< pin 14 output mode bit */
|
||||
#define GPIO_OMODE_OM15 BIT(15) /*!< pin 15 output mode bit */
|
||||
|
||||
/* GPIO_OSPD */
|
||||
#define GPIO_OSPD_OSPD0 BITS(0,1) /*!< pin 0 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD1 BITS(2,3) /*!< pin 1 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD2 BITS(4,5) /*!< pin 2 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD3 BITS(6,7) /*!< pin 3 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD4 BITS(8,9) /*!< pin 4 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD5 BITS(10,11) /*!< pin 5 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD6 BITS(12,13) /*!< pin 6 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD7 BITS(14,15) /*!< pin 7 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD8 BITS(16,17) /*!< pin 8 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD9 BITS(18,19) /*!< pin 9 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD10 BITS(20,21) /*!< pin 10 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD11 BITS(22,23) /*!< pin 11 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD12 BITS(24,25) /*!< pin 12 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD13 BITS(26,27) /*!< pin 13 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD14 BITS(28,29) /*!< pin 14 output max speed bits */
|
||||
#define GPIO_OSPD_OSPD15 BITS(30,31) /*!< pin 15 output max speed bits */
|
||||
|
||||
/* GPIO_PUD */
|
||||
#define GPIO_PUD_PUD0 BITS(0,1) /*!< pin 0 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD1 BITS(2,3) /*!< pin 1 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD2 BITS(4,5) /*!< pin 2 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD3 BITS(6,7) /*!< pin 3 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD4 BITS(8,9) /*!< pin 4 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD5 BITS(10,11) /*!< pin 5 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD6 BITS(12,13) /*!< pin 6 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD7 BITS(14,15) /*!< pin 7 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD8 BITS(16,17) /*!< pin 8 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD9 BITS(18,19) /*!< pin 9 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD10 BITS(20,21) /*!< pin 10 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD11 BITS(22,23) /*!< pin 11 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD12 BITS(24,25) /*!< pin 12 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD13 BITS(26,27) /*!< pin 13 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD14 BITS(28,29) /*!< pin 14 pull-up or pull-down bits */
|
||||
#define GPIO_PUD_PUD15 BITS(30,31) /*!< pin 15 pull-up or pull-down bits */
|
||||
|
||||
/* GPIO_ISTAT */
|
||||
#define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */
|
||||
#define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */
|
||||
#define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */
|
||||
#define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */
|
||||
#define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */
|
||||
#define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */
|
||||
#define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */
|
||||
#define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */
|
||||
#define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */
|
||||
#define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */
|
||||
#define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */
|
||||
#define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */
|
||||
#define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */
|
||||
#define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */
|
||||
#define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */
|
||||
#define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */
|
||||
|
||||
/* GPIO_OCTL */
|
||||
#define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */
|
||||
#define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */
|
||||
#define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */
|
||||
#define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */
|
||||
#define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */
|
||||
#define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */
|
||||
#define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */
|
||||
#define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */
|
||||
#define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */
|
||||
#define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */
|
||||
#define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */
|
||||
#define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */
|
||||
#define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */
|
||||
#define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */
|
||||
#define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */
|
||||
#define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */
|
||||
|
||||
/* GPIO_BOP */
|
||||
#define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */
|
||||
#define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */
|
||||
#define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */
|
||||
#define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */
|
||||
#define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */
|
||||
#define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */
|
||||
#define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */
|
||||
#define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */
|
||||
#define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */
|
||||
#define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */
|
||||
#define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */
|
||||
#define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */
|
||||
#define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */
|
||||
#define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */
|
||||
#define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */
|
||||
#define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */
|
||||
#define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */
|
||||
#define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */
|
||||
#define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */
|
||||
#define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */
|
||||
#define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */
|
||||
#define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */
|
||||
#define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */
|
||||
#define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */
|
||||
#define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */
|
||||
#define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */
|
||||
#define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */
|
||||
#define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */
|
||||
#define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */
|
||||
#define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */
|
||||
#define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */
|
||||
#define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */
|
||||
|
||||
/* GPIO_LOCK */
|
||||
#define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */
|
||||
#define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */
|
||||
#define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */
|
||||
#define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */
|
||||
#define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */
|
||||
#define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */
|
||||
#define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */
|
||||
#define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */
|
||||
#define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */
|
||||
#define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */
|
||||
#define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */
|
||||
#define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */
|
||||
#define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */
|
||||
#define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */
|
||||
#define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */
|
||||
#define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */
|
||||
#define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */
|
||||
|
||||
/* GPIO_AFSEL0 */
|
||||
#define GPIO_AFSEL0_SEL0 BITS(0,3) /*!< pin 0 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL1 BITS(4,7) /*!< pin 1 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL2 BITS(8,11) /*!< pin 2 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL3 BITS(12,15) /*!< pin 3 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL4 BITS(16,19) /*!< pin 4 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL5 BITS(20,23) /*!< pin 5 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL6 BITS(24,27) /*!< pin 6 alternate function selected */
|
||||
#define GPIO_AFSEL0_SEL7 BITS(28,31) /*!< pin 7 alternate function selected */
|
||||
|
||||
/* GPIO_AFSEL1 */
|
||||
#define GPIO_AFSEL1_SEL8 BITS(0,3) /*!< pin 8 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL9 BITS(4,7) /*!< pin 9 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL10 BITS(8,11) /*!< pin 10 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL11 BITS(12,15) /*!< pin 11 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL12 BITS(16,19) /*!< pin 12 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL13 BITS(20,23) /*!< pin 13 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL14 BITS(24,27) /*!< pin 14 alternate function selected */
|
||||
#define GPIO_AFSEL1_SEL15 BITS(28,31) /*!< pin 15 alternate function selected */
|
||||
|
||||
/* GPIO_BC */
|
||||
#define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */
|
||||
#define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */
|
||||
#define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */
|
||||
#define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */
|
||||
#define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */
|
||||
#define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */
|
||||
#define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */
|
||||
#define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */
|
||||
#define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */
|
||||
#define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */
|
||||
#define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */
|
||||
#define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */
|
||||
#define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */
|
||||
#define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */
|
||||
#define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */
|
||||
#define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */
|
||||
|
||||
/* GPIO_TG */
|
||||
#define GPIO_TG_TG0 BIT(0) /*!< pin 0 toggle bit */
|
||||
#define GPIO_TG_TG1 BIT(1) /*!< pin 1 toggle bit */
|
||||
#define GPIO_TG_TG2 BIT(2) /*!< pin 2 toggle bit */
|
||||
#define GPIO_TG_TG3 BIT(3) /*!< pin 3 toggle bit */
|
||||
#define GPIO_TG_TG4 BIT(4) /*!< pin 4 toggle bit */
|
||||
#define GPIO_TG_TG5 BIT(5) /*!< pin 5 toggle bit */
|
||||
#define GPIO_TG_TG6 BIT(6) /*!< pin 6 toggle bit */
|
||||
#define GPIO_TG_TG7 BIT(7) /*!< pin 7 toggle bit */
|
||||
#define GPIO_TG_TG8 BIT(8) /*!< pin 8 toggle bit */
|
||||
#define GPIO_TG_TG9 BIT(9) /*!< pin 9 toggle bit */
|
||||
#define GPIO_TG_TG10 BIT(10) /*!< pin 10 toggle bit */
|
||||
#define GPIO_TG_TG11 BIT(11) /*!< pin 11 toggle bit */
|
||||
#define GPIO_TG_TG12 BIT(12) /*!< pin 12 toggle bit */
|
||||
#define GPIO_TG_TG13 BIT(13) /*!< pin 13 toggle bit */
|
||||
#define GPIO_TG_TG14 BIT(14) /*!< pin 14 toggle bit */
|
||||
#define GPIO_TG_TG15 BIT(15) /*!< pin 15 toggle bit */
|
||||
|
||||
/* constants definitions */
|
||||
typedef FlagStatus bit_status;
|
||||
|
||||
/* output mode definitions */
|
||||
#define CTL_CLTR(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_MODE_INPUT CTL_CLTR(0) /*!< input mode */
|
||||
#define GPIO_MODE_OUTPUT CTL_CLTR(1) /*!< output mode */
|
||||
#define GPIO_MODE_AF CTL_CLTR(2) /*!< alternate function mode */
|
||||
#define GPIO_MODE_ANALOG CTL_CLTR(3) /*!< analog mode */
|
||||
|
||||
/* pull-up/pull-down definitions */
|
||||
#define PUD_PUPD(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_PUPD_NONE PUD_PUPD(0) /*!< floating mode, no pull-up and pull-down resistors */
|
||||
#define GPIO_PUPD_PULLUP PUD_PUPD(1) /*!< with pull-up resistor */
|
||||
#define GPIO_PUPD_PULLDOWN PUD_PUPD(2) /*!< with pull-down resistor */
|
||||
|
||||
/* GPIO pin definitions */
|
||||
#define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */
|
||||
#define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */
|
||||
#define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */
|
||||
#define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */
|
||||
#define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */
|
||||
#define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */
|
||||
#define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */
|
||||
#define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */
|
||||
#define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */
|
||||
#define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */
|
||||
#define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */
|
||||
#define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */
|
||||
#define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */
|
||||
#define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */
|
||||
#define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */
|
||||
#define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */
|
||||
#define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */
|
||||
|
||||
/* GPIO mode configuration values */
|
||||
#define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (2U * (n))))
|
||||
#define GPIO_MODE_MASK(n) (0x3U << (2U * (n)))
|
||||
|
||||
/* GPIO pull-up/pull-down values */
|
||||
#define GPIO_PUPD_SET(n, pupd) ((uint32_t)((uint32_t)(pupd) << (2U * (n))))
|
||||
#define GPIO_PUPD_MASK(n) (0x3U << (2U * (n)))
|
||||
|
||||
/* GPIO output speed values */
|
||||
#define GPIO_OSPEED_SET(n, speed) ((uint32_t)((uint32_t)(speed) << (2U * (n))))
|
||||
#define GPIO_OSPEED_MASK(n) (0x3U << (2U * (n)))
|
||||
|
||||
/* GPIO output type */
|
||||
#define GPIO_OTYPE_PP ((uint8_t)(0x00U)) /*!< push pull mode */
|
||||
#define GPIO_OTYPE_OD ((uint8_t)(0x01U)) /*!< open drain mode */
|
||||
|
||||
/* GPIO output max speed value */
|
||||
#define OSPD_OSPD0(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_OSPEED_2MHZ OSPD_OSPD0(0) /*!< output max speed 2MHz */
|
||||
#define GPIO_OSPEED_10MHZ OSPD_OSPD0(1) /*!< output max speed 10MHz */
|
||||
#define GPIO_OSPEED_50MHZ OSPD_OSPD0(3) /*!< output max speed 50MHz */
|
||||
|
||||
/* GPIO alternate function values */
|
||||
#define GPIO_AFR_SET(n, af) ((uint32_t)((uint32_t)(af) << (4U * (n))))
|
||||
#define GPIO_AFR_MASK(n) (0xFU << (4U * (n)))
|
||||
|
||||
/* GPIO alternate function */
|
||||
#define AF(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
|
||||
#define GPIO_AF_0 AF(0) /*!< alternate function 0 selected */
|
||||
#define GPIO_AF_1 AF(1) /*!< alternate function 1 selected */
|
||||
#define GPIO_AF_2 AF(2) /*!< alternate function 2 selected */
|
||||
#define GPIO_AF_3 AF(3) /*!< alternate function 3 selected */
|
||||
#define GPIO_AF_4 AF(4) /*!< alternate function 4 selected (port A,B only) */
|
||||
#define GPIO_AF_5 AF(5) /*!< alternate function 5 selected (port A,B only) */
|
||||
#define GPIO_AF_6 AF(6) /*!< alternate function 6 selected (port A,B only) */
|
||||
#define GPIO_AF_7 AF(7) /*!< alternate function 7 selected (port A,B only) */
|
||||
|
||||
/* function declarations */
|
||||
/* reset GPIO port */
|
||||
void gpio_deinit(uint32_t gpio_periph);
|
||||
/* set GPIO mode */
|
||||
void gpio_mode_set(uint32_t gpio_periph, uint32_t mode, uint32_t pull_up_down, uint32_t pin);
|
||||
/* set GPIO output type and speed */
|
||||
void gpio_output_options_set(uint32_t gpio_periph, uint8_t otype, uint32_t speed, uint32_t pin);
|
||||
|
||||
/* set GPIO pin bit */
|
||||
void gpio_bit_set(uint32_t gpio_periph, uint32_t pin);
|
||||
/* reset GPIO pin bit */
|
||||
void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin);
|
||||
/* write data to the specified GPIO pin */
|
||||
void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value);
|
||||
/* write data to the specified GPIO port */
|
||||
void gpio_port_write(uint32_t gpio_periph, uint16_t data);
|
||||
|
||||
/* get GPIO pin input status */
|
||||
FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin);
|
||||
/* get GPIO port input status */
|
||||
uint16_t gpio_input_port_get(uint32_t gpio_periph);
|
||||
/* get GPIO pin output status */
|
||||
FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin);
|
||||
/* get GPIO port output status */
|
||||
uint16_t gpio_output_port_get(uint32_t gpio_periph);
|
||||
|
||||
/* set GPIO alternate function */
|
||||
void gpio_af_set(uint32_t gpio_periph,uint32_t alt_func_num, uint32_t pin);
|
||||
/* lock GPIO pin bit */
|
||||
void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin);
|
||||
|
||||
/* toggle GPIO pin status */
|
||||
void gpio_bit_toggle(uint32_t gpio_periph, uint32_t pin);
|
||||
/* toggle GPIO port status */
|
||||
void gpio_port_toggle(uint32_t gpio_periph);
|
||||
|
||||
#endif /* GD32E23X_GPIO_H */
|
||||
@@ -0,0 +1,382 @@
|
||||
/*!
|
||||
\file gd32e23x_i2c.h
|
||||
\brief definitions for the I2C
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_I2C_H
|
||||
#define GD32E23X_I2C_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* I2Cx(x=0,1) definitions */
|
||||
#define I2C0 I2C_BASE /*!< I2C0 base address */
|
||||
#define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */
|
||||
#define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */
|
||||
#define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0 */
|
||||
#define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1 */
|
||||
#define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */
|
||||
#define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */
|
||||
#define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */
|
||||
#define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */
|
||||
#define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */
|
||||
#define I2C_SAMCS(i2cx) REG32((i2cx) + 0x00000080U) /*!< I2C SAM control and status register */
|
||||
#define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x00000090U) /*!< I2C fast mode plus configure register */
|
||||
|
||||
/* bits definitions */
|
||||
/* I2Cx_CTL0 */
|
||||
#define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */
|
||||
#define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */
|
||||
#define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */
|
||||
#define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */
|
||||
#define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */
|
||||
#define I2C_CTL0_GCEN BIT(6) /*!< general call enable */
|
||||
#define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */
|
||||
#define I2C_CTL0_START BIT(8) /*!< start generation */
|
||||
#define I2C_CTL0_STOP BIT(9) /*!< stop generation */
|
||||
#define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */
|
||||
#define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */
|
||||
#define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */
|
||||
#define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */
|
||||
#define I2C_CTL0_SRESET BIT(15) /*!< software reset */
|
||||
|
||||
/* I2Cx_CTL1 */
|
||||
#define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */
|
||||
#define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */
|
||||
#define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */
|
||||
#define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */
|
||||
#define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */
|
||||
#define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */
|
||||
|
||||
/* I2Cx_SADDR0 */
|
||||
#define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */
|
||||
#define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */
|
||||
|
||||
/* I2Cx_SADDR1 */
|
||||
#define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */
|
||||
#define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */
|
||||
|
||||
/* I2Cx_DATA */
|
||||
#define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */
|
||||
|
||||
/* I2Cx_STAT0 */
|
||||
#define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */
|
||||
#define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */
|
||||
#define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */
|
||||
#define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */
|
||||
#define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */
|
||||
#define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */
|
||||
#define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */
|
||||
#define I2C_STAT0_BERR BIT(8) /*!< bus error */
|
||||
#define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */
|
||||
#define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */
|
||||
#define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */
|
||||
#define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */
|
||||
#define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */
|
||||
#define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */
|
||||
|
||||
/* I2Cx_STAT1 */
|
||||
#define I2C_STAT1_MASTER BIT(0) /*!< master/slave */
|
||||
#define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */
|
||||
#define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */
|
||||
#define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */
|
||||
#define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */
|
||||
#define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */
|
||||
#define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */
|
||||
#define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */
|
||||
|
||||
/* I2Cx_CKCFG */
|
||||
#define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */
|
||||
#define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */
|
||||
#define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */
|
||||
|
||||
/* I2Cx_RT */
|
||||
#define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */
|
||||
|
||||
/* I2Cx_SAMCS */
|
||||
#define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */
|
||||
#define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */
|
||||
#define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */
|
||||
#define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */
|
||||
#define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */
|
||||
#define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */
|
||||
#define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */
|
||||
#define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */
|
||||
#define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */
|
||||
#define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */
|
||||
#define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */
|
||||
#define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */
|
||||
|
||||
/* I2Cx_FMPCFG */
|
||||
#define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */
|
||||
|
||||
/* constants definitions */
|
||||
/* define the I2C bit position and its register index offset */
|
||||
#define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
|
||||
#define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
|
||||
#define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
|
||||
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
|
||||
#define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22)))
|
||||
#define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
|
||||
|
||||
/* register offset */
|
||||
#define I2C_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */
|
||||
#define I2C_STAT0_REG_OFFSET ((uint32_t)0x00000014U) /*!< STAT0 register offset */
|
||||
#define I2C_STAT1_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT1 register offset */
|
||||
#define I2C_SAMCS_REG_OFFSET ((uint32_t)0x00000080U) /*!< SAMCS register offset */
|
||||
|
||||
/* I2C flags */
|
||||
typedef enum {
|
||||
/* flags in STAT0 register */
|
||||
I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */
|
||||
I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */
|
||||
I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */
|
||||
I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */
|
||||
I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */
|
||||
I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not empty during receiving */
|
||||
I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */
|
||||
I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */
|
||||
I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */
|
||||
I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */
|
||||
I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */
|
||||
I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */
|
||||
I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */
|
||||
I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */
|
||||
/* flags in STAT1 register */
|
||||
I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */
|
||||
I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */
|
||||
I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */
|
||||
I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */
|
||||
I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */
|
||||
I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */
|
||||
I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */
|
||||
/* flags in SAMCS register */
|
||||
I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */
|
||||
I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */
|
||||
I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */
|
||||
I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */
|
||||
} i2c_flag_enum;
|
||||
|
||||
/* I2C interrupt flags */
|
||||
typedef enum {
|
||||
/* interrupt flags in CTL1 register */
|
||||
I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */
|
||||
I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes interrupt flag */
|
||||
I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */
|
||||
I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */
|
||||
I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */
|
||||
I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */
|
||||
I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */
|
||||
I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */
|
||||
I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */
|
||||
I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */
|
||||
I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */
|
||||
I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status interrupt flag */
|
||||
/* interrupt flags in SAMCS register */
|
||||
I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */
|
||||
I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */
|
||||
I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */
|
||||
I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */
|
||||
} i2c_interrupt_flag_enum;
|
||||
|
||||
/* I2C interrupt */
|
||||
typedef enum {
|
||||
/* interrupt in CTL1 register */
|
||||
I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt */
|
||||
I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt */
|
||||
I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt */
|
||||
/* interrupt in SAMCS register */
|
||||
I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt */
|
||||
I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt */
|
||||
I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt */
|
||||
I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U) /*!< rxframe rise interrupt */
|
||||
} i2c_interrupt_enum;
|
||||
|
||||
/* SMBus/I2C mode switch and SMBus type selection */
|
||||
#define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */
|
||||
#define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */
|
||||
|
||||
/* SMBus/I2C mode switch and SMBus type selection */
|
||||
#define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */
|
||||
#define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */
|
||||
|
||||
/* I2C transfer direction */
|
||||
#define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */
|
||||
#define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */
|
||||
|
||||
/* whether or not to send an ACK */
|
||||
#define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */
|
||||
#define I2C_ACK_ENABLE I2C_CTL0_ACKEN /*!< ACK will be sent */
|
||||
|
||||
/* I2C POAP position*/
|
||||
#define I2C_ACKPOS_CURRENT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */
|
||||
#define I2C_ACKPOS_NEXT I2C_CTL0_POAP /*!< ACKEN bit decides whether or not to send ACK for the next byte */
|
||||
|
||||
/* whether or not to stretch SCL low */
|
||||
#define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< enable SCL stretching */
|
||||
#define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< disable SCL stretching */
|
||||
|
||||
/* whether or not to response to a general call */
|
||||
#define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */
|
||||
#define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */
|
||||
|
||||
/* software reset I2C */
|
||||
#define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */
|
||||
#define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */
|
||||
|
||||
/* I2C DMA mode configure */
|
||||
/* DMA mode switch */
|
||||
#define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< disable DMA mode */
|
||||
#define I2C_DMA_ON I2C_CTL1_DMAON /*!< enable DMA mode */
|
||||
|
||||
/* flag indicating DMA last transfer */
|
||||
#define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */
|
||||
#define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */
|
||||
|
||||
/* I2C PEC configure */
|
||||
/* PEC enable */
|
||||
#define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */
|
||||
#define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */
|
||||
|
||||
/* PEC transfer */
|
||||
#define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */
|
||||
#define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC value */
|
||||
|
||||
/* I2C SMBus configure */
|
||||
/* issue or not alert through SMBA pin */
|
||||
#define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */
|
||||
#define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */
|
||||
|
||||
/* ARP protocol in SMBus switch */
|
||||
#define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< disable ARP */
|
||||
#define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< enable ARP */
|
||||
|
||||
/* transmit I2C data */
|
||||
#define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* receive I2C data */
|
||||
#define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7)
|
||||
|
||||
/* I2C duty cycle in fast mode or fast mode plus */
|
||||
#define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< T_low/T_high = 2 in fast mode or fast mode plus */
|
||||
#define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< T_low/T_high = 16/9 in fast mode or fast mode plus */
|
||||
|
||||
/* address mode for the I2C slave */
|
||||
#define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address format is 7 bits */
|
||||
#define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address format is 10 bits */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* reset I2C */
|
||||
void i2c_deinit(uint32_t i2c_periph);
|
||||
/* configure I2C clock */
|
||||
void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc);
|
||||
/* configure I2C address */
|
||||
void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr);
|
||||
|
||||
/* application function declarations */
|
||||
/* select SMBus type */
|
||||
void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type);
|
||||
/* whether or not to send an ACK */
|
||||
void i2c_ack_config(uint32_t i2c_periph, uint32_t ack);
|
||||
/* configure I2C POAP position */
|
||||
void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos);
|
||||
/* master sends slave address */
|
||||
void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection);
|
||||
/* enable dual-address mode */
|
||||
void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr);
|
||||
/* disable dual-address mode */
|
||||
void i2c_dualaddr_disable(uint32_t i2c_periph);
|
||||
/* enable I2C */
|
||||
void i2c_enable(uint32_t i2c_periph);
|
||||
/* disable I2C */
|
||||
void i2c_disable(uint32_t i2c_periph);
|
||||
/* generate a START condition on I2C bus */
|
||||
void i2c_start_on_bus(uint32_t i2c_periph);
|
||||
/* generate a STOP condition on I2C bus */
|
||||
void i2c_stop_on_bus(uint32_t i2c_periph);
|
||||
/* I2C transmit data function */
|
||||
void i2c_data_transmit(uint32_t i2c_periph, uint8_t data);
|
||||
/* I2C receive data function */
|
||||
uint8_t i2c_data_receive(uint32_t i2c_periph);
|
||||
/* configure I2C DMA mode */
|
||||
void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate);
|
||||
/* configure whether next DMA EOT is DMA last transfer or not */
|
||||
void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast);
|
||||
/* whether to stretch SCL low when data is not ready in slave mode */
|
||||
void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara);
|
||||
/* whether or not to response to a general call */
|
||||
void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara);
|
||||
/* configure software reset of I2C */
|
||||
void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset);
|
||||
/* configure I2C PEC calculation */
|
||||
void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate);
|
||||
/* configure whether to transfer PEC value */
|
||||
void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara);
|
||||
/* get packet error checking value */
|
||||
uint8_t i2c_pec_value_get(uint32_t i2c_periph);
|
||||
/* configure I2C alert through SMBA pin */
|
||||
void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara);
|
||||
/* configure I2C ARP protocol in SMBus */
|
||||
void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate);
|
||||
/* enable SAM_V interface */
|
||||
void i2c_sam_enable(uint32_t i2c_periph);
|
||||
/* disable SAM_V interface */
|
||||
void i2c_sam_disable(uint32_t i2c_periph);
|
||||
/* enable SAM_V interface timeout detect */
|
||||
void i2c_sam_timeout_enable(uint32_t i2c_periph);
|
||||
/* disable SAM_V interface timeout detect */
|
||||
void i2c_sam_timeout_disable(uint32_t i2c_periph);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get I2C flag status */
|
||||
FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||
/* clear I2C flag status */
|
||||
void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag);
|
||||
/* enable I2C interrupt */
|
||||
void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||
/* disable I2C interrupt */
|
||||
void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt);
|
||||
/* get I2C interrupt flag status */
|
||||
FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
||||
/* clear I2C interrupt flag status */
|
||||
void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag);
|
||||
|
||||
#endif /* GD32E23X_I2C_H */
|
||||
@@ -0,0 +1,59 @@
|
||||
/*!
|
||||
\file gd32e23x_libopt.h
|
||||
\brief library optional for gd32e23x
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2023, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_LIBOPT_H
|
||||
#define GD32E23X_LIBOPT_H
|
||||
|
||||
#include "gd32e23x_adc.h"
|
||||
#include "gd32e23x_crc.h"
|
||||
#include "gd32e23x_dbg.h"
|
||||
#include "gd32e23x_dma.h"
|
||||
#include "gd32e23x_exti.h"
|
||||
#include "gd32e23x_fmc.h"
|
||||
#include "gd32e23x_gpio.h"
|
||||
#include "gd32e23x_syscfg.h"
|
||||
#include "gd32e23x_i2c.h"
|
||||
#include "gd32e23x_fwdgt.h"
|
||||
#include "gd32e23x_pmu.h"
|
||||
#include "gd32e23x_rcu.h"
|
||||
#include "gd32e23x_rtc.h"
|
||||
#include "gd32e23x_spi.h"
|
||||
#include "gd32e23x_timer.h"
|
||||
#include "gd32e23x_usart.h"
|
||||
#include "gd32e23x_wwdgt.h"
|
||||
#include "gd32e23x_misc.h"
|
||||
#include "gd32e23x_cmp.h"
|
||||
|
||||
#endif /* GD32E23X_LIBOPT_H */
|
||||
@@ -0,0 +1,85 @@
|
||||
/*!
|
||||
\file gd32e23x_misc.h
|
||||
\brief definitions for the MISC
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_MISC_H
|
||||
#define GD32E23X_MISC_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* constants definitions */
|
||||
/* set the RAM and FLASH base address */
|
||||
#define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< RAM base address */
|
||||
#define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< Flash base address */
|
||||
|
||||
/* set the NVIC vector table offset mask */
|
||||
#define NVIC_VECTTAB_OFFSET_MASK ((uint32_t)0x1FFFFF80) /*!< NVIC vector table offset mask */
|
||||
|
||||
/* the register key mask, if you want to do the write operation, you should write 0x5FA to VECTKEY bits */
|
||||
#define NVIC_AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000) /*!< NVIC VECTKEY mask */
|
||||
|
||||
/* choose the method to enter or exit the lowpower mode */
|
||||
#define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< choose the the system whether enter low power mode by exiting from ISR */
|
||||
#define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< choose the the system enter the DEEPSLEEP mode or SLEEP mode */
|
||||
#define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< choose the interrupt source that can wake up the lowpower mode */
|
||||
|
||||
#define SCB_LPM_SLEEP_EXIT_ISR SCB_SCR_SLEEPONEXIT /*!< low power mode by exiting from ISR */
|
||||
#define SCB_LPM_DEEPSLEEP SCB_SCR_SLEEPDEEP /*!< DEEPSLEEP mode or SLEEP mode */
|
||||
#define SCB_LPM_WAKE_BY_ALL_INT SCB_SCR_SEVONPEND /*!< wakeup by all interrupt */
|
||||
|
||||
/* choose the systick clock source */
|
||||
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0xFFFFFFFBU) /*!< systick clock source is from HCLK/8 */
|
||||
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U) /*!< systick clock source is from HCLK */
|
||||
|
||||
/* function declarations */
|
||||
|
||||
/* enable NVIC request */
|
||||
void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_priority);
|
||||
/* disable NVIC request */
|
||||
void nvic_irq_disable(uint8_t nvic_irq);
|
||||
/* initiates a system reset request to reset the MCU */
|
||||
void nvic_system_reset(void);
|
||||
|
||||
/* set the NVIC vector table base address */
|
||||
void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
|
||||
|
||||
/* set the state of the low power mode */
|
||||
void system_lowpower_set(uint8_t lowpower_mode);
|
||||
/* reset the state of the low power mode */
|
||||
void system_lowpower_reset(uint8_t lowpower_mode);
|
||||
|
||||
/* set the systick clock source */
|
||||
void systick_clksource_set(uint32_t systick_clksource);
|
||||
|
||||
#endif /* GD32E23X_MISC_H */
|
||||
@@ -0,0 +1,149 @@
|
||||
/*!
|
||||
\file gd32e23x_pmu.h
|
||||
\brief definitions for the PMU
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_PMU_H
|
||||
#define GD32E23X_PMU_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* PMU definitions */
|
||||
#define PMU PMU_BASE /*!< PMU base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */
|
||||
#define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* PMU_CTL */
|
||||
#define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */
|
||||
#define PMU_CTL_STBMOD BIT(1) /*!< standby mode */
|
||||
#define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */
|
||||
#define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */
|
||||
#define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */
|
||||
#define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */
|
||||
#define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */
|
||||
#define PMU_CTL_LDOVS_0 BIT(14) /*!< LDO output voltage select */
|
||||
#define PMU_CTL_LDOVS_1 BIT(15) /*!< LDO output voltage select */
|
||||
#define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */
|
||||
|
||||
/* PMU_CS */
|
||||
#define PMU_CS_WUF BIT(0) /*!< wakeup flag */
|
||||
#define PMU_CS_STBF BIT(1) /*!< standby flag */
|
||||
#define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */
|
||||
#define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin enable */
|
||||
#ifdef GD32E230
|
||||
#define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin enable */
|
||||
#endif /* GD32E230 */
|
||||
#define PMU_CS_WUPEN5 BIT(13) /*!< wakeup pin enable */
|
||||
#define PMU_CS_WUPEN6 BIT(14) /*!< wakeup pin enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* PMU ldo definitions */
|
||||
#define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO operates normally when PMU enter deepsleep mode */
|
||||
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */
|
||||
|
||||
/* PMU low voltage detector threshold definitions */
|
||||
#define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5))
|
||||
#define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */
|
||||
#define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */
|
||||
#define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */
|
||||
#define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */
|
||||
#define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */
|
||||
#define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */
|
||||
#define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */
|
||||
#define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */
|
||||
|
||||
/* PMU LDO output voltage select definitions */
|
||||
#define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14))
|
||||
#define PMU_LDOVS_HIGH CTL_LDOVS(1) /*!< LDO output voltage high mode */
|
||||
#define PMU_LDOVS_LOW CTL_LDOVS(2) /*!< LDO output voltage low mode */
|
||||
|
||||
/* PMU WKUP pin definitions */
|
||||
#define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */
|
||||
#ifdef GD32E230
|
||||
#define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */
|
||||
#endif /* GD32E230 */
|
||||
#define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5 /*!< WKUP Pin 5 (PB5) enable */
|
||||
#define PMU_WAKEUP_PIN6 PMU_CS_WUPEN6 /*!< WKUP Pin 6 (PB15) enable */
|
||||
|
||||
/* PMU flag definitions */
|
||||
#define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */
|
||||
#define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */
|
||||
#define PMU_FLAG_LVD PMU_CS_LVDF /*!< LVD flag status */
|
||||
|
||||
/* PMU flag reset definitions */
|
||||
#define PMU_FLAG_RESET_WAKEUP PMU_CTL_WURST /*!< wakeup flag reset */
|
||||
#define PMU_FLAG_RESET_STANDBY PMU_CTL_STBRST /*!< standby flag reset */
|
||||
|
||||
/* PMU command constants definitions */
|
||||
#define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */
|
||||
#define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */
|
||||
|
||||
/* function declarations */
|
||||
/* reset PMU registers */
|
||||
void pmu_deinit(void);
|
||||
|
||||
/* select low voltage detector threshold */
|
||||
void pmu_lvd_select(uint32_t lvdt_n);
|
||||
/* select LDO output voltage */
|
||||
void pmu_ldo_output_select(uint32_t ldo_output);
|
||||
/* disable PMU lvd */
|
||||
void pmu_lvd_disable(void);
|
||||
|
||||
/* set PMU mode */
|
||||
/* PMU work in sleep mode */
|
||||
void pmu_to_sleepmode(uint8_t sleepmodecmd);
|
||||
/* PMU work in deepsleep mode */
|
||||
void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd);
|
||||
/* PMU work in standby mode */
|
||||
void pmu_to_standbymode(void);
|
||||
/* enable PMU wakeup pin */
|
||||
void pmu_wakeup_pin_enable(uint32_t wakeup_pin);
|
||||
/* disable PMU wakeup pin */
|
||||
void pmu_wakeup_pin_disable(uint32_t wakeup_pin);
|
||||
|
||||
/* backup related functions */
|
||||
/* enable backup domain write */
|
||||
void pmu_backup_write_enable(void);
|
||||
/* disable backup domain write */
|
||||
void pmu_backup_write_disable(void);
|
||||
|
||||
/* flag functions */
|
||||
/* get flag state */
|
||||
FlagStatus pmu_flag_get(uint32_t flag);
|
||||
/* clear flag bit */
|
||||
void pmu_flag_clear(uint32_t flag);
|
||||
|
||||
#endif /* GD32E23X_PMU_H */
|
||||
@@ -0,0 +1,671 @@
|
||||
/*!
|
||||
\file gd32e23x_rcu.h
|
||||
\brief definitions for the RCU
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_RCU_H
|
||||
#define GD32E23X_RCU_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* RCU definitions */
|
||||
#define RCU RCU_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define RCU_CTL0 REG32(RCU + 0x00000000U) /*!< control register 0 */
|
||||
#define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< configuration register 0 */
|
||||
#define RCU_INT REG32(RCU + 0x00000008U) /*!< interrupt register */
|
||||
#define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */
|
||||
#define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */
|
||||
#define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB enable register */
|
||||
#define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */
|
||||
#define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */
|
||||
#define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control register */
|
||||
#define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source /clock register */
|
||||
#define RCU_AHBRST REG32(RCU + 0x00000028U) /*!< AHB reset register */
|
||||
#define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< configuration register 1 */
|
||||
#define RCU_CFG2 REG32(RCU + 0x00000030U) /*!< configuration register 2 */
|
||||
#define RCU_CTL1 REG32(RCU + 0x00000034U) /*!< control register 1 */
|
||||
#define RCU_VKEY REG32(RCU + 0x00000100U) /*!< voltage key register */
|
||||
#define RCU_DSV REG32(RCU + 0x00000134U) /*!< deep-sleep mode voltage register */
|
||||
|
||||
/* bits definitions */
|
||||
/* RCU_CTL0 */
|
||||
#define RCU_CTL0_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */
|
||||
#define RCU_CTL0_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */
|
||||
#define RCU_CTL0_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */
|
||||
#define RCU_CTL0_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */
|
||||
#define RCU_CTL0_HXTALEN BIT(16) /*!< external high speed oscillator enable */
|
||||
#define RCU_CTL0_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */
|
||||
#define RCU_CTL0_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */
|
||||
#define RCU_CTL0_CKMEN BIT(19) /*!< HXTAL clock monitor enable */
|
||||
#define RCU_CTL0_PLLEN BIT(24) /*!< PLL enable */
|
||||
#define RCU_CTL0_PLLSTB BIT(25) /*!< PLL clock stabilization flag */
|
||||
|
||||
/* RCU_CFG0 */
|
||||
#define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */
|
||||
#define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */
|
||||
#define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */
|
||||
#define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */
|
||||
#define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */
|
||||
#define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC clock prescaler selection */
|
||||
#define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */
|
||||
#define RCU_CFG0_PLLPREDV BIT(17) /*!< divider for PLL source clock selection */
|
||||
#define RCU_CFG0_PLLMF (BIT(27) | BITS(18,21)) /*!< PLL multiply factor */
|
||||
#define RCU_CFG0_CKOUTSEL BITS(24,26) /*!< CK_OUT clock source selection */
|
||||
#define RCU_CFG0_PLLMF4 BIT(27) /*!< bit 4 of PLLMF */
|
||||
#define RCU_CFG0_CKOUTDIV BITS(28,30) /*!< CK_OUT divider which the CK_OUT frequency can be reduced */
|
||||
#define RCU_CFG0_PLLDV BIT(31) /*!< CK_PLL divide by 1 or 2 */
|
||||
|
||||
/* RCU_INT */
|
||||
#define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */
|
||||
#define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */
|
||||
#define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */
|
||||
#define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */
|
||||
#define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */
|
||||
#define RCU_INT_IRC28MSTBIF BIT(5) /*!< IRC28M stabilization interrupt flag */
|
||||
#define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */
|
||||
#define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */
|
||||
#define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */
|
||||
#define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */
|
||||
#define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */
|
||||
#define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */
|
||||
#define RCU_INT_IRC28MSTBIE BIT(13) /*!< IRC28M stabilization interrupt enable */
|
||||
#define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */
|
||||
#define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */
|
||||
#define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */
|
||||
#define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */
|
||||
#define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */
|
||||
#define RCU_INT_IRC28MSTBIC BIT(21) /*!< IRC28M stabilization interrupt clear */
|
||||
#define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */
|
||||
|
||||
/* RCU_APB2RST */
|
||||
#define RCU_APB2RST_CFGCMPRST BIT(0) /*!< system configuration and comparator reset */
|
||||
#define RCU_APB2RST_ADCRST BIT(9) /*!< ADC reset */
|
||||
#define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */
|
||||
#define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */
|
||||
#define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */
|
||||
#define RCU_APB2RST_TIMER14RST BIT(16) /*!< TIMER14 reset */
|
||||
#define RCU_APB2RST_TIMER15RST BIT(17) /*!< TIMER15 reset */
|
||||
#define RCU_APB2RST_TIMER16RST BIT(18) /*!< TIMER16 reset */
|
||||
|
||||
/* RCU_APB1RST */
|
||||
#define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 timer reset */
|
||||
#define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 timer reset */
|
||||
#define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 timer reset */
|
||||
#define RCU_APB1RST_WWDGTRST BIT(11) /*!< window watchdog timer reset */
|
||||
#define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */
|
||||
#define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */
|
||||
#define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */
|
||||
#define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */
|
||||
#define RCU_APB1RST_PMURST BIT(28) /*!< power control reset */
|
||||
|
||||
/* RCU_AHBEN */
|
||||
#define RCU_AHBEN_DMAEN BIT(0) /*!< DMA clock enable */
|
||||
#define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM interface clock enable */
|
||||
#define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable */
|
||||
#define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */
|
||||
#define RCU_AHBEN_PAEN BIT(17) /*!< GPIO port A clock enable */
|
||||
#define RCU_AHBEN_PBEN BIT(18) /*!< GPIO port B clock enable */
|
||||
#define RCU_AHBEN_PCEN BIT(19) /*!< GPIO port C clock enable */
|
||||
#define RCU_AHBEN_PFEN BIT(22) /*!< GPIO port F clock enable */
|
||||
|
||||
/* RCU_APB2EN */
|
||||
#define RCU_APB2EN_CFGCMPEN BIT(0) /*!< system configuration and comparator clock enable */
|
||||
#define RCU_APB2EN_ADCEN BIT(9) /*!< ADC interface clock enable */
|
||||
#define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 timer clock enable */
|
||||
#define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */
|
||||
#define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */
|
||||
#define RCU_APB2EN_TIMER14EN BIT(16) /*!< TIMER14 timer clock enable */
|
||||
#define RCU_APB2EN_TIMER15EN BIT(17) /*!< TIMER15 timer clock enable */
|
||||
#define RCU_APB2EN_TIMER16EN BIT(18) /*!< TIMER16 timer clock enable */
|
||||
#define RCU_APB2EN_DBGMCUEN BIT(22) /*!< DBGMCU clock enable */
|
||||
|
||||
/* RCU_APB1EN */
|
||||
#define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 timer clock enable */
|
||||
#define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 timer clock enable */
|
||||
#define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 timer clock enable */
|
||||
#define RCU_APB1EN_WWDGTEN BIT(11) /*!< window watchdog timer clock enable */
|
||||
#define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */
|
||||
#define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */
|
||||
#define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */
|
||||
#define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */
|
||||
#define RCU_APB1EN_PMUEN BIT(28) /*!< power interface clock enable */
|
||||
|
||||
/* RCU_BDCTL */
|
||||
#define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */
|
||||
#define RCU_BDCTL_LXTALSTB BIT(1) /*!< external low-speed oscillator stabilization */
|
||||
#define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */
|
||||
#define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */
|
||||
#define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */
|
||||
#define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */
|
||||
#define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */
|
||||
|
||||
/* RCU_RSTSCK */
|
||||
#define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */
|
||||
#define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization */
|
||||
#define RCU_RSTSCK_V12RSTF BIT(23) /*!< V12 domain power reset flag */
|
||||
#define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */
|
||||
#define RCU_RSTSCK_OBLRSTF BIT(25) /*!< option byte loader reset flag */
|
||||
#define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */
|
||||
#define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */
|
||||
#define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */
|
||||
#define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */
|
||||
#define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */
|
||||
#define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */
|
||||
|
||||
/* RCU_AHBRST */
|
||||
#define RCU_AHBRST_PARST BIT(17) /*!< GPIO port A reset */
|
||||
#define RCU_AHBRST_PBRST BIT(18) /*!< GPIO port B reset */
|
||||
#define RCU_AHBRST_PCRST BIT(19) /*!< GPIO port C reset */
|
||||
#define RCU_AHBRST_PFRST BIT(22) /*!< GPIO port F reset */
|
||||
|
||||
/* RCU_CFG1 */
|
||||
#define RCU_CFG1_PREDV BITS(0,3) /*!< CK_HXTAL divider previous PLL */
|
||||
|
||||
/* RCU_CFG2 */
|
||||
#define RCU_CFG2_USART0SEL BITS(0,1) /*!< CK_USART0 clock source selection */
|
||||
#define RCU_CFG2_ADCSEL BIT(8) /*!< CK_ADC clock source selection */
|
||||
#define RCU_CFG2_IRC28MDIV BIT(16) /*!< CK_IRC28M divider 2 or not */
|
||||
#define RCU_CFG2_ADCPSC2 BIT(31) /*!< bit 2 of ADCPSC */
|
||||
|
||||
/* RCU_CTL1 */
|
||||
#define RCU_CTL1_IRC28MEN BIT(0) /*!< IRC28M internal 28M RC oscillator enable */
|
||||
#define RCU_CTL1_IRC28MSTB BIT(1) /*!< IRC28M internal 28M RC oscillator stabilization flag */
|
||||
#define RCU_CTL1_IRC28MADJ BITS(3,7) /*!< internal 28M RC oscillator clock trim adjust value */
|
||||
#define RCU_CTL1_IRC28MCALIB BITS(8,15) /*!< internal 28M RC oscillator calibration value register */
|
||||
|
||||
/* RCU_VKEY */
|
||||
#define RCU_VKEY_KEY BITS(0,31) /*!< key of RCU_DSV register */
|
||||
|
||||
/* RCU_DSV */
|
||||
#define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */
|
||||
|
||||
/* constants definitions */
|
||||
/* define the peripheral clock enable bit position and its register index offset */
|
||||
#define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx)<<6) | (uint32_t)(bitpos))
|
||||
#define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph)>>6)))
|
||||
#define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
/* define the voltage key unlock value */
|
||||
#define RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4D)
|
||||
|
||||
/* register index */
|
||||
typedef enum
|
||||
{
|
||||
/* peripherals enable */
|
||||
IDX_AHBEN = 0x14U,
|
||||
IDX_APB2EN = 0x18U,
|
||||
IDX_APB1EN = 0x1CU,
|
||||
/* peripherals reset */
|
||||
IDX_AHBRST = 0x28U,
|
||||
IDX_APB2RST = 0x0CU,
|
||||
IDX_APB1RST = 0x10U,
|
||||
/* clock stabilization */
|
||||
IDX_CTL0 = 0x00U,
|
||||
IDX_BDCTL = 0x20U,
|
||||
IDX_CTL1 = 0x34U,
|
||||
/* peripheral reset */
|
||||
IDX_RSTSCK = 0x24U,
|
||||
/* clock stabilization and stuck interrupt */
|
||||
IDX_INT = 0x08U,
|
||||
/* configuration register */
|
||||
IDX_CFG0 = 0x04U,
|
||||
IDX_CFG2 = 0x30U
|
||||
}reg_idx;
|
||||
|
||||
/* peripheral clock enable */
|
||||
typedef enum
|
||||
{
|
||||
/* AHB peripherals */
|
||||
RCU_DMA = RCU_REGIDX_BIT(IDX_AHBEN, 0U), /*!< DMA clock */
|
||||
RCU_CRC = RCU_REGIDX_BIT(IDX_AHBEN, 6U), /*!< CRC clock */
|
||||
RCU_GPIOA = RCU_REGIDX_BIT(IDX_AHBEN, 17U), /*!< GPIOA clock */
|
||||
RCU_GPIOB = RCU_REGIDX_BIT(IDX_AHBEN, 18U), /*!< GPIOB clock */
|
||||
RCU_GPIOC = RCU_REGIDX_BIT(IDX_AHBEN, 19U), /*!< GPIOC clock */
|
||||
RCU_GPIOF = RCU_REGIDX_BIT(IDX_AHBEN, 22U), /*!< GPIOF clock */
|
||||
|
||||
/* APB2 peripherals */
|
||||
RCU_CFGCMP = RCU_REGIDX_BIT(IDX_APB2EN, 0U), /*!< CFGCMP clock */
|
||||
RCU_ADC = RCU_REGIDX_BIT(IDX_APB2EN, 9U), /*!< ADC clock */
|
||||
RCU_TIMER0 = RCU_REGIDX_BIT(IDX_APB2EN, 11U), /*!< TIMER0 clock */
|
||||
RCU_SPI0 = RCU_REGIDX_BIT(IDX_APB2EN, 12U), /*!< SPI0 clock */
|
||||
RCU_USART0 = RCU_REGIDX_BIT(IDX_APB2EN, 14U), /*!< USART0 clock */
|
||||
RCU_TIMER14 = RCU_REGIDX_BIT(IDX_APB2EN, 16U), /*!< TIMER14 clock */
|
||||
RCU_TIMER15 = RCU_REGIDX_BIT(IDX_APB2EN, 17U), /*!< TIMER15 clock */
|
||||
RCU_TIMER16 = RCU_REGIDX_BIT(IDX_APB2EN, 18U), /*!< TIMER16 clock */
|
||||
RCU_DBGMCU = RCU_REGIDX_BIT(IDX_APB2EN, 22U), /*!< DBGMCU clock */
|
||||
|
||||
/* APB1 peripherals */
|
||||
RCU_TIMER2 = RCU_REGIDX_BIT(IDX_APB1EN, 1U), /*!< TIMER2 clock */
|
||||
RCU_TIMER5 = RCU_REGIDX_BIT(IDX_APB1EN, 4U), /*!< TIMER5 clock */
|
||||
RCU_TIMER13 = RCU_REGIDX_BIT(IDX_APB1EN, 8U), /*!< TIMER13 clock */
|
||||
RCU_WWDGT = RCU_REGIDX_BIT(IDX_APB1EN, 11U), /*!< WWDGT clock */
|
||||
RCU_SPI1 = RCU_REGIDX_BIT(IDX_APB1EN, 14U), /*!< SPI1 clock */
|
||||
RCU_USART1 = RCU_REGIDX_BIT(IDX_APB1EN, 17U), /*!< USART1 clock */
|
||||
RCU_I2C0 = RCU_REGIDX_BIT(IDX_APB1EN, 21U), /*!< I2C0 clock */
|
||||
RCU_I2C1 = RCU_REGIDX_BIT(IDX_APB1EN, 22U), /*!< I2C1 clock */
|
||||
RCU_PMU = RCU_REGIDX_BIT(IDX_APB1EN, 28U), /*!< PMU clock */
|
||||
|
||||
/* Backup domain control(BDCTL) */
|
||||
RCU_RTC = RCU_REGIDX_BIT(IDX_BDCTL, 15U) /*!< RTC clock */
|
||||
}rcu_periph_enum;
|
||||
|
||||
/* peripheral clock enable when sleep mode*/
|
||||
typedef enum
|
||||
{
|
||||
/* AHB peripherals */
|
||||
RCU_SRAM_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 2U), /*!< SRAM clock */
|
||||
RCU_FMC_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 4U), /*!< FMC clock */
|
||||
}rcu_periph_sleep_enum;
|
||||
|
||||
/* peripherals reset */
|
||||
typedef enum
|
||||
{
|
||||
/* AHB peripherals reset */
|
||||
RCU_GPIOARST = RCU_REGIDX_BIT(IDX_AHBRST, 17U), /*!< GPIOA reset */
|
||||
RCU_GPIOBRST = RCU_REGIDX_BIT(IDX_AHBRST, 18U), /*!< GPIOB reset */
|
||||
RCU_GPIOCRST = RCU_REGIDX_BIT(IDX_AHBRST, 19U), /*!< GPIOC reset */
|
||||
RCU_GPIOFRST = RCU_REGIDX_BIT(IDX_AHBRST, 22U), /*!< GPIOF reset */
|
||||
|
||||
/* APB2 peripherals reset */
|
||||
RCU_CFGCMPRST = RCU_REGIDX_BIT(IDX_APB2RST, 0U), /*!< CFGCMP reset */
|
||||
RCU_ADCRST = RCU_REGIDX_BIT(IDX_APB2RST, 9U), /*!< ADC reset */
|
||||
RCU_TIMER0RST = RCU_REGIDX_BIT(IDX_APB2RST, 11U), /*!< TIMER0 reset */
|
||||
RCU_SPI0RST = RCU_REGIDX_BIT(IDX_APB2RST, 12U), /*!< SPI0 reset */
|
||||
RCU_USART0RST = RCU_REGIDX_BIT(IDX_APB2RST, 14U), /*!< USART0 reset */
|
||||
RCU_TIMER14RST = RCU_REGIDX_BIT(IDX_APB2RST, 16U), /*!< TIMER14 reset */
|
||||
RCU_TIMER15RST = RCU_REGIDX_BIT(IDX_APB2RST, 17U), /*!< TIMER15 reset */
|
||||
RCU_TIMER16RST = RCU_REGIDX_BIT(IDX_APB2RST, 18U), /*!< TIMER16 reset */
|
||||
|
||||
/* APB1 peripherals reset */
|
||||
RCU_TIMER2RST = RCU_REGIDX_BIT(IDX_APB1RST, 1U), /*!< TIMER2 reset */
|
||||
RCU_TIMER5RST = RCU_REGIDX_BIT(IDX_APB1RST, 4U), /*!< TIMER5 reset */
|
||||
RCU_TIMER13RST = RCU_REGIDX_BIT(IDX_APB1RST, 8U), /*!< TIMER13 reset */
|
||||
RCU_WWDGTRST = RCU_REGIDX_BIT(IDX_APB1RST, 11U), /*!< WWDGT reset */
|
||||
RCU_SPI1RST = RCU_REGIDX_BIT(IDX_APB1RST, 14U), /*!< SPI1 reset */
|
||||
RCU_USART1RST = RCU_REGIDX_BIT(IDX_APB1RST, 17U), /*!< USART1 reset */
|
||||
RCU_I2C0RST = RCU_REGIDX_BIT(IDX_APB1RST, 21U), /*!< I2C0 reset */
|
||||
RCU_I2C1RST = RCU_REGIDX_BIT(IDX_APB1RST, 22U), /*!< I2C1 reset */
|
||||
RCU_PMURST = RCU_REGIDX_BIT(IDX_APB1RST, 28U), /*!< PMU reset */
|
||||
}rcu_periph_reset_enum;
|
||||
|
||||
/* clock stabilization and peripheral reset flags */
|
||||
typedef enum
|
||||
{
|
||||
RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_RSTSCK, 1U), /*!< IRC40K stabilization flags */
|
||||
RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_BDCTL, 1U), /*!< LXTAL stabilization flags */
|
||||
RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_CTL0, 1U), /*!< IRC8M stabilization flags */
|
||||
RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_CTL0, 17U), /*!< HXTAL stabilization flags */
|
||||
RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_CTL0, 25U), /*!< PLL stabilization flags */
|
||||
RCU_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_CTL1, 1U), /*!< IRC28M stabilization flags */
|
||||
|
||||
RCU_FLAG_V12RST = RCU_REGIDX_BIT(IDX_RSTSCK, 23U), /*!< V12 reset flags */
|
||||
RCU_FLAG_OBLRST = RCU_REGIDX_BIT(IDX_RSTSCK, 25U), /*!< OBL reset flags */
|
||||
RCU_FLAG_EPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 26U), /*!< EPR reset flags */
|
||||
RCU_FLAG_PORRST = RCU_REGIDX_BIT(IDX_RSTSCK, 27U), /*!< power reset flags */
|
||||
RCU_FLAG_SWRST = RCU_REGIDX_BIT(IDX_RSTSCK, 28U), /*!< SW reset flags */
|
||||
RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 29U), /*!< FWDGT reset flags */
|
||||
RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 30U), /*!< WWDGT reset flags */
|
||||
RCU_FLAG_LPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 31U) /*!< LP reset flags */
|
||||
}rcu_flag_enum;
|
||||
|
||||
/* clock stabilization and ckm interrupt flags */
|
||||
typedef enum
|
||||
{
|
||||
RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 0U), /*!< IRC40K stabilization interrupt flag */
|
||||
RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 1U), /*!< LXTAL stabilization interrupt flag */
|
||||
RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 2U), /*!< IRC8M stabilization interrupt flag */
|
||||
RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 3U), /*!< HXTAL stabilization interrupt flag */
|
||||
RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 4U), /*!< PLL stabilization interrupt flag */
|
||||
RCU_INT_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 5U), /*!< IRC28M stabilization interrupt flag */
|
||||
RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(IDX_INT, 7U), /*!< CKM interrupt flag */
|
||||
}rcu_int_flag_enum;
|
||||
|
||||
/* clock stabilization and stuck interrupt flags clear */
|
||||
typedef enum
|
||||
{
|
||||
RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 16U), /*!< IRC40K stabilization interrupt flags clear */
|
||||
RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 17U), /*!< LXTAL stabilization interrupt flags clear */
|
||||
RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 18U), /*!< IRC8M stabilization interrupt flags clear */
|
||||
RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 19U), /*!< HXTAL stabilization interrupt flags clear */
|
||||
RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 20U), /*!< PLL stabilization interrupt flags clear */
|
||||
RCU_INT_FLAG_IRC28MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 21U), /*!< IRC28M stabilization interrupt flags clear */
|
||||
RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(IDX_INT, 23U), /*!< CKM interrupt flags clear */
|
||||
}rcu_int_flag_clear_enum;
|
||||
|
||||
/* clock stabilization interrupt enable or disable */
|
||||
typedef enum
|
||||
{
|
||||
RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 8U), /*!< IRC40K stabilization interrupt */
|
||||
RCU_INT_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 9U), /*!< LXTAL stabilization interrupt */
|
||||
RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 10U), /*!< IRC8M stabilization interrupt */
|
||||
RCU_INT_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 11U), /*!< HXTAL stabilization interrupt */
|
||||
RCU_INT_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 12U), /*!< PLL stabilization interrupt */
|
||||
RCU_INT_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 13U), /*!< IRC28M stabilization interrupt */
|
||||
}rcu_int_enum;
|
||||
|
||||
/* ADC clock source */
|
||||
typedef enum
|
||||
{
|
||||
RCU_ADCCK_IRC28M_DIV2 = 0U, /*!< ADC clock source select IRC28M/2 */
|
||||
RCU_ADCCK_IRC28M, /*!< ADC clock source select IRC28M */
|
||||
RCU_ADCCK_APB2_DIV2, /*!< ADC clock source select APB2/2 */
|
||||
RCU_ADCCK_AHB_DIV3, /*!< ADC clock source select AHB/3 */
|
||||
RCU_ADCCK_APB2_DIV4, /*!< ADC clock source select APB2/4 */
|
||||
RCU_ADCCK_AHB_DIV5, /*!< ADC clock source select AHB/5 */
|
||||
RCU_ADCCK_APB2_DIV6, /*!< ADC clock source select APB2/6 */
|
||||
RCU_ADCCK_AHB_DIV7, /*!< ADC clock source select AHB/7 */
|
||||
RCU_ADCCK_APB2_DIV8, /*!< ADC clock source select APB2/8 */
|
||||
RCU_ADCCK_AHB_DIV9 /*!< ADC clock source select AHB/9 */
|
||||
}rcu_adc_clock_enum;
|
||||
|
||||
/* oscillator types */
|
||||
typedef enum
|
||||
{
|
||||
RCU_HXTAL = RCU_REGIDX_BIT(IDX_CTL0, 16U), /*!< HXTAL */
|
||||
RCU_LXTAL = RCU_REGIDX_BIT(IDX_BDCTL, 0U), /*!< LXTAL */
|
||||
RCU_IRC8M = RCU_REGIDX_BIT(IDX_CTL0, 0U), /*!< IRC8M */
|
||||
RCU_IRC28M = RCU_REGIDX_BIT(IDX_CTL1, 0U), /*!< IRC28M */
|
||||
RCU_IRC40K = RCU_REGIDX_BIT(IDX_RSTSCK, 0U), /*!< IRC40K */
|
||||
RCU_PLL_CK = RCU_REGIDX_BIT(IDX_CTL0, 24U) /*!< PLL */
|
||||
}rcu_osci_type_enum;
|
||||
|
||||
/* rcu clock frequency */
|
||||
typedef enum
|
||||
{
|
||||
CK_SYS = 0U, /*!< system clock */
|
||||
CK_AHB, /*!< AHB clock */
|
||||
CK_APB1, /*!< APB1 clock */
|
||||
CK_APB2, /*!< APB2 clock */
|
||||
CK_ADC, /*!< ADC clock */
|
||||
CK_USART /*!< USART clock */
|
||||
}rcu_clock_freq_enum;
|
||||
|
||||
/* system clock source select */
|
||||
#define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */
|
||||
#define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */
|
||||
#define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */
|
||||
|
||||
/* system clock source select status */
|
||||
#define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
|
||||
#define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */
|
||||
#define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */
|
||||
#define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLL */
|
||||
|
||||
/* AHB prescaler selection */
|
||||
#define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4))
|
||||
#define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */
|
||||
#define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */
|
||||
#define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */
|
||||
#define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */
|
||||
#define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */
|
||||
#define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */
|
||||
#define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */
|
||||
#define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */
|
||||
#define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */
|
||||
|
||||
/* APB1 prescaler selection */
|
||||
#define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8))
|
||||
#define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */
|
||||
#define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */
|
||||
#define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */
|
||||
#define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */
|
||||
#define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */
|
||||
|
||||
/* APB2 prescaler selection */
|
||||
#define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11))
|
||||
#define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */
|
||||
#define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */
|
||||
#define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */
|
||||
#define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */
|
||||
#define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */
|
||||
|
||||
/* ADC clock prescaler selection */
|
||||
#define CFG0_ADCPSC(regval) (BITS(14,15) & ((uint32_t)(regval) << 14))
|
||||
#define RCU_ADC_CKAPB2_DIV2 CFG0_ADCPSC(0) /*!< ADC clock prescaler select CK_APB2/2 */
|
||||
#define RCU_ADC_CKAPB2_DIV4 CFG0_ADCPSC(1) /*!< ADC clock prescaler select CK_APB2/4 */
|
||||
#define RCU_ADC_CKAPB2_DIV6 CFG0_ADCPSC(2) /*!< ADC clock prescaler select CK_APB2/6 */
|
||||
#define RCU_ADC_CKAPB2_DIV8 CFG0_ADCPSC(3) /*!< ADC clock prescaler select CK_APB2/8 */
|
||||
|
||||
/* PLL clock source selection */
|
||||
#define RCU_PLLSRC_IRC8M_DIV2 (uint32_t)0x00000000U /*!< PLL clock source select IRC8M/2 */
|
||||
#define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< PLL clock source select HXTAL */
|
||||
|
||||
/* HXTAL divider for PLL source clock selection */
|
||||
#define RCU_PLLPREDV (uint32_t)0x00000000U /*!< HXTAL clock selected */
|
||||
#define RCU_PLLPREDV_DIV2 RCU_CFG0_PLLPREDV /*!< HXTAL/2 clock selected */
|
||||
|
||||
/* PLL multiply factor */
|
||||
#define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18))
|
||||
#define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */
|
||||
#define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */
|
||||
#define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */
|
||||
#define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */
|
||||
#define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */
|
||||
#define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */
|
||||
#define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */
|
||||
#define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */
|
||||
#define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */
|
||||
#define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */
|
||||
#define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */
|
||||
#define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */
|
||||
#define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */
|
||||
#define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */
|
||||
#define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */
|
||||
#define RCU_PLL_MUL17 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */
|
||||
#define RCU_PLL_MUL18 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */
|
||||
#define RCU_PLL_MUL19 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */
|
||||
#define RCU_PLL_MUL20 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */
|
||||
#define RCU_PLL_MUL21 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */
|
||||
#define RCU_PLL_MUL22 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */
|
||||
#define RCU_PLL_MUL23 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */
|
||||
#define RCU_PLL_MUL24 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */
|
||||
#define RCU_PLL_MUL25 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */
|
||||
#define RCU_PLL_MUL26 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */
|
||||
#define RCU_PLL_MUL27 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */
|
||||
#define RCU_PLL_MUL28 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */
|
||||
#define RCU_PLL_MUL29 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */
|
||||
#define RCU_PLL_MUL30 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */
|
||||
#define RCU_PLL_MUL31 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */
|
||||
#define RCU_PLL_MUL32 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */
|
||||
|
||||
/* CK_OUT clock source selection */
|
||||
#define CFG0_CKOUTSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
|
||||
#define RCU_CKOUTSRC_NONE CFG0_CKOUTSEL(0) /*!< no clock selected */
|
||||
#define RCU_CKOUTSRC_IRC28M CFG0_CKOUTSEL(1) /*!< CK_OUT clock source select IRC28M */
|
||||
#define RCU_CKOUTSRC_IRC40K CFG0_CKOUTSEL(2) /*!< CK_OUT clock source select IRC40K */
|
||||
#define RCU_CKOUTSRC_LXTAL CFG0_CKOUTSEL(3) /*!< CK_OUT clock source select LXTAL */
|
||||
#define RCU_CKOUTSRC_CKSYS CFG0_CKOUTSEL(4) /*!< CK_OUT clock source select CKSYS */
|
||||
#define RCU_CKOUTSRC_IRC8M CFG0_CKOUTSEL(5) /*!< CK_OUT clock source select IRC8M */
|
||||
#define RCU_CKOUTSRC_HXTAL CFG0_CKOUTSEL(6) /*!< CK_OUT clock source select HXTAL */
|
||||
#define RCU_CKOUTSRC_CKPLL_DIV1 (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7)) /*!< CK_OUT clock source select CK_PLL */
|
||||
#define RCU_CKOUTSRC_CKPLL_DIV2 CFG0_CKOUTSEL(7) /*!< CK_OUT clock source select CK_PLL/2 */
|
||||
|
||||
/* CK_OUT divider */
|
||||
#define CFG0_CKOUTDIV(regval) (BITS(28,30) & ((uint32_t)(regval) << 28))
|
||||
#define RCU_CKOUT_DIV1 CFG0_CKOUTDIV(0) /*!< CK_OUT is divided by 1 */
|
||||
#define RCU_CKOUT_DIV2 CFG0_CKOUTDIV(1) /*!< CK_OUT is divided by 2 */
|
||||
#define RCU_CKOUT_DIV4 CFG0_CKOUTDIV(2) /*!< CK_OUT is divided by 4 */
|
||||
#define RCU_CKOUT_DIV8 CFG0_CKOUTDIV(3) /*!< CK_OUT is divided by 8 */
|
||||
#define RCU_CKOUT_DIV16 CFG0_CKOUTDIV(4) /*!< CK_OUT is divided by 16 */
|
||||
#define RCU_CKOUT_DIV32 CFG0_CKOUTDIV(5) /*!< CK_OUT is divided by 32 */
|
||||
#define RCU_CKOUT_DIV64 CFG0_CKOUTDIV(6) /*!< CK_OUT is divided by 64 */
|
||||
#define RCU_CKOUT_DIV128 CFG0_CKOUTDIV(7) /*!< CK_OUT is divided by 128 */
|
||||
|
||||
/* CK_PLL divide by 1 or 2 for CK_OUT */
|
||||
#define RCU_PLLDV_CKPLL_DIV2 (uint32_t)0x00000000U /*!< CK_PLL divide by 2 for CK_OUT */
|
||||
#define RCU_PLLDV_CKPLL RCU_CFG0_PLLDV /*!< CK_PLL divide by 1 for CK_OUT */
|
||||
|
||||
/* LXTAL drive capability */
|
||||
#define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3))
|
||||
#define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */
|
||||
#define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */
|
||||
#define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */
|
||||
#define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */
|
||||
|
||||
/* RTC clock entry selection */
|
||||
#define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
|
||||
#define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */
|
||||
#define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< LXTAL selected as RTC source clock */
|
||||
#define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< IRC40K selected as RTC source clock */
|
||||
#define RCU_RTCSRC_HXTAL_DIV32 BDCTL_RTCSRC(3) /*!< HXTAL/32 selected as RTC source clock */
|
||||
|
||||
/* CK_HXTAL divider previous PLL */
|
||||
#define CFG1_PREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0))
|
||||
#define RCU_PLL_PREDV1 CFG1_PREDV(0) /*!< PLL not divided */
|
||||
#define RCU_PLL_PREDV2 CFG1_PREDV(1) /*!< PLL divided by 2 */
|
||||
#define RCU_PLL_PREDV3 CFG1_PREDV(2) /*!< PLL divided by 3 */
|
||||
#define RCU_PLL_PREDV4 CFG1_PREDV(3) /*!< PLL divided by 4 */
|
||||
#define RCU_PLL_PREDV5 CFG1_PREDV(4) /*!< PLL divided by 5 */
|
||||
#define RCU_PLL_PREDV6 CFG1_PREDV(5) /*!< PLL divided by 6 */
|
||||
#define RCU_PLL_PREDV7 CFG1_PREDV(6) /*!< PLL divided by 7 */
|
||||
#define RCU_PLL_PREDV8 CFG1_PREDV(7) /*!< PLL divided by 8 */
|
||||
#define RCU_PLL_PREDV9 CFG1_PREDV(8) /*!< PLL divided by 9 */
|
||||
#define RCU_PLL_PREDV10 CFG1_PREDV(9) /*!< PLL divided by 10 */
|
||||
#define RCU_PLL_PREDV11 CFG1_PREDV(10) /*!< PLL divided by 11 */
|
||||
#define RCU_PLL_PREDV12 CFG1_PREDV(11) /*!< PLL divided by 12 */
|
||||
#define RCU_PLL_PREDV13 CFG1_PREDV(12) /*!< PLL divided by 13 */
|
||||
#define RCU_PLL_PREDV14 CFG1_PREDV(13) /*!< PLL divided by 14 */
|
||||
#define RCU_PLL_PREDV15 CFG1_PREDV(14) /*!< PLL divided by 15 */
|
||||
#define RCU_PLL_PREDV16 CFG1_PREDV(15) /*!< PLL divided by 16 */
|
||||
|
||||
/* USART0 clock source selection */
|
||||
#define CFG2_USART0SEL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define RCU_USART0SRC_CKAPB2 CFG2_USART0SEL(0) /*!< CK_USART0 select CK_APB2 */
|
||||
#define RCU_USART0SRC_CKSYS CFG2_USART0SEL(1) /*!< CK_USART0 select CK_SYS */
|
||||
#define RCU_USART0SRC_LXTAL CFG2_USART0SEL(2) /*!< CK_USART0 select LXTAL */
|
||||
#define RCU_USART0SRC_IRC8M CFG2_USART0SEL(3) /*!< CK_USART0 select IRC8M */
|
||||
|
||||
/* ADC clock source selection */
|
||||
#define RCU_ADCSRC_IRC28M (uint32_t)0x00000000U /*!< ADC clock source select */
|
||||
#define RCU_ADCSRC_AHB_APB2DIV RCU_CFG2_ADCSEL /*!< ADC clock source select */
|
||||
|
||||
/* IRC28M clock divider for ADC */
|
||||
#define RCU_ADC_IRC28M_DIV2 (uint32_t)0x00000000U /*!< IRC28M/2 select to ADC clock */
|
||||
#define RCU_ADC_IRC28M_DIV1 RCU_CFG2_IRC28MDIV /*!< IRC28M select to ADC clock */
|
||||
|
||||
/* Deep-sleep mode voltage */
|
||||
#define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */
|
||||
#define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */
|
||||
#define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */
|
||||
#define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(3) /*!< core voltage is 1.2V in deep-sleep mode */
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize the RCU */
|
||||
void rcu_deinit(void);
|
||||
/* enable the peripherals clock */
|
||||
void rcu_periph_clock_enable(rcu_periph_enum periph);
|
||||
/* disable the peripherals clock */
|
||||
void rcu_periph_clock_disable(rcu_periph_enum periph);
|
||||
/* enable the peripherals clock when sleep mode */
|
||||
void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph);
|
||||
/* disable the peripherals clock when sleep mode */
|
||||
void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph);
|
||||
/* reset the peripherals */
|
||||
void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset);
|
||||
/* disable reset the peripheral */
|
||||
void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset);
|
||||
/* reset the BKP */
|
||||
void rcu_bkp_reset_enable(void);
|
||||
/* disable the BKP reset */
|
||||
void rcu_bkp_reset_disable(void);
|
||||
|
||||
/* configure the system clock source */
|
||||
void rcu_system_clock_source_config(uint32_t ck_sys);
|
||||
/* get the system clock source */
|
||||
uint32_t rcu_system_clock_source_get(void);
|
||||
/* configure the AHB prescaler selection */
|
||||
void rcu_ahb_clock_config(uint32_t ck_ahb);
|
||||
/* configure the APB1 prescaler selection */
|
||||
void rcu_apb1_clock_config(uint32_t ck_apb1);
|
||||
/* configure the APB2 prescaler selection */
|
||||
void rcu_apb2_clock_config(uint32_t ck_apb2);
|
||||
/* configure the ADC clock source and prescaler selection */
|
||||
void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc);
|
||||
/* configure the CK_OUT clock source and divider */
|
||||
void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div);
|
||||
|
||||
/* configure the PLL clock source selection and PLL multiply factor */
|
||||
void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul);
|
||||
/* configure the USART clock source selection */
|
||||
void rcu_usart_clock_config(uint32_t ck_usart);
|
||||
/* configure the RTC clock source selection */
|
||||
void rcu_rtc_clock_config(uint32_t rtc_clock_source);
|
||||
/* configure the HXTAL divider used as input of PLL */
|
||||
void rcu_hxtal_prediv_config(uint32_t hxtal_prediv);
|
||||
/* configure the LXTAL drive capability */
|
||||
void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap);
|
||||
|
||||
/* wait until oscillator stabilization flags is SET */
|
||||
ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci);
|
||||
/* turn on the oscillator */
|
||||
void rcu_osci_on(rcu_osci_type_enum osci);
|
||||
/* turn off the oscillator */
|
||||
void rcu_osci_off(rcu_osci_type_enum osci);
|
||||
/* enable the oscillator bypass mode */
|
||||
void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci);
|
||||
/* disable the oscillator bypass mode */
|
||||
void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci);
|
||||
/* enable the HXTAL clock monitor */
|
||||
void rcu_hxtal_clock_monitor_enable(void);
|
||||
/* disable the HXTAL clock monitor */
|
||||
void rcu_hxtal_clock_monitor_disable(void);
|
||||
|
||||
/* set the IRC8M adjust value */
|
||||
void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval);
|
||||
/* set the IRC28M adjust value */
|
||||
void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval);
|
||||
/* unlock the voltage key */
|
||||
void rcu_voltage_key_unlock(void);
|
||||
/* set the deep sleep mode voltage */
|
||||
void rcu_deepsleep_voltage_set(uint32_t dsvol);
|
||||
|
||||
/* get the system clock, bus and peripheral clock frequency */
|
||||
uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock);
|
||||
|
||||
/* get the clock stabilization and periphral reset flags */
|
||||
FlagStatus rcu_flag_get(rcu_flag_enum flag);
|
||||
/* clear the reset flag */
|
||||
void rcu_all_reset_flag_clear(void);
|
||||
/* get the clock stabilization interrupt and ckm flags */
|
||||
FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag);
|
||||
/* clear the interrupt flags */
|
||||
void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear);
|
||||
/* enable the stabilization interrupt */
|
||||
void rcu_interrupt_enable(rcu_int_enum stab_int);
|
||||
/* disable the stabilization interrupt */
|
||||
void rcu_interrupt_disable(rcu_int_enum stab_int);
|
||||
|
||||
#endif /* GD32E23X_RCU_H */
|
||||
@@ -0,0 +1,560 @@
|
||||
/*!
|
||||
\file gd32e23x_rtc.h
|
||||
\brief definitions for the RTC
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_RTC_H
|
||||
#define GD32E23X_RTC_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* RTC definitions */
|
||||
#define RTC RTC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define RTC_TIME REG32((RTC) + 0x00000000U) /*!< RTC time of day register */
|
||||
#define RTC_DATE REG32((RTC) + 0x00000004U) /*!< RTC date register */
|
||||
#define RTC_CTL REG32((RTC) + 0x00000008U) /*!< RTC control register */
|
||||
#define RTC_STAT REG32((RTC) + 0x0000000CU) /*!< RTC status register */
|
||||
#define RTC_PSC REG32((RTC) + 0x00000010U) /*!< RTC time prescaler register */
|
||||
#define RTC_ALRM0TD REG32((RTC) + 0x0000001CU) /*!< RTC alarm 0 time and date register */
|
||||
#define RTC_WPK REG32((RTC) + 0x00000024U) /*!< RTC write protection key register */
|
||||
#define RTC_SS REG32((RTC) + 0x00000028U) /*!< RTC sub second register */
|
||||
#define RTC_SHIFTCTL REG32((RTC) + 0x0000002CU) /*!< RTC shift function control register */
|
||||
#define RTC_TTS REG32((RTC) + 0x00000030U) /*!< RTC time of timestamp register */
|
||||
#define RTC_DTS REG32((RTC) + 0x00000034U) /*!< RTC date of timestamp register */
|
||||
#define RTC_SSTS REG32((RTC) + 0x00000038U) /*!< RTC sub second of timestamp register */
|
||||
#define RTC_HRFC REG32((RTC) + 0x0000003CU) /*!< RTC high resolution frequency compensation registor */
|
||||
#define RTC_TAMP REG32((RTC) + 0x00000040U) /*!< RTC tamper register */
|
||||
#define RTC_ALRM0SS REG32((RTC) + 0x00000044U) /*!< RTC alarm 0 sub second register */
|
||||
#define RTC_BKP0 REG32((RTC) + 0x00000050U) /*!< RTC backup 0 register */
|
||||
#define RTC_BKP1 REG32((RTC) + 0x00000054U) /*!< RTC backup 1 register */
|
||||
#define RTC_BKP2 REG32((RTC) + 0x00000058U) /*!< RTC backup 2 register */
|
||||
#define RTC_BKP3 REG32((RTC) + 0x0000005CU) /*!< RTC backup 3 register */
|
||||
#define RTC_BKP4 REG32((RTC) + 0x00000060U) /*!< RTC backup 4 register */
|
||||
|
||||
/* bits definitions */
|
||||
/* RTC_TIME */
|
||||
#define RTC_TIME_SCU BITS(0,3) /*!< second units in BCD code */
|
||||
#define RTC_TIME_SCT BITS(4,6) /*!< second tens in BCD code */
|
||||
#define RTC_TIME_MNU BITS(8,11) /*!< minute units in BCD code */
|
||||
#define RTC_TIME_MNT BITS(12,14) /*!< minute tens in BCD code */
|
||||
#define RTC_TIME_HRU BITS(16,19) /*!< hour units in BCD code */
|
||||
#define RTC_TIME_HRT BITS(20,21) /*!< hour tens in BCD code */
|
||||
#define RTC_TIME_PM BIT(22) /*!< AM/PM notation */
|
||||
|
||||
/* RTC_DATE */
|
||||
#define RTC_DATE_DAYU BITS(0,3) /*!< date units in BCD code */
|
||||
#define RTC_DATE_DAYT BITS(4,5) /*!< date tens in BCD code */
|
||||
#define RTC_DATE_MONU BITS(8,11) /*!< month units in BCD code */
|
||||
#define RTC_DATE_MONT BIT(12) /*!< month tens in BCD code */
|
||||
#define RTC_DATE_DOW BITS(13,15) /*!< day of week units */
|
||||
#define RTC_DATE_YRU BITS(16,19) /*!< year units in BCD code */
|
||||
#define RTC_DATE_YRT BITS(20,23) /*!< year tens in BCD code */
|
||||
|
||||
/* RTC_CTL */
|
||||
#define RTC_CTL_TSEG BIT(3) /*!< valid event edge of time-stamp */
|
||||
#define RTC_CTL_REFEN BIT(4) /*!< reference clock detection function enable */
|
||||
#define RTC_CTL_BPSHAD BIT(5) /*!< shadow registers bypass control */
|
||||
#define RTC_CTL_CS BIT(6) /*!< display format of clock system */
|
||||
#define RTC_CTL_ALRM0EN BIT(8) /*!< alarm function enable */
|
||||
#define RTC_CTL_TSEN BIT(11) /*!< time-stamp function enable */
|
||||
#define RTC_CTL_ALRM0IE BIT(12) /*!< RTC alarm interrupt enable */
|
||||
#define RTC_CTL_TSIE BIT(15) /*!< time-stamp interrupt enable */
|
||||
#define RTC_CTL_A1H BIT(16) /*!< add 1 hour(summer time change) */
|
||||
#define RTC_CTL_S1H BIT(17) /*!< subtract 1 hour(winter time change) */
|
||||
#define RTC_CTL_DSM BIT(18) /*!< daylight saving mark */
|
||||
#define RTC_CTL_COS BIT(19) /*!< calibration output selection */
|
||||
#define RTC_CTL_OPOL BIT(20) /*!< output polarity */
|
||||
#define RTC_CTL_OS BITS(21,22) /*!< output selection */
|
||||
#define RTC_CTL_COEN BIT(23) /*!< calibration output enable */
|
||||
|
||||
/* RTC_STAT */
|
||||
#define RTC_STAT_ALRM0WF BIT(0) /*!< alarm configuration can be write flag */
|
||||
#define RTC_STAT_SOPF BIT(3) /*!< shift function operation pending flag */
|
||||
#define RTC_STAT_YCM BIT(4) /*!< year configuration mark status flag */
|
||||
#define RTC_STAT_RSYNF BIT(5) /*!< register synchronization flag */
|
||||
#define RTC_STAT_INITF BIT(6) /*!< initialization state flag */
|
||||
#define RTC_STAT_INITM BIT(7) /*!< enter initialization mode */
|
||||
#define RTC_STAT_ALRM0F BIT(8) /*!< alarm occurs flag */
|
||||
#define RTC_STAT_TSF BIT(11) /*!< time-stamp flag */
|
||||
#define RTC_STAT_TSOVRF BIT(12) /*!< time-stamp overflow flag */
|
||||
#define RTC_STAT_TP0F BIT(13) /*!< RTC tamp 0 detected flag */
|
||||
#define RTC_STAT_TP1F BIT(14) /*!< RTC tamp 1 detected flag */
|
||||
#define RTC_STAT_SCPF BIT(16) /*!< recalibration pending flag */
|
||||
|
||||
/* RTC_PSC */
|
||||
#define RTC_PSC_FACTOR_S BITS(0,14) /*!< synchronous prescaler factor */
|
||||
#define RTC_PSC_FACTOR_A BITS(16,22) /*!< asynchronous prescaler factor */
|
||||
|
||||
/* RTC_ALRM0TD */
|
||||
#define RTC_ALRM0TD_SCU BITS(0,3) /*!< second units in BCD code */
|
||||
#define RTC_ALRM0TD_SCT BITS(4,6) /*!< second tens in BCD code */
|
||||
#define RTC_ALRM0TD_MSKS BIT(7) /*!< alarm second mask bit */
|
||||
#define RTC_ALRM0TD_MNU BITS(8,11) /*!< minutes units in BCD code */
|
||||
#define RTC_ALRM0TD_MNT BITS(12,14) /*!< minutes tens in BCD code */
|
||||
#define RTC_ALRM0TD_MSKM BIT(15) /*!< alarm minutes mask bit */
|
||||
#define RTC_ALRM0TD_HRU BITS(16,19) /*!< hour units in BCD code */
|
||||
#define RTC_ALRM0TD_HRT BITS(20,21) /*!< hour units in BCD code */
|
||||
#define RTC_ALRM0TD_PM BIT(22) /*!< AM/PM flag */
|
||||
#define RTC_ALRM0TD_MSKH BIT(23) /*!< alarm hour mask bit */
|
||||
#define RTC_ALRM0TD_DAYU BITS(24,27) /*!< date units or week day in BCD code */
|
||||
#define RTC_ALRM0TD_DAYT BITS(28,29) /*!< date tens in BCD code */
|
||||
#define RTC_ALRM0TD_DOWS BIT(30) /*!< day of week selection */
|
||||
#define RTC_ALRM0TD_MSKD BIT(31) /*!< alarm date mask bit */
|
||||
|
||||
/* RTC_WPK */
|
||||
#define RTC_WPK_WPK BITS(0,7) /*!< key for write protection */
|
||||
|
||||
/* RTC_SS */
|
||||
#define RTC_SS_SSC BITS(0,15) /*!< sub second value */
|
||||
|
||||
/* RTC_SHIFTCTL */
|
||||
#define RTC_SHIFTCTL_SFS BITS(0,14) /*!< subtract a fraction of a second */
|
||||
#define RTC_SHIFTCTL_A1S BIT(31) /*!< one second add */
|
||||
|
||||
/* RTC_TTS */
|
||||
#define RTC_TTS_SCU BITS(0,3) /*!< second units in BCD code */
|
||||
#define RTC_TTS_SCT BITS(4,6) /*!< second units in BCD code */
|
||||
#define RTC_TTS_MNU BITS(8,11) /*!< minute units in BCD code */
|
||||
#define RTC_TTS_MNT BITS(12,14) /*!< minute tens in BCD code */
|
||||
#define RTC_TTS_HRU BITS(16,19) /*!< hour units in BCD code */
|
||||
#define RTC_TTS_HRT BITS(20,21) /*!< hour tens in BCD code */
|
||||
#define RTC_TTS_PM BIT(22) /*!< AM/PM notation */
|
||||
|
||||
/* RTC_DTS */
|
||||
#define RTC_DTS_DAYU BITS(0,3) /*!< date units in BCD code */
|
||||
#define RTC_DTS_DAYT BITS(4,5) /*!< date tens in BCD code */
|
||||
#define RTC_DTS_MONU BITS(8,11) /*!< month units in BCD code */
|
||||
#define RTC_DTS_MONT BIT(12) /*!< month tens in BCD code */
|
||||
#define RTC_DTS_DOW BITS(13,15) /*!< day of week units */
|
||||
|
||||
/* RTC_SSTS */
|
||||
#define RTC_SSTS_SSC BITS(0,15) /*!< timestamp sub second units */
|
||||
|
||||
/* RTC_HRFC */
|
||||
#define RTC_HRFC_CMSK BITS(0,8) /*!< calibration mask number */
|
||||
#define RTC_HRFC_CWND16 BIT(13) /*!< calibration window select 16 seconds */
|
||||
#define RTC_HRFC_CWND8 BIT(14) /*!< calibration window select 16 seconds */
|
||||
#define RTC_HRFC_FREQI BIT(15) /*!< increase RTC frequency by 488.5ppm */
|
||||
|
||||
/* RTC_TAMP */
|
||||
#define RTC_TAMP_TP0EN BIT(0) /*!< tamper 0 detection enable */
|
||||
#define RTC_TAMP_TP0EG BIT(1) /*!< tamper 0 event trigger edge for RTC tamp 0 input */
|
||||
#define RTC_TAMP_TPIE BIT(2) /*!< tamper detection interrupt enable */
|
||||
#define RTC_TAMP_TP1EN BIT(3) /*!< tamper 1 detection enable */
|
||||
#define RTC_TAMP_TP1EG BIT(4) /*!< tamper 1 event trigger edge for RTC tamp 1 input */
|
||||
#define RTC_TAMP_TPTS BIT(7) /*!< make tamper function used for timestamp function */
|
||||
#define RTC_TAMP_FREQ BITS(8,10) /*!< sample frequency of tamper event detection */
|
||||
#define RTC_TAMP_FLT BITS(11,12) /*!< RTC tamp x filter count setting */
|
||||
#define RTC_TAMP_PRCH BITS(13,14) /*!< precharge duration time of RTC tamp x */
|
||||
#define RTC_TAMP_DISPU BIT(15) /*!< RTC tamp x pull up disable bit */
|
||||
#define RTC_TAMP_PC13VAL BIT(18) /*!< alarm output type control/PC13 output value */
|
||||
#define RTC_TAMP_PC13MDE BIT(19) /*!< PC13 mode */
|
||||
#define RTC_TAMP_PC14VAL BIT(20) /*!< PC14 output value */
|
||||
#define RTC_TAMP_PC14MDE BIT(21) /*!< PC14 mode */
|
||||
#define RTC_TAMP_PC15VAL BIT(22) /*!< PC15 output value */
|
||||
#define RTC_TAMP_PC15MDE BIT(23) /*!< PC15 mode */
|
||||
|
||||
/* RTC_ALRM0SS */
|
||||
#define RTC_ALRM0SS_SSC BITS(0,14) /*!< alarm sub second value */
|
||||
#define RTC_ALRM0SS_MASKSSC BITS(24,27) /*!< mask control bit of SS */
|
||||
|
||||
/* RTC_BKP0 */
|
||||
#define RTC_BKP0_DATA BITS(0,31) /*!< backup domain registers */
|
||||
|
||||
/* RTC_BKP1 */
|
||||
#define RTC_BKP1_DATA BITS(0,31) /*!< backup domain registers */
|
||||
|
||||
/* RTC_BKP2 */
|
||||
#define RTC_BKP2_DATA BITS(0,31) /*!< backup domain registers */
|
||||
|
||||
/* RTC_BKP3 */
|
||||
#define RTC_BKP3_DATA BITS(0,31) /*!< backup domain registers */
|
||||
|
||||
/* RTC_BKP4 */
|
||||
#define RTC_BKP4_DATA BITS(0,31) /*!< backup domain registers */
|
||||
|
||||
/* constants definitions */
|
||||
/* structure for initialization of the RTC */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t rtc_year; /*!< RTC year value: 0x0 - 0x99(BCD format) */
|
||||
uint8_t rtc_month; /*!< RTC month value */
|
||||
uint8_t rtc_date; /*!< RTC date value: 0x1 - 0x31(BCD format) */
|
||||
uint8_t rtc_day_of_week; /*!< RTC weekday value */
|
||||
uint8_t rtc_hour; /*!< RTC hour value */
|
||||
uint8_t rtc_minute; /*!< RTC minute value: 0x0 - 0x59(BCD format) */
|
||||
uint8_t rtc_second; /*!< RTC second value: 0x0 - 0x59(BCD format) */
|
||||
uint16_t rtc_factor_asyn; /*!< RTC asynchronous prescaler value: 0x0 - 0x7F */
|
||||
uint16_t rtc_factor_syn; /*!< RTC synchronous prescaler value: 0x0 - 0x7FFF */
|
||||
uint32_t rtc_am_pm; /*!< RTC AM/PM value */
|
||||
uint32_t rtc_display_format; /*!< RTC time notation */
|
||||
}rtc_parameter_struct;
|
||||
|
||||
/* structure for RTC alarm configuration */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t rtc_alarm_mask; /*!< RTC alarm mask */
|
||||
uint32_t rtc_weekday_or_date; /*!< specify RTC alarm is on date or weekday */
|
||||
uint8_t rtc_alarm_day; /*!< RTC alarm date or weekday value*/
|
||||
uint8_t rtc_alarm_hour; /*!< RTC alarm hour value */
|
||||
uint8_t rtc_alarm_minute; /*!< RTC alarm minute value: 0x0 - 0x59(BCD format) */
|
||||
uint8_t rtc_alarm_second; /*!< RTC alarm second value: 0x0 - 0x59(BCD format) */
|
||||
uint32_t rtc_am_pm; /*!< RTC alarm AM/PM value */
|
||||
}rtc_alarm_struct;
|
||||
|
||||
/* structure for RTC time-stamp configuration */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t rtc_timestamp_month; /*!< RTC time-stamp month value */
|
||||
uint8_t rtc_timestamp_date; /*!< RTC time-stamp date value: 0x1 - 0x31(BCD format) */
|
||||
uint8_t rtc_timestamp_day; /*!< RTC time-stamp weekday value */
|
||||
uint8_t rtc_timestamp_hour; /*!< RTC time-stamp hour value */
|
||||
uint8_t rtc_timestamp_minute; /*!< RTC time-stamp minute value: 0x0 - 0x59(BCD format) */
|
||||
uint8_t rtc_timestamp_second; /*!< RTC time-stamp second value: 0x0 - 0x59(BCD format) */
|
||||
uint32_t rtc_am_pm; /*!< RTC time-stamp AM/PM value */
|
||||
}rtc_timestamp_struct;
|
||||
|
||||
/* structure for RTC tamper configuration */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t rtc_tamper_source; /*!< RTC tamper source */
|
||||
uint32_t rtc_tamper_trigger; /*!< RTC tamper trigger */
|
||||
uint32_t rtc_tamper_filter; /*!< RTC tamper consecutive samples needed during a voltage level detection */
|
||||
uint32_t rtc_tamper_sample_frequency; /*!< RTC tamper sampling frequency during a voltage level detection */
|
||||
ControlStatus rtc_tamper_precharge_enable; /*!< RTC tamper precharge feature during a voltage level detection */
|
||||
uint32_t rtc_tamper_precharge_time; /*!< RTC tamper precharge duration if precharge feature is enabled */
|
||||
ControlStatus rtc_tamper_with_timestamp; /*!< RTC tamper time-stamp feature */
|
||||
}rtc_tamper_struct;
|
||||
|
||||
/* time register value */
|
||||
#define TIME_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TIME_SC bit field */
|
||||
#define GET_TIME_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TIME_SC bit field */
|
||||
|
||||
#define TIME_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TIME_MN bit field */
|
||||
#define GET_TIME_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TIME_MN bit field */
|
||||
|
||||
#define TIME_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TIME_HR bit field */
|
||||
#define GET_TIME_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TIME_HR bit field */
|
||||
|
||||
#define RTC_AM ((uint32_t)0x00000000U) /*!< AM format */
|
||||
#define RTC_PM RTC_TIME_PM /*!< PM format */
|
||||
|
||||
/* date register value */
|
||||
#define DATE_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DATE_DAY bit field */
|
||||
#define GET_DATE_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DATE_DAY bit field */
|
||||
|
||||
#define DATE_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DATE_MON bit field */
|
||||
#define GET_DATE_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DATE_MON bit field */
|
||||
#define RTC_JAN ((uint8_t)0x01U) /*!< Janurary */
|
||||
#define RTC_FEB ((uint8_t)0x02U) /*!< February */
|
||||
#define RTC_MAR ((uint8_t)0x03U) /*!< March */
|
||||
#define RTC_APR ((uint8_t)0x04U) /*!< April */
|
||||
#define RTC_MAY ((uint8_t)0x05U) /*!< May */
|
||||
#define RTC_JUN ((uint8_t)0x06U) /*!< June */
|
||||
#define RTC_JUL ((uint8_t)0x07U) /*!< July */
|
||||
#define RTC_AUG ((uint8_t)0x08U) /*!< August */
|
||||
#define RTC_SEP ((uint8_t)0x09U) /*!< September */
|
||||
#define RTC_OCT ((uint8_t)0x10U) /*!< October */
|
||||
#define RTC_NOV ((uint8_t)0x11U) /*!< November */
|
||||
#define RTC_DEC ((uint8_t)0x12U) /*!< December */
|
||||
|
||||
#define DATE_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DATE_DOW bit field */
|
||||
#define GET_DATE_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DATE_DOW bit field */
|
||||
#define RTC_MONDAY ((uint8_t)0x01U) /*!< Monday */
|
||||
#define RTC_TUESDAY ((uint8_t)0x02U) /*!< Tuesday */
|
||||
#define RTC_WEDSDAY ((uint8_t)0x03U) /*!< Wednesday */
|
||||
#define RTC_THURSDAY ((uint8_t)0x04U) /*!< Thursday */
|
||||
#define RTC_FRIDAY ((uint8_t)0x05U) /*!< Friday */
|
||||
#define RTC_SATURDAY ((uint8_t)0x06U) /*!< Saturday */
|
||||
#define RTC_SUNDAY ((uint8_t)0x07U) /*!< Sunday */
|
||||
|
||||
#define DATE_YR(regval) (BITS(16,23) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_DATE_YR bit field */
|
||||
#define GET_DATE_YR(regval) GET_BITS((regval),16,23) /*!< get value of RTC_DATE_YR bit field */
|
||||
|
||||
/* ctl register value */
|
||||
#define CTL_OS(regval) (BITS(21,22) & ((uint32_t)(regval) << 21U)) /*!< write value to RTC_CTL_OS bit field */
|
||||
#define RTC_OS_DISABLE CTL_OS(0) /*!< disable output RTC_ALARM */
|
||||
#define RTC_OS_ENABLE CTL_OS(1) /*!< enable alarm flag output */
|
||||
|
||||
#define RTC_CALIBRATION_512HZ RTC_CTL_COEN /*!< calibration output of 512Hz is enable */
|
||||
#define RTC_CALIBRATION_1HZ (RTC_CTL_COEN | RTC_CTL_COS) /*!< calibration output of 1Hz is enable */
|
||||
#define RTC_ALARM_HIGH RTC_OS_ENABLE /*!< enable alarm flag output with high level */
|
||||
#define RTC_ALARM_LOW (RTC_OS_ENABLE | RTC_CTL_OPOL) /*!< enable alarm flag output with low level*/
|
||||
|
||||
#define RTC_24HOUR ((uint32_t)0x00000000U) /*!< 24-hour format */
|
||||
#define RTC_12HOUR RTC_CTL_CS /*!< 12-hour format */
|
||||
|
||||
#define RTC_TIMESTAMP_RISING_EDGE ((uint32_t)0x00000000U) /*!< rising edge is valid event edge for time-stamp event */
|
||||
#define RTC_TIMESTAMP_FALLING_EDGE RTC_CTL_TSEG /*!< falling edge is valid event edge for time-stamp event */
|
||||
|
||||
/* psc register value */
|
||||
#define PSC_FACTOR_S(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_PSC_FACTOR_S bit field */
|
||||
#define GET_PSC_FACTOR_S(regval) GET_BITS((regval),0,14) /*!< get value of RTC_PSC_FACTOR_S bit field */
|
||||
|
||||
#define PSC_FACTOR_A(regval) (BITS(16,22) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_PSC_FACTOR_A bit field */
|
||||
#define GET_PSC_FACTOR_A(regval) GET_BITS((regval),16,22) /*!< get value of RTC_PSC_FACTOR_A bit field */
|
||||
|
||||
/* alrm0td register value */
|
||||
#define ALRM0TD_SC(regval) (BITS(0,6) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0TD_SC bit field */
|
||||
#define GET_ALRM0TD_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_ALRM0TD_SC bit field */
|
||||
|
||||
#define ALRM0TD_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_ALRM0TD_MN bit field */
|
||||
#define GET_ALRM0TD_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_ALRM0TD_MN bit field */
|
||||
|
||||
#define ALRM0TD_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_ALRM0TD_HR bit field */
|
||||
#define GET_ALRM0TD_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_ALRM0TD_HR bit field */
|
||||
|
||||
#define ALRM0TD_DAY(regval) (BITS(24,29) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0TD_DAY bit field */
|
||||
#define GET_ALRM0TD_DAY(regval) GET_BITS((regval),24,29) /*!< get value of RTC_ALRM0TD_DAY bit field */
|
||||
|
||||
#define RTC_ALARM_NONE_MASK ((uint32_t)0x00000000U) /*!< alarm none mask */
|
||||
#define RTC_ALARM_DATE_MASK RTC_ALRM0TD_MSKD /*!< alarm date mask */
|
||||
#define RTC_ALARM_HOUR_MASK RTC_ALRM0TD_MSKH /*!< alarm hour mask */
|
||||
#define RTC_ALARM_MINUTE_MASK RTC_ALRM0TD_MSKM /*!< alarm minute mask */
|
||||
#define RTC_ALARM_SECOND_MASK RTC_ALRM0TD_MSKS /*!< alarm second mask */
|
||||
#define RTC_ALARM_ALL_MASK (RTC_ALRM0TD_MSKD|RTC_ALRM0TD_MSKH|RTC_ALRM0TD_MSKM|RTC_ALRM0TD_MSKS) /*!< alarm all mask */
|
||||
|
||||
#define RTC_ALARM_DATE_SELECTED ((uint32_t)0x00000000U) /*!< alarm date format selected */
|
||||
#define RTC_ALARM_WEEKDAY_SELECTED RTC_ALRM0TD_DOWS /*!< alarm weekday format selected */
|
||||
|
||||
/* wpk register value */
|
||||
#define WPK_WPK(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_WPK_WPK bit field */
|
||||
|
||||
/* ss register value */
|
||||
#define SS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SS_SSC bit field */
|
||||
|
||||
/* shiftctl register value */
|
||||
#define SHIFTCTL_SFS(regval) (BITS(0,14) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SHIFTCTL_SFS bit field */
|
||||
|
||||
#define RTC_SHIFT_ADD1S_RESET ((uint32_t)0x00000000U) /*!< not add 1 second */
|
||||
#define RTC_SHIFT_ADD1S_SET RTC_SHIFTCTL_A1S /*!< add one second to the clock */
|
||||
|
||||
/* tts register value */
|
||||
#define TTS_SC(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_TTS_SC bit field */
|
||||
#define GET_TTS_SC(regval) GET_BITS((regval),0,6) /*!< get value of RTC_TTS_SC bit field */
|
||||
|
||||
#define TTS_MN(regval) (BITS(8,14) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TTS_MN bit field */
|
||||
#define GET_TTS_MN(regval) GET_BITS((regval),8,14) /*!< get value of RTC_TTS_MN bit field */
|
||||
|
||||
#define TTS_HR(regval) (BITS(16,21) & ((uint32_t)(regval) << 16U)) /*!< write value to RTC_TTS_HR bit field */
|
||||
#define GET_TTS_HR(regval) GET_BITS((regval),16,21) /*!< get value of RTC_TTS_HR bit field */
|
||||
|
||||
/* dts register value */
|
||||
#define DTS_DAY(regval) (BITS(0,5) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_DTS_DAY bit field */
|
||||
#define GET_DTS_DAY(regval) GET_BITS((regval),0,5) /*!< get value of RTC_DTS_DAY bit field */
|
||||
|
||||
#define DTS_MON(regval) (BITS(8,12) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_DTS_MON bit field */
|
||||
#define GET_DTS_MON(regval) GET_BITS((regval),8,12) /*!< get value of RTC_DTS_MON bit field */
|
||||
|
||||
#define DTS_DOW(regval) (BITS(13,15) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_DTS_DOW bit field */
|
||||
#define GET_DTS_DOW(regval) GET_BITS((regval),13,15) /*!< get value of RTC_DTS_DOW bit field */
|
||||
|
||||
/* ssts register value */
|
||||
#define SSTS_SSC(regval) (BITS(0,15) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_SSTS_SSC bit field */
|
||||
|
||||
/* hrfc register value */
|
||||
#define HRFC_CMSK(regval) (BITS(0,8) & ((uint32_t)(regval) << 0U)) /*!< write value to RTC_HRFC_CMSK bit field */
|
||||
|
||||
#define RTC_CALIBRATION_WINDOW_32S ((uint32_t)0x00000000U) /*!< 2exp20 RTCCLK cycles, 32s if RTCCLK = 32768 Hz */
|
||||
#define RTC_CALIBRATION_WINDOW_16S RTC_HRFC_CWND16 /*!< 2exp19 RTCCLK cycles, 16s if RTCCLK = 32768 Hz */
|
||||
#define RTC_CALIBRATION_WINDOW_8S RTC_HRFC_CWND8 /*!< 2exp18 RTCCLK cycles, 8s if RTCCLK = 32768 Hz */
|
||||
|
||||
#define RTC_CALIBRATION_PLUS_SET RTC_HRFC_FREQI /*!< increase RTC frequency by 488.5ppm */
|
||||
#define RTC_CALIBRATION_PLUS_RESET ((uint32_t)0x00000000U) /*!< no effect */
|
||||
|
||||
/* tamp register value */
|
||||
#define TAMP_FREQ(regval) (BITS(8,10) & ((uint32_t)(regval) << 8U)) /*!< write value to RTC_TAMP_FREQ bit field */
|
||||
#define RTC_FREQ_DIV32768 TAMP_FREQ(0) /*!< sample once every 32768 RTCCLK(1Hz if RTCCLK=32.768KHz) */
|
||||
#define RTC_FREQ_DIV16384 TAMP_FREQ(1) /*!< sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) */
|
||||
#define RTC_FREQ_DIV8192 TAMP_FREQ(2) /*!< sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) */
|
||||
#define RTC_FREQ_DIV4096 TAMP_FREQ(3) /*!< sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) */
|
||||
#define RTC_FREQ_DIV2048 TAMP_FREQ(4) /*!< sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) */
|
||||
#define RTC_FREQ_DIV1024 TAMP_FREQ(5) /*!< sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) */
|
||||
#define RTC_FREQ_DIV512 TAMP_FREQ(6) /*!< sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) */
|
||||
#define RTC_FREQ_DIV256 TAMP_FREQ(7) /*!< sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) */
|
||||
|
||||
#define TAMP_FLT(regval) (BITS(11,12) & ((uint32_t)(regval) << 11U)) /*!< write value to RTC_TAMP_FLT bit field */
|
||||
#define RTC_FLT_EDGE TAMP_FLT(0) /*!< detecting tamper event using edge mode. precharge duration is disabled automatically */
|
||||
#define RTC_FLT_2S TAMP_FLT(1) /*!< detecting tamper event using level mode.2 consecutive valid level samples will make a effective tamper event */
|
||||
#define RTC_FLT_4S TAMP_FLT(2) /*!< detecting tamper event using level mode.4 consecutive valid level samples will make an effective tamper event */
|
||||
#define RTC_FLT_8S TAMP_FLT(3) /*!< detecting tamper event using level mode.8 consecutive valid level samples will make a effective tamper event */
|
||||
|
||||
#define TAMP_PRCH(regval) (BITS(13,14) & ((uint32_t)(regval) << 13U)) /*!< write value to RTC_TAMP_PRCH bit field */
|
||||
#define RTC_PRCH_1C TAMP_PRCH(0) /*!< 1 RTC clock prechagre time before each sampling */
|
||||
#define RTC_PRCH_2C TAMP_PRCH(1) /*!< 2 RTC clock prechagre time before each sampling */
|
||||
#define RTC_PRCH_4C TAMP_PRCH(2) /*!< 4 RTC clock prechagre time before each sampling */
|
||||
#define RTC_PRCH_8C TAMP_PRCH(3) /*!< 8 RTC clock prechagre time before each sampling */
|
||||
|
||||
#define RTC_TAMPER0 RTC_TAMP_TP0EN /*!< tamper 0 detection enable */
|
||||
#define RTC_TAMPER1 RTC_TAMP_TP1EN /*!< tamper 1 detection enable */
|
||||
|
||||
#define RTC_TAMPER_TRIGGER_EDGE_RISING ((uint32_t)0x00000000U) /*!< tamper detection is in rising edge mode */
|
||||
#define RTC_TAMPER_TRIGGER_EDGE_FALLING ((uint32_t)0x00000001U) /*!< tamper detection is in falling edge mode */
|
||||
#define RTC_TAMPER_TRIGGER_LEVEL_LOW ((uint32_t)0x00000000U) /*!< tamper detection is in low level mode */
|
||||
#define RTC_TAMPER_TRIGGER_LEVEL_HIGH ((uint32_t)0x00000001U) /*!< tamper detection is in high level mode */
|
||||
|
||||
#define RTC_TAMPER_TRIGGER_POS ((uint32_t)0x00000001U) /* shift position of trigger relative to source */
|
||||
|
||||
#define RTC_ALARM_OUTPUT_OD ((uint32_t)0x00000000U) /*!< RTC alarm output open-drain mode */
|
||||
#define RTC_ALARM_OUTPUT_PP RTC_TAMP_PC13VAL /*!< RTC alarm output push-pull mode */
|
||||
|
||||
/* alrm0ss register value */
|
||||
#define ALRM0SS_SSC(regval) (BITS(0,14) & ((uint32_t)(regval)<< 0U)) /*!< write value to RTC_ALRM0SS_SSC bit field */
|
||||
|
||||
#define ALRM0SS_MASKSSC(regval) (BITS(24,27) & ((uint32_t)(regval) << 24U)) /*!< write value to RTC_ALRM0SS_MASKSSC bit field */
|
||||
#define RTC_MASKSSC_0_14 ALRM0SS_MASKSSC(0) /*!< mask alarm subsecond configuration */
|
||||
#define RTC_MASKSSC_1_14 ALRM0SS_MASKSSC(1) /*!< mask RTC_ALRM0SS_SSC[14:1], and RTC_ALRM0SS_SSC[0] is to be compared */
|
||||
#define RTC_MASKSSC_2_14 ALRM0SS_MASKSSC(2) /*!< mask RTC_ALRM0SS_SSC[14:2], and RTC_ALRM0SS_SSC[1:0] is to be compared */
|
||||
#define RTC_MASKSSC_3_14 ALRM0SS_MASKSSC(3) /*!< mask RTC_ALRM0SS_SSC[14:3], and RTC_ALRM0SS_SSC[2:0] is to be compared */
|
||||
#define RTC_MASKSSC_4_14 ALRM0SS_MASKSSC(4) /*!< mask RTC_ALRM0SS_SSC[14:4], and RTC_ALRM0SS_SSC[3:0] is to be compared */
|
||||
#define RTC_MASKSSC_5_14 ALRM0SS_MASKSSC(5) /*!< mask RTC_ALRM0SS_SSC[14:5], and RTC_ALRM0SS_SSC[4:0] is to be compared */
|
||||
#define RTC_MASKSSC_6_14 ALRM0SS_MASKSSC(6) /*!< mask RTC_ALRM0SS_SSC[14:6], and RTC_ALRM0SS_SSC[5:0] is to be compared */
|
||||
#define RTC_MASKSSC_7_14 ALRM0SS_MASKSSC(7) /*!< mask RTC_ALRM0SS_SSC[14:7], and RTC_ALRM0SS_SSC[6:0] is to be compared */
|
||||
#define RTC_MASKSSC_8_14 ALRM0SS_MASKSSC(8) /*!< mask RTC_ALRM0SS_SSC[14:8], and RTC_ALRM0SS_SSC[7:0] is to be compared */
|
||||
#define RTC_MASKSSC_9_14 ALRM0SS_MASKSSC(9) /*!< mask RTC_ALRM0SS_SSC[14:9], and RTC_ALRM0SS_SSC[8:0] is to be compared */
|
||||
#define RTC_MASKSSC_10_14 ALRM0SS_MASKSSC(10) /*!< mask RTC_ALRM0SS_SSC[14:10], and RTC_ALRM0SS_SSC[9:0] is to be compared */
|
||||
#define RTC_MASKSSC_11_14 ALRM0SS_MASKSSC(11) /*!< mask RTC_ALRM0SS_SSC[14:11], and RTC_ALRM0SS_SSC[10:0] is to be compared */
|
||||
#define RTC_MASKSSC_12_14 ALRM0SS_MASKSSC(12) /*!< mask RTC_ALRM0SS_SSC[14:12], and RTC_ALRM0SS_SSC[11:0] is to be compared */
|
||||
#define RTC_MASKSSC_13_14 ALRM0SS_MASKSSC(13) /*!< mask RTC_ALRM0SS_SSC[14:13], and RTC_ALRM0SS_SSC[12:0] is to be compared */
|
||||
#define RTC_MASKSSC_14 ALRM0SS_MASKSSC(14) /*!< mask RTC_ALRM0SS_SSC[14], and RTC_ALRM0SS_SSC[13:0] is to be compared */
|
||||
#define RTC_MASKSSC_NONE ALRM0SS_MASKSSC(15) /*!< mask none, and RTC_ALRM0SS_SSC[14:0] is to be compared */
|
||||
|
||||
/* RTC interrupt source */
|
||||
#define RTC_INT_TIMESTAMP RTC_CTL_TSIE /*!< time-stamp interrupt enable */
|
||||
#define RTC_INT_ALARM RTC_CTL_ALRM0IE /*!< RTC alarm interrupt enable */
|
||||
#define RTC_INT_TAMP RTC_TAMP_TPIE /*!< tamper detection interrupt enable */
|
||||
|
||||
/* write protect key */
|
||||
#define RTC_UNLOCK_KEY1 ((uint8_t)0xCAU) /*!< RTC unlock key1 */
|
||||
#define RTC_UNLOCK_KEY2 ((uint8_t)0x53U) /*!< RTC unlock key2 */
|
||||
#define RTC_LOCK_KEY ((uint8_t)0xFFU) /*!< RTC lock key */
|
||||
|
||||
/* registers reset value */
|
||||
#define RTC_REGISTER_RESET ((uint32_t)0x00000000U) /*!< RTC common register reset value */
|
||||
#define RTC_DATE_RESET ((uint32_t)0x00002101U) /*!< RTC_DATE register reset value */
|
||||
#define RTC_STAT_RESET ((uint32_t)0x00000007U) /*!< RTC_STAT register reset value */
|
||||
#define RTC_PSC_RESET ((uint32_t)0x007F00FFU) /*!< RTC_PSC register reset value */
|
||||
|
||||
/* RTC timeout value */
|
||||
#define RTC_INITM_TIMEOUT ((uint32_t)0x00004000U) /*!< initialization state flag timeout */
|
||||
#define RTC_RSYNF_TIMEOUT ((uint32_t)0x00008000U) /*!< register synchronization flag timeout */
|
||||
#define RTC_HRFC_TIMEOUT ((uint32_t)0x00001000U) /*!< recalibration pending flag timeout */
|
||||
#define RTC_SHIFTCTL_TIMEOUT ((uint32_t)0x00001000U) /*!< shift function operation pending flag timeout */
|
||||
#define RTC_ALRM0WF_TIMEOUT ((uint32_t)0x00008000U) /*!< alarm configuration can be write flag timeout */
|
||||
|
||||
/* RTC flag */
|
||||
#define RTC_FLAG_RECALIBRATION RTC_STAT_SCPF /*!< recalibration pending flag */
|
||||
#define RTC_FLAG_TAMP1 RTC_STAT_TP1F /*!< tamper 1 event flag */
|
||||
#define RTC_FLAG_TAMP0 RTC_STAT_TP0F /*!< tamper 0 event flag */
|
||||
#define RTC_FLAG_TIMESTAMP_OVERFLOW RTC_STAT_TSOVRF /*!< time-stamp overflow event flag */
|
||||
#define RTC_FLAG_TIMESTAMP RTC_STAT_TSF /*!< time-stamp event flag */
|
||||
#define RTC_FLAG_ALARM0 RTC_STAT_ALRM0F /*!< alarm event flag */
|
||||
#define RTC_FLAG_INIT RTC_STAT_INITF /*!< init mode event flag */
|
||||
#define RTC_FLAG_RSYN RTC_STAT_RSYNF /*!< registers synchronized flag */
|
||||
#define RTC_FLAG_YCM RTC_STAT_YCM /*!< year parameter configured event flag */
|
||||
#define RTC_FLAG_SHIFT RTC_STAT_SOPF /*!< shift operation pending flag */
|
||||
#define RTC_FLAG_ALARM0_WRITTEN RTC_STAT_ALRM0WF /*!< alarm written available flag */
|
||||
|
||||
/* function declarations */
|
||||
/* reset most of the RTC registers */
|
||||
ErrStatus rtc_deinit(void);
|
||||
/* initialize RTC registers */
|
||||
ErrStatus rtc_init(rtc_parameter_struct* rtc_initpara_struct);
|
||||
/* enter RTC init mode */
|
||||
ErrStatus rtc_init_mode_enter(void);
|
||||
/* exit RTC init mode */
|
||||
void rtc_init_mode_exit(void);
|
||||
/* wait until RTC_TIME and RTC_DATE registers are synchronized with APB clock, and the shadow registers are updated */
|
||||
ErrStatus rtc_register_sync_wait(void);
|
||||
|
||||
/* get current time and date */
|
||||
void rtc_current_time_get(rtc_parameter_struct* rtc_initpara_struct);
|
||||
/* get current subsecond value */
|
||||
uint32_t rtc_subsecond_get(void);
|
||||
|
||||
/* configure RTC alarm */
|
||||
void rtc_alarm_config(rtc_alarm_struct* rtc_alarm_time);
|
||||
/* configure subsecond of RTC alarm */
|
||||
void rtc_alarm_subsecond_config(uint32_t mask_subsecond, uint32_t subsecond);
|
||||
/* get RTC alarm */
|
||||
void rtc_alarm_get(rtc_alarm_struct* rtc_alarm_time);
|
||||
/* get RTC alarm subsecond */
|
||||
uint32_t rtc_alarm_subsecond_get(void);
|
||||
/* enable RTC alarm */
|
||||
void rtc_alarm_enable(void);
|
||||
/* disable RTC alarm */
|
||||
ErrStatus rtc_alarm_disable(void);
|
||||
|
||||
/* enable RTC time-stamp */
|
||||
void rtc_timestamp_enable(uint32_t edge);
|
||||
/* disable RTC time-stamp */
|
||||
void rtc_timestamp_disable(void);
|
||||
/* get RTC timestamp time and date */
|
||||
void rtc_timestamp_get(rtc_timestamp_struct* rtc_timestamp);
|
||||
/* get RTC time-stamp subsecond */
|
||||
uint32_t rtc_timestamp_subsecond_get(void);
|
||||
|
||||
/* enable RTC tamper */
|
||||
void rtc_tamper_enable(rtc_tamper_struct* rtc_tamper);
|
||||
/* disable RTC tamper */
|
||||
void rtc_tamper_disable(uint32_t source);
|
||||
|
||||
/* enable specified RTC interrupt */
|
||||
void rtc_interrupt_enable(uint32_t interrupt);
|
||||
/* disble specified RTC interrupt */
|
||||
void rtc_interrupt_disable(uint32_t interrupt);
|
||||
/* check specified flag */
|
||||
FlagStatus rtc_flag_get(uint32_t flag);
|
||||
/* clear specified flag */
|
||||
void rtc_flag_clear(uint32_t flag);
|
||||
/* configure RTC alternate output source */
|
||||
void rtc_alter_output_config(uint32_t source, uint32_t mode);
|
||||
|
||||
/* configure RTC calibration register */
|
||||
ErrStatus rtc_calibration_config(uint32_t window, uint32_t plus, uint32_t minus);
|
||||
/* ajust the daylight saving time by adding or substracting one hour from the current time */
|
||||
void rtc_hour_adjust(uint32_t operation);
|
||||
/* ajust RTC second or subsecond value of current time */
|
||||
ErrStatus rtc_second_adjust(uint32_t add, uint32_t minus);
|
||||
/* enable RTC bypass shadow registers function */
|
||||
void rtc_bypass_shadow_enable(void);
|
||||
/* disable RTC bypass shadow registers function */
|
||||
void rtc_bypass_shadow_disable(void);
|
||||
/* enable RTC reference clock detection function */
|
||||
ErrStatus rtc_refclock_detection_enable(void);
|
||||
/* disable RTC reference clock detection function */
|
||||
ErrStatus rtc_refclock_detection_disable(void);
|
||||
|
||||
#endif /* GD32E23X_RTC_H */
|
||||
@@ -0,0 +1,423 @@
|
||||
/*!
|
||||
\file gd32e23x_spi.h
|
||||
\brief definitions for the SPI
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_SPI_H
|
||||
#define GD32E23X_SPI_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* SPIx(x=0,1) definitions */
|
||||
#define SPI0 (SPI_BASE + 0x0000F800U)
|
||||
#define SPI1 SPI_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define SPI_CTL0(spix) REG32((spix) + 0x00000000U) /*!< SPI control register 0 */
|
||||
#define SPI_CTL1(spix) REG32((spix) + 0x00000004U) /*!< SPI control register 1*/
|
||||
#define SPI_STAT(spix) REG32((spix) + 0x00000008U) /*!< SPI status register */
|
||||
#define SPI_DATA(spix) REG32((spix) + 0x0000000CU) /*!< SPI data register */
|
||||
#define SPI_CRCPOLY(spix) REG32((spix) + 0x00000010U) /*!< SPI CRC polynomial register */
|
||||
#define SPI_RCRC(spix) REG32((spix) + 0x00000014U) /*!< SPI receive CRC register */
|
||||
#define SPI_TCRC(spix) REG32((spix) + 0x00000018U) /*!< SPI transmit CRC register */
|
||||
#define SPI_I2SCTL(spix) REG32((spix) + 0x0000001CU) /*!< SPI I2S control register */
|
||||
#define SPI_I2SPSC(spix) REG32((spix) + 0x00000020U) /*!< SPI I2S clock prescaler register */
|
||||
#define SPI_QCTL(spix) REG32((spix) + 0x00000080U) /*!< SPI quad mode control register(only available in SPI1) */
|
||||
|
||||
/* bits definitions */
|
||||
/* SPI_CTL0 */
|
||||
#define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection */
|
||||
#define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */
|
||||
#define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */
|
||||
#define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */
|
||||
#define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/
|
||||
#define SPI_CTL0_LF BIT(7) /*!< LSB first mode */
|
||||
#define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */
|
||||
#define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */
|
||||
#define SPI_CTL0_RO BIT(10) /*!< receive only */
|
||||
/* only available in SPI0*/
|
||||
#define SPI_CTL0_FF16 BIT(11) /*!< data frame size */
|
||||
/* only available in SPI1*/
|
||||
#define SPI_CTL0_CRCL BIT(11) /*!< CRC length */
|
||||
#define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */
|
||||
#define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */
|
||||
#define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/
|
||||
#define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */
|
||||
|
||||
/* SPI_CTL1 */
|
||||
#define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer DMA enable */
|
||||
#define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer DMA enable */
|
||||
#define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */
|
||||
#define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */
|
||||
#define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */
|
||||
#define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */
|
||||
#define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */
|
||||
#define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */
|
||||
/* only available in SPI1 */
|
||||
#define SPI_CTL1_DZ BITS(8,11) /*!< data size */
|
||||
#define SPI_CTL1_BYTEN BIT(12) /*!< byte access to FIFO enable */
|
||||
#define SPI_CTL1_RXDMA_ODD BIT(13) /*!< odd bytes in RX DMA channel */
|
||||
#define SPI_CTL1_TXDMA_ODD BIT(14) /*!< odd bytes in TX DMA channel */
|
||||
|
||||
/* SPI_STAT */
|
||||
#define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */
|
||||
#define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */
|
||||
#define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */
|
||||
#define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */
|
||||
#define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */
|
||||
#define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */
|
||||
#define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */
|
||||
#define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */
|
||||
#define SPI_STAT_FERR BIT(8) /*!< format error bit */
|
||||
/* only available in SPI1 */
|
||||
#define SPI_STAT_RXLVL BITS(9,10) /*!< RXFIFO level */
|
||||
#define SPI_STAT_TXLVL BITS(11,12) /*!< TXFIFO level */
|
||||
|
||||
/* SPI_DATA */
|
||||
#define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */
|
||||
|
||||
/* SPI_CRCPOLY */
|
||||
#define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */
|
||||
|
||||
/* SPI_RCRC */
|
||||
#define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */
|
||||
|
||||
/* SPI_TCRC */
|
||||
#define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */
|
||||
|
||||
/* SPI_I2SCTL */
|
||||
#define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */
|
||||
#define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */
|
||||
#define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */
|
||||
#define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */
|
||||
#define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */
|
||||
#define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */
|
||||
#define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */
|
||||
#define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */
|
||||
|
||||
/* SPI_I2SPSC */
|
||||
#define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */
|
||||
#define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */
|
||||
#define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */
|
||||
|
||||
/* SPI_QCTL(only available in SPI1) */
|
||||
#define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */
|
||||
#define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */
|
||||
#define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */
|
||||
|
||||
/* constants definitions */
|
||||
/* SPI and I2S parameter struct definitions */
|
||||
typedef struct {
|
||||
uint32_t device_mode; /*!< SPI master or slave */
|
||||
uint32_t trans_mode; /*!< SPI transfer type */
|
||||
uint32_t frame_size; /*!< SPI frame size */
|
||||
uint32_t nss; /*!< SPI NSS control by handware or software */
|
||||
uint32_t endian; /*!< SPI big endian or little endian */
|
||||
uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */
|
||||
uint32_t prescale; /*!< SPI prescaler factor */
|
||||
} spi_parameter_struct;
|
||||
|
||||
/* SPI mode definitions */
|
||||
#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */
|
||||
#define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */
|
||||
|
||||
/* SPI bidirectional transfer direction */
|
||||
#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */
|
||||
#define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */
|
||||
|
||||
/* SPI transmit type */
|
||||
#define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */
|
||||
#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */
|
||||
#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */
|
||||
#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/
|
||||
|
||||
/* SPI NSS control mode */
|
||||
#define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */
|
||||
#define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */
|
||||
|
||||
/* SPI transmit way */
|
||||
#define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */
|
||||
#define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */
|
||||
|
||||
/* SPI clock phase and polarity */
|
||||
#define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */
|
||||
#define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */
|
||||
#define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */
|
||||
#define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */
|
||||
|
||||
/* SPI clock prescaler factor */
|
||||
#define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
|
||||
#define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescaler factor is 2 */
|
||||
#define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescaler factor is 4 */
|
||||
#define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescaler factor is 8 */
|
||||
#define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescaler factor is 16 */
|
||||
#define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescaler factor is 32 */
|
||||
#define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescaler factor is 64 */
|
||||
#define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescaler factor is 128 */
|
||||
#define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescaler factor is 256 */
|
||||
|
||||
/* SPIx frame size */
|
||||
#define CTL1_FRAMESIZE(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
|
||||
#define SPI_FRAMESIZE_4BIT CTL1_FRAMESIZE(3) /*!< SPI frame size is 4 bits */
|
||||
#define SPI_FRAMESIZE_5BIT CTL1_FRAMESIZE(4) /*!< SPI frame size is 5 bits */
|
||||
#define SPI_FRAMESIZE_6BIT CTL1_FRAMESIZE(5) /*!< SPI frame size is 6 bits */
|
||||
#define SPI_FRAMESIZE_7BIT CTL1_FRAMESIZE(6) /*!< SPI frame size is 7 bits */
|
||||
#define SPI_FRAMESIZE_8BIT CTL1_FRAMESIZE(7) /*!< SPI frame size is 8 bits */
|
||||
#define SPI_FRAMESIZE_9BIT CTL1_FRAMESIZE(8) /*!< SPI frame size is 9 bits */
|
||||
#define SPI_FRAMESIZE_10BIT CTL1_FRAMESIZE(9) /*!< SPI frame size is 10 bits */
|
||||
#define SPI_FRAMESIZE_11BIT CTL1_FRAMESIZE(10) /*!< SPI frame size is 11 bits */
|
||||
#define SPI_FRAMESIZE_12BIT CTL1_FRAMESIZE(11) /*!< SPI frame size is 12 bits */
|
||||
#define SPI_FRAMESIZE_13BIT CTL1_FRAMESIZE(12) /*!< SPI frame size is 13 bits */
|
||||
#define SPI_FRAMESIZE_14BIT CTL1_FRAMESIZE(13) /*!< SPI frame size is 14 bits */
|
||||
#define SPI_FRAMESIZE_15BIT CTL1_FRAMESIZE(14) /*!< SPI frame size is 15 bits */
|
||||
#define SPI_FRAMESIZE_16BIT CTL1_FRAMESIZE(15) /*!< SPI frame size is 16 bits */
|
||||
|
||||
/* SPIx CRC length(x=1) */
|
||||
#define SPI_CRC_8BIT ((uint32_t)0x00000000U) /*!< SPI CRC length is 8 bits */
|
||||
#define SPI_CRC_16BIT SPI_CTL0_CRCL /*!< SPI CRC length is 16 bits */
|
||||
|
||||
/* SPIx byte access enable(x=1) */
|
||||
#define SPI_HALFWORD_ACCESS ((uint32_t)0x00000000U) /*!< SPI half-word access to FIFO */
|
||||
#define SPI_BYTE_ACCESS SPI_CTL1_BYTEN /*!< SPI byte access to FIFO */
|
||||
|
||||
/* SPIx odd bytes in TX DMA channel(x=1) */
|
||||
#define SPI_TXDMA_EVEN ((uint32_t)0x00000000U) /*!< SPI number of byte in TX DMA channel is even */
|
||||
#define SPI_TXDMA_ODD SPI_CTL1_TXDMA_ODD /*!< SPI number of byte in TX DMA channel is odd */
|
||||
|
||||
/* SPIx odd bytes in RX DMA channel(x=1) */
|
||||
#define SPI_RXDMA_EVEN ((uint32_t)0x00000000U) /*!< SPI number of byte in RX DMA channel is even */
|
||||
#define SPI_RXDMA_ODD SPI_CTL1_RXDMA_ODD /*!< SPI number of byte in RX DMA channel is odd */
|
||||
|
||||
/* SPIx TXFIFO level(x=1) */
|
||||
#define CTL1_TXLVL(regval) (BITS(11,12) & ((uint32_t)(regval) << 11))
|
||||
#define SPI_TXLVL_EMPTY CTL1_TXLVL(0) /*!< SPI TXFIFO is empty */
|
||||
#define SPI_TXLVL_QUARTER_FULL CTL1_TXLVL(1) /*!< SPI TXFIFO is a quarter of full */
|
||||
#define SPI_TXLVL_HAlF_FULL CTL1_TXLVL(2) /*!< SPI TXFIFO is a half of full */
|
||||
#define SPI_TXLVL_FULL CTL1_TXLVL(3) /*!< SPI TXFIFO is full */
|
||||
|
||||
/* SPIx RXFIFO level(x=1) */
|
||||
#define CTL1_RXLVL(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
|
||||
#define SPI_RXLVL_EMPTY CTL1_RXLVL(0) /*!< SPI RXFIFO is empty */
|
||||
#define SPI_RXLVL_QUARTER_FULL CTL1_RXLVL(1) /*!< SPI RXFIFO is a quarter of full */
|
||||
#define SPI_RXLVL_HAlF_FULL CTL1_RXLVL(2) /*!< SPI RXFIFO is a half of full */
|
||||
#define SPI_RXLVL_FULL CTL1_RXLVL(3) /*!< SPI RXFIFO is full */
|
||||
|
||||
/* I2S audio sample rate */
|
||||
#define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */
|
||||
#define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */
|
||||
#define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */
|
||||
#define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */
|
||||
#define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */
|
||||
#define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */
|
||||
#define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */
|
||||
#define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */
|
||||
#define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */
|
||||
|
||||
/* I2S frame format */
|
||||
#define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1))
|
||||
#define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */
|
||||
#define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */
|
||||
#define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */
|
||||
#define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */
|
||||
|
||||
/* I2S master clock output */
|
||||
#define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */
|
||||
#define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */
|
||||
|
||||
/* I2S operation mode */
|
||||
#define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8))
|
||||
#define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */
|
||||
#define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */
|
||||
#define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */
|
||||
#define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */
|
||||
|
||||
/* I2S standard */
|
||||
#define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */
|
||||
#define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */
|
||||
#define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */
|
||||
#define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */
|
||||
#define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */
|
||||
|
||||
/* I2S clock polarity */
|
||||
#define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */
|
||||
#define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */
|
||||
|
||||
/* SPI DMA constants definitions */
|
||||
#define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */
|
||||
#define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */
|
||||
|
||||
/* SPI CRC constants definitions */
|
||||
#define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */
|
||||
#define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */
|
||||
|
||||
/* SPI/I2S interrupt enable/disable constants definitions */
|
||||
#define SPI_I2S_INT_TBE SPI_CTL1_TBEIE /*!< transmit buffer empty interrupt */
|
||||
#define SPI_I2S_INT_RBNE SPI_CTL1_RBNEIE /*!< receive buffer not empty interrupt */
|
||||
#define SPI_I2S_INT_ERR SPI_CTL1_ERRIE /*!< error interrupt */
|
||||
|
||||
/* SPI/I2S interrupt flag constants definitions */
|
||||
#define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */
|
||||
#define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */
|
||||
#define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */
|
||||
#define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */
|
||||
#define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */
|
||||
|
||||
/* SPI/I2S flag definitions */
|
||||
#define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
|
||||
#define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
|
||||
#define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */
|
||||
#define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */
|
||||
#define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */
|
||||
#define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
|
||||
#define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error flag */
|
||||
#define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */
|
||||
#define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */
|
||||
#define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */
|
||||
#define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */
|
||||
#define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */
|
||||
#define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */
|
||||
#define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error flag */
|
||||
|
||||
/* function declarations */
|
||||
/* SPI deinitialization and initialization functions */
|
||||
/* reset SPI and I2S */
|
||||
void spi_i2s_deinit(uint32_t spi_periph);
|
||||
/* initialize the parameters of SPI structure with the default values */
|
||||
void spi_struct_para_init(spi_parameter_struct *spi_struct);
|
||||
/* initialize SPI parameters */
|
||||
ErrStatus spi_init(uint32_t spi_periph, spi_parameter_struct *spi_struct);
|
||||
/* enable SPI */
|
||||
void spi_enable(uint32_t spi_periph);
|
||||
/* disable SPI */
|
||||
void spi_disable(uint32_t spi_periph);
|
||||
|
||||
/* I2S initialization functions */
|
||||
/* initialize I2S parameters */
|
||||
void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl);
|
||||
/* configure I2S prescaler */
|
||||
void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout);
|
||||
/* enable I2S */
|
||||
void i2s_enable(uint32_t spi_periph);
|
||||
/* disable I2S */
|
||||
void i2s_disable(uint32_t spi_periph);
|
||||
|
||||
/* NSS functions */
|
||||
/* enable SPI NSS output */
|
||||
void spi_nss_output_enable(uint32_t spi_periph);
|
||||
/* disable SPI NSS output */
|
||||
void spi_nss_output_disable(uint32_t spi_periph);
|
||||
/* SPI NSS pin high level in software mode */
|
||||
void spi_nss_internal_high(uint32_t spi_periph);
|
||||
/* SPI NSS pin low level in software mode */
|
||||
void spi_nss_internal_low(uint32_t spi_periph);
|
||||
|
||||
/* DMA functions */
|
||||
/* enable SPI DMA */
|
||||
void spi_dma_enable(uint32_t spi_periph, uint8_t dma);
|
||||
/* disable SPI DMA */
|
||||
void spi_dma_disable(uint32_t spi_periph, uint8_t dma);
|
||||
/* configure SPI total number of data to be transmitted by DMA is odd or not */
|
||||
void spi_transmit_odd_config(uint32_t spi_periph, uint16_t odd);
|
||||
/* configure SPI total number of data to be received by DMA is odd or not */
|
||||
void spi_receive_odd_config(uint32_t spi_periph, uint16_t odd);
|
||||
|
||||
/* communication functions */
|
||||
/* configure SPI data frame format */
|
||||
ErrStatus spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format);
|
||||
/* configure SPI access size to FIFO(8-bit or 16-bit) */
|
||||
void spi_fifo_access_size_config(uint32_t spi_periph, uint16_t fifo_access_size);
|
||||
/* configure SPI bidirectional transfer direction */
|
||||
void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction);
|
||||
/* SPI transmit data */
|
||||
void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data);
|
||||
/* SPI receive data */
|
||||
uint16_t spi_i2s_data_receive(uint32_t spi_periph);
|
||||
|
||||
/* SPI CRC functions */
|
||||
/* set SPI CRC polynomial */
|
||||
void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly);
|
||||
/* get SPI CRC polynomial */
|
||||
uint16_t spi_crc_polynomial_get(uint32_t spi_periph);
|
||||
/* set CRC length */
|
||||
void spi_crc_length_set(uint32_t spi_periph, uint16_t crc_length);
|
||||
/* turn on SPI CRC function */
|
||||
void spi_crc_on(uint32_t spi_periph);
|
||||
/* turn off SPI CRC function */
|
||||
void spi_crc_off(uint32_t spi_periph);
|
||||
/* SPI next data is CRC value */
|
||||
void spi_crc_next(uint32_t spi_periph);
|
||||
/* get SPI CRC send value or receive value */
|
||||
uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc);
|
||||
|
||||
/* SPI TI mode functions */
|
||||
/* enable SPI TI mode */
|
||||
void spi_ti_mode_enable(uint32_t spi_periph);
|
||||
/* disable SPI TI mode */
|
||||
void spi_ti_mode_disable(uint32_t spi_periph);
|
||||
|
||||
/* SPI NSS pulse mode functions */
|
||||
/* enable SPI NSS pulse mode */
|
||||
void spi_nssp_mode_enable(uint32_t spi_periph);
|
||||
/* disable SPI NSS pulse mode */
|
||||
void spi_nssp_mode_disable(uint32_t spi_periph);
|
||||
|
||||
/* quad wire SPI functions */
|
||||
/* enable quad wire SPI */
|
||||
void spi_quad_enable(uint32_t spi_periph);
|
||||
/* disable quad wire SPI */
|
||||
void spi_quad_disable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI write */
|
||||
void spi_quad_write_enable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI read */
|
||||
void spi_quad_read_enable(uint32_t spi_periph);
|
||||
/* enable quad wire SPI_IO2 and SPI_IO3 pin output */
|
||||
void spi_quad_io23_output_enable(uint32_t spi_periph);
|
||||
/* disable quad wire SPI_IO2 and SPI_IO3 pin output */
|
||||
void spi_quad_io23_output_disable(uint32_t spi_periph);
|
||||
|
||||
/* flag and interrupt functions */
|
||||
/* get SPI and I2S flag status */
|
||||
FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag);
|
||||
/* enable SPI and I2S interrupt */
|
||||
void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* disable SPI and I2S interrupt */
|
||||
void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* get SPI and I2S interrupt status */
|
||||
FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt);
|
||||
/* clear SPI CRC error flag status */
|
||||
void spi_crc_error_clear(uint32_t spi_periph);
|
||||
|
||||
#endif /* GD32E23X_SPI_H */
|
||||
@@ -0,0 +1,192 @@
|
||||
/*!
|
||||
\file GD32e23x_syscfg.h
|
||||
\brief definitions for the SYSCFG
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_SYSCFG_H
|
||||
#define GD32E23X_SYSCFG_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* SYSCFG definitions */
|
||||
#define SYSCFG SYSCFG_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define SYSCFG_CFG0 REG32(SYSCFG + 0x00U) /*!< system configuration register 0 */
|
||||
#define SYSCFG_EXTISS0 REG32(SYSCFG + 0x08U) /*!< EXTI sources selection register 0 */
|
||||
#define SYSCFG_EXTISS1 REG32(SYSCFG + 0x0CU) /*!< EXTI sources selection register 1 */
|
||||
#define SYSCFG_EXTISS2 REG32(SYSCFG + 0x10U) /*!< EXTI sources selection register 2 */
|
||||
#define SYSCFG_EXTISS3 REG32(SYSCFG + 0x14U) /*!< EXTI sources selection register 3 */
|
||||
#define SYSCFG_CFG2 REG32(SYSCFG + 0x18U) /*!< system configuration register 2 */
|
||||
#define SYSCFG_CPU_IRQ_LAT REG32(SYSCFG + 0x100U) /*!< IRQ Latency register */
|
||||
|
||||
/* SYSCFG_CFG0 bits definitions */
|
||||
#define SYSCFG_CFG0_BOOT_MODE BITS(0,1) /*!< SYSCFG memory remap config */
|
||||
#define SYSCFG_CFG0_PA11_PA12_RMP BIT(4) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins) */
|
||||
#define SYSCFG_CFG0_ADC_DMA_RMP BIT(8) /*!< ADC DMA remap config */
|
||||
#define SYSCFG_CFG0_USART0_TX_DMA_RMP BIT(9) /*!< USART0 Tx DMA remap config */
|
||||
#define SYSCFG_CFG0_USART0_RX_DMA_RMP BIT(10) /*!< USART0 Rx DMA remap config */
|
||||
#define SYSCFG_CFG0_TIMER15_DMA_RMP BIT(11) /*!< TIMER 15 DMA remap config */
|
||||
#define SYSCFG_CFG0_TIMER16_DMA_RMP BIT(12) /*!< TIMER 16 DMA remap config */
|
||||
#if defined(GD32E230)
|
||||
#define SYSCFG_CFG0_PB9_HCCE BIT(19) /*!< PB9 pin high current capability enable */
|
||||
#endif
|
||||
|
||||
/* SYSCFG_EXTISS0 bits definitions */
|
||||
#define SYSCFG_EXTISS0_EXTI0_SS BITS(0,3) /*!< EXTI 0 configuration */
|
||||
#define SYSCFG_EXTISS0_EXTI1_SS BITS(4,7) /*!< EXTI 1 configuration */
|
||||
#define SYSCFG_EXTISS0_EXTI2_SS BITS(8,11) /*!< EXTI 2 configuration */
|
||||
#define SYSCFG_EXTISS0_EXTI3_SS BITS(12,15) /*!< EXTI 3 configuration */
|
||||
|
||||
/* SYSCFG_EXTISS1 bits definitions */
|
||||
#define SYSCFG_EXTISS1_EXTI4_SS BITS(0,3) /*!< EXTI 4 configuration */
|
||||
#define SYSCFG_EXTISS1_EXTI5_SS BITS(4,7) /*!< EXTI 5 configuration */
|
||||
#define SYSCFG_EXTISS1_EXTI6_SS BITS(8,11) /*!< EXTI 6 configuration */
|
||||
#define SYSCFG_EXTISS1_EXTI7_SS BITS(12,15) /*!< EXTI 7 configuration */
|
||||
|
||||
/* SYSCFG_EXTISS2 bits definitions */
|
||||
#define SYSCFG_EXTISS2_EXTI8_SS BITS(0,3) /*!< EXTI 8 configuration */
|
||||
#define SYSCFG_EXTISS2_EXTI9_SS BITS(4,7) /*!< EXTI 9 configuration */
|
||||
#define SYSCFG_EXTISS2_EXTI10_SS BITS(8,11) /*!< EXTI 10 configuration */
|
||||
#define SYSCFG_EXTISS2_EXTI11_SS BITS(12,15) /*!< EXTI 11 configuration */
|
||||
|
||||
/* SYSCFG_EXTISS3 bits definitions */
|
||||
#define SYSCFG_EXTISS3_EXTI12_SS BITS(0,3) /*!< EXTI 12 configuration */
|
||||
#define SYSCFG_EXTISS3_EXTI13_SS BITS(4,7) /*!< EXTI 13 configuration */
|
||||
#define SYSCFG_EXTISS3_EXTI14_SS BITS(8,11) /*!< EXTI 14 configuration */
|
||||
#define SYSCFG_EXTISS3_EXTI15_SS BITS(12,15) /*!< EXTI 15 configuration */
|
||||
|
||||
/* SYSCFG_CFG2 bits definitions */
|
||||
#define SYSCFG_CFG2_LOCKUP_LOCK BIT(0) /*!< enable and lock the LOCKUP (Hardfault) output of Cortex-M23 with break input of TIMER0/14/15/16 */
|
||||
#define SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK BIT(1) /*!< enable and lock the SRAM_PARITY error signal with break input of TIMER0/14/15/16 */
|
||||
#define SYSCFG_CFG2_LVD_LOCK BIT(2) /*!< enable and lock the LVD connection with TIMER0 break input and also the LVD_EN and LVDSEL[2:0] bits of the power control interface */
|
||||
#define SYSCFG_CFG2_SRAM_PCEF BIT(8) /*!< SRAM parity check error flag */
|
||||
|
||||
/* SYSCFG_CPU_IRQ_LAT bits definitions */
|
||||
#define SYSCFG_CPU_IRQ_LAT_IRQ_LATENCY BITS(0,7) /*!< IRQ_LATENCY specifies the minimum number of cycles between an interrupt */
|
||||
|
||||
/* constants definitions */
|
||||
/* DMA remap definitions */
|
||||
#define SYSCFG_PA11_REMAP_PA12 SYSCFG_CFG0_PA11_PA12_RMP /*!< PA11 PA12 remap */
|
||||
#define SYSCFG_DMA_REMAP_ADC SYSCFG_CFG0_ADC_DMA_RMP /*!< ADC DMA remap */
|
||||
#define SYSCFG_DMA_REMAP_USART0TX SYSCFG_CFG0_USART0_TX_DMA_RMP /*!< USART0_TX DMA remap */
|
||||
#define SYSCFG_DMA_REMAP_USART0RX SYSCFG_CFG0_USART0_RX_DMA_RMP /*!< USART0_RX DMA remap */
|
||||
#define SYSCFG_DMA_REMAP_TIMER15 SYSCFG_CFG0_TIMER15_DMA_RMP /*!< TIMER15 DMA remap */
|
||||
#define SYSCFG_DMA_REMAP_TIMER16 SYSCFG_CFG0_TIMER16_DMA_RMP /*!< TIMER16 DMA remap */
|
||||
|
||||
#if defined(GD32E230)
|
||||
/* high current definitions */
|
||||
#define SYSCFG_HIGH_CURRENT_ENABLE SYSCFG_CFG0_PB9_HCCE /*!< high current enable */
|
||||
#define SYSCFG_HIGH_CURRENT_DISABLE (~SYSCFG_CFG0_PB9_HCCE) /*!< high current disable */
|
||||
#endif
|
||||
|
||||
/* EXTI source select definition */
|
||||
#define EXTISS0 ((uint8_t)0x00U) /*!< EXTI source select register 0 */
|
||||
#define EXTISS1 ((uint8_t)0x01U) /*!< EXTI source select register 1 */
|
||||
#define EXTISS2 ((uint8_t)0x02U) /*!< EXTI source select register 2 */
|
||||
#define EXTISS3 ((uint8_t)0x03U) /*!< EXTI source select register 3 */
|
||||
|
||||
/* EXTI source select mask bits definition */
|
||||
#define EXTI_SS_MASK BITS(0,3) /*!< EXTI source select mask */
|
||||
|
||||
/* EXTI source select jumping step definition */
|
||||
#define EXTI_SS_JSTEP ((uint8_t)(0x04U)) /*!< EXTI source select jumping step */
|
||||
|
||||
/* EXTI source select moving step definition */
|
||||
#define EXTI_SS_MSTEP(pin) (EXTI_SS_JSTEP * ((pin) % EXTI_SS_JSTEP)) /*!< EXTI source select moving step */
|
||||
|
||||
/* EXTI source port definitions */
|
||||
#define EXTI_SOURCE_GPIOA ((uint8_t)0x00U) /*!< EXTI GPIOA configuration */
|
||||
#define EXTI_SOURCE_GPIOB ((uint8_t)0x01U) /*!< EXTI GPIOB configuration */
|
||||
#define EXTI_SOURCE_GPIOC ((uint8_t)0x02U) /*!< EXTI GPIOC configuration */
|
||||
#define EXTI_SOURCE_GPIOF ((uint8_t)0x05U) /*!< EXTI GPIOF configuration */
|
||||
|
||||
/* EXTI source pin definitions */
|
||||
#define EXTI_SOURCE_PIN0 ((uint8_t)0x00U) /*!< EXTI GPIO pin0 configuration */
|
||||
#define EXTI_SOURCE_PIN1 ((uint8_t)0x01U) /*!< EXTI GPIO pin1 configuration */
|
||||
#define EXTI_SOURCE_PIN2 ((uint8_t)0x02U) /*!< EXTI GPIO pin2 configuration */
|
||||
#define EXTI_SOURCE_PIN3 ((uint8_t)0x03U) /*!< EXTI GPIO pin3 configuration */
|
||||
#define EXTI_SOURCE_PIN4 ((uint8_t)0x04U) /*!< EXTI GPIO pin4 configuration */
|
||||
#define EXTI_SOURCE_PIN5 ((uint8_t)0x05U) /*!< EXTI GPIO pin5 configuration */
|
||||
#define EXTI_SOURCE_PIN6 ((uint8_t)0x06U) /*!< EXTI GPIO pin6 configuration */
|
||||
#define EXTI_SOURCE_PIN7 ((uint8_t)0x07U) /*!< EXTI GPIO pin7 configuration */
|
||||
#define EXTI_SOURCE_PIN8 ((uint8_t)0x08U) /*!< EXTI GPIO pin8 configuration */
|
||||
#define EXTI_SOURCE_PIN9 ((uint8_t)0x09U) /*!< EXTI GPIO pin9 configuration */
|
||||
#define EXTI_SOURCE_PIN10 ((uint8_t)0x0AU) /*!< EXTI GPIO pin10 configuration */
|
||||
#define EXTI_SOURCE_PIN11 ((uint8_t)0x0BU) /*!< EXTI GPIO pin11 configuration */
|
||||
#define EXTI_SOURCE_PIN12 ((uint8_t)0x0CU) /*!< EXTI GPIO pin12 configuration */
|
||||
#define EXTI_SOURCE_PIN13 ((uint8_t)0x0DU) /*!< EXTI GPIO pin13 configuration */
|
||||
#define EXTI_SOURCE_PIN14 ((uint8_t)0x0EU) /*!< EXTI GPIO pin14 configuration */
|
||||
#define EXTI_SOURCE_PIN15 ((uint8_t)0x0FU) /*!< EXTI GPIO pin15 configuration */
|
||||
|
||||
/* lock definitions */
|
||||
#define SYSCFG_LOCK_LOCKUP SYSCFG_CFG2_LOCKUP_LOCK /*!< LOCKUP output lock */
|
||||
#define SYSCFG_LOCK_SRAM_PARITY_ERROR SYSCFG_CFG2_SRAM_PARITY_ERROR_LOCK /*!< SRAM parity error lock */
|
||||
#define SYSCFG_LOCK_LVD SYSCFG_CFG2_LVD_LOCK /*!< LVD lock */
|
||||
|
||||
/* SRAM parity check error flag definitions */
|
||||
#define SYSCFG_SRAM_PCEF SYSCFG_CFG2_SRAM_PCEF /*!< SRAM parity check error flag */
|
||||
|
||||
/* SYSCFG_CPU_IRQ_LAT register IRQ_LATENCY value */
|
||||
#define IRQ_LATENCY(regval) (BITS(0,7) & ((uint32_t)(regval) << 0U)) /*!< write value to IRQ_LATENCY bits field */
|
||||
|
||||
/* function declarations */
|
||||
/* deinit syscfg module */
|
||||
void syscfg_deinit(void);
|
||||
|
||||
/* enable the DMA channels remapping */
|
||||
void syscfg_dma_remap_enable(uint32_t syscfg_dma_remap);
|
||||
/* disable the DMA channels remapping */
|
||||
void syscfg_dma_remap_disable(uint32_t syscfg_dma_remap);
|
||||
|
||||
#if defined(GD32E230)
|
||||
/* enable PB9 high current capability */
|
||||
void syscfg_high_current_enable(void);
|
||||
/* disable PB9 high current capability */
|
||||
void syscfg_high_current_disable(void);
|
||||
#endif
|
||||
|
||||
/* configure the GPIO pin as EXTI Line */
|
||||
void syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin);
|
||||
/* connect TIMER0/14/15/16 break input to the selected parameter */
|
||||
void syscfg_lock_config(uint32_t syscfg_lock);
|
||||
|
||||
/* set the IRQ_LATENCY value */
|
||||
void irq_latency_set(uint8_t irq_latency);
|
||||
|
||||
/* check if the specified flag in SYSCFG_CFG2 is set or not */
|
||||
FlagStatus syscfg_flag_get(uint32_t syscfg_flag);
|
||||
/* clear the flag in SYSCFG_CFG2 by writing 1 */
|
||||
void syscfg_flag_clear(uint32_t syscfg_flag);
|
||||
|
||||
#endif /* GD32E23X_SYSCFG_H */
|
||||
@@ -0,0 +1,759 @@
|
||||
/*!
|
||||
\file gd32e23x_timer.h
|
||||
\brief definitions for the TIMER
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_TIMER_H
|
||||
#define GD32E23X_TIMER_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* TIMERx(x=0,1,2,5,13..16) definitions */
|
||||
#define TIMER0 (TIMER_BASE + 0x00012C00U)
|
||||
#define TIMER2 (TIMER_BASE + 0x00000400U)
|
||||
#define TIMER5 (TIMER_BASE + 0x00001000U)
|
||||
#define TIMER13 (TIMER_BASE + 0x00002000U)
|
||||
#define TIMER14 (TIMER_BASE + 0x00014000U)
|
||||
#define TIMER15 (TIMER_BASE + 0x00014400U)
|
||||
#define TIMER16 (TIMER_BASE + 0x00014800U)
|
||||
|
||||
/* registers definitions */
|
||||
#define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */
|
||||
#define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */
|
||||
#define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */
|
||||
#define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */
|
||||
#define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */
|
||||
#define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */
|
||||
#define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */
|
||||
#define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */
|
||||
#define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */
|
||||
#define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */
|
||||
#define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */
|
||||
#define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */
|
||||
#define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */
|
||||
#define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */
|
||||
#define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */
|
||||
#define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */
|
||||
#define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */
|
||||
#define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER complementary channel protection register */
|
||||
#define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */
|
||||
#define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */
|
||||
#define TIMER_IRMP(timerx) REG32((timerx) + 0x50U) /*!< TIMER channel input remap register */
|
||||
#define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration register */
|
||||
|
||||
/* bits definitions */
|
||||
/* TIMER_CTL0 */
|
||||
#define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */
|
||||
#define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */
|
||||
#define TIMER_CTL0_UPS BIT(2) /*!< update source */
|
||||
#define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */
|
||||
#define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */
|
||||
#define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */
|
||||
#define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */
|
||||
#define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */
|
||||
|
||||
/* TIMER_CTL1 */
|
||||
#define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */
|
||||
#define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */
|
||||
#define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */
|
||||
#define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */
|
||||
#define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */
|
||||
#define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */
|
||||
#define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */
|
||||
#define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */
|
||||
#define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */
|
||||
#define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */
|
||||
#define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */
|
||||
#define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */
|
||||
|
||||
/* TIMER_SMCFG */
|
||||
#define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */
|
||||
#define TIMER_SMCFG_OCRC BIT(3) /*!< OCPRE clear source selection */
|
||||
#define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */
|
||||
#define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */
|
||||
#define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */
|
||||
#define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */
|
||||
#define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */
|
||||
#define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */
|
||||
|
||||
/* TIMER_DMAINTEN */
|
||||
#define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */
|
||||
#define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */
|
||||
#define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */
|
||||
#define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */
|
||||
#define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */
|
||||
#define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */
|
||||
#define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */
|
||||
#define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */
|
||||
#define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */
|
||||
#define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 DMA request enable */
|
||||
#define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 DMA request enable */
|
||||
#define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 DMA request enable */
|
||||
#define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 DMA request enable */
|
||||
#define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */
|
||||
#define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */
|
||||
|
||||
/* TIMER_INTF */
|
||||
#define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */
|
||||
#define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */
|
||||
#define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */
|
||||
#define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */
|
||||
#define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */
|
||||
#define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */
|
||||
#define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */
|
||||
#define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */
|
||||
#define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */
|
||||
#define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */
|
||||
#define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */
|
||||
#define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */
|
||||
|
||||
/* TIMER_SWEVG */
|
||||
#define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */
|
||||
#define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */
|
||||
#define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */
|
||||
#define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */
|
||||
#define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */
|
||||
#define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */
|
||||
#define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */
|
||||
#define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */
|
||||
|
||||
/* TIMER_CHCTL0 */
|
||||
/* output compare mode */
|
||||
#define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */
|
||||
#define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */
|
||||
#define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */
|
||||
#define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare mode */
|
||||
#define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */
|
||||
#define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */
|
||||
#define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */
|
||||
#define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */
|
||||
#define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare mode */
|
||||
#define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */
|
||||
/* input capture mode */
|
||||
#define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */
|
||||
#define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */
|
||||
#define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */
|
||||
#define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */
|
||||
|
||||
/* TIMER_CHCTL1 */
|
||||
/* output compare mode */
|
||||
#define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */
|
||||
#define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */
|
||||
#define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */
|
||||
#define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare mode */
|
||||
#define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */
|
||||
#define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */
|
||||
#define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */
|
||||
#define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */
|
||||
#define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare mode */
|
||||
#define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */
|
||||
/* input capture mode */
|
||||
#define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */
|
||||
#define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */
|
||||
#define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */
|
||||
#define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */
|
||||
|
||||
/* TIMER_CHCTL2 */
|
||||
#define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */
|
||||
#define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */
|
||||
#define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */
|
||||
#define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */
|
||||
#define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */
|
||||
#define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */
|
||||
#define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */
|
||||
#define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */
|
||||
#define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */
|
||||
#define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */
|
||||
#define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */
|
||||
#define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */
|
||||
#define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */
|
||||
#define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */
|
||||
#define TIMER_CHCTL2_CH3NP BIT(15) /*!< channel 3 complementary output polarity */
|
||||
|
||||
/* TIMER_CNT */
|
||||
#define TIMER_CNT_CNT16 BITS(0,15) /*!< 16 bit timer counter */
|
||||
|
||||
/* TIMER_PSC */
|
||||
#define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */
|
||||
|
||||
/* TIMER_CAR */
|
||||
#define TIMER_CAR_CARL16 BITS(0,15) /*!< 16 bit counter auto reload value */
|
||||
|
||||
/* TIMER_CREP */
|
||||
#define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */
|
||||
|
||||
/* TIMER_CH0CV */
|
||||
#define TIMER_CH0CV_CH0VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */
|
||||
|
||||
/* TIMER_CH1CV */
|
||||
#define TIMER_CH1CV_CH1VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */
|
||||
|
||||
/* TIMER_CH2CV */
|
||||
#define TIMER_CH2CV_CH2VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */
|
||||
|
||||
/* TIMER_CH3CV */
|
||||
#define TIMER_CH3CV_CH3VAL16 BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */
|
||||
|
||||
/* TIMER_CCHP */
|
||||
#define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */
|
||||
#define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */
|
||||
#define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */
|
||||
#define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */
|
||||
#define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */
|
||||
#define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */
|
||||
#define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */
|
||||
#define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */
|
||||
|
||||
/* TIMER_DMACFG */
|
||||
#define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */
|
||||
#define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */
|
||||
|
||||
/* TIMER_DMATB */
|
||||
#define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */
|
||||
|
||||
/* TIMER_IRMP */
|
||||
#define TIMER13_IRMP_CI0_RMP BITS(0,1) /*!< TIMER13 channel 0 input remap */
|
||||
|
||||
/* TIMER_CFG */
|
||||
#define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */
|
||||
#define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */
|
||||
|
||||
/* constants definitions */
|
||||
/* TIMER init parameter struct definitions*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t prescaler; /*!< prescaler value */
|
||||
uint16_t alignedmode; /*!< aligned mode */
|
||||
uint16_t counterdirection; /*!< counter direction */
|
||||
uint16_t clockdivision; /*!< clock division value */
|
||||
uint32_t period; /*!< period value */
|
||||
uint8_t repetitioncounter; /*!< the counter repetition value */
|
||||
}timer_parameter_struct;
|
||||
|
||||
/* break parameter struct definitions*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t runoffstate; /*!< run mode off-state */
|
||||
uint16_t ideloffstate; /*!< idle mode off-state */
|
||||
uint16_t deadtime; /*!< dead time */
|
||||
uint16_t breakpolarity; /*!< break polarity */
|
||||
uint16_t outputautostate; /*!< output automatic enable */
|
||||
uint16_t protectmode; /*!< complementary register protect control */
|
||||
uint16_t breakstate; /*!< break enable */
|
||||
}timer_break_parameter_struct;
|
||||
|
||||
/* channel output parameter struct definitions */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t outputstate; /*!< channel output state */
|
||||
uint16_t outputnstate; /*!< channel complementary output state */
|
||||
uint16_t ocpolarity; /*!< channel output polarity */
|
||||
uint16_t ocnpolarity; /*!< channel complementary output polarity */
|
||||
uint16_t ocidlestate; /*!< idle state of channel output */
|
||||
uint16_t ocnidlestate; /*!< idle state of channel complementary output */
|
||||
}timer_oc_parameter_struct;
|
||||
|
||||
/* channel input parameter struct definitions */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t icpolarity; /*!< channel input polarity */
|
||||
uint16_t icselection; /*!< channel input mode selection */
|
||||
uint16_t icprescaler; /*!< channel input capture prescaler */
|
||||
uint16_t icfilter; /*!< channel input capture filter control */
|
||||
}timer_ic_parameter_struct;
|
||||
|
||||
/* TIMER interrupt enable or disable */
|
||||
#define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */
|
||||
#define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */
|
||||
#define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */
|
||||
#define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */
|
||||
#define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */
|
||||
#define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */
|
||||
#define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */
|
||||
#define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */
|
||||
|
||||
/* TIMER flag */
|
||||
#define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */
|
||||
#define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */
|
||||
#define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */
|
||||
#define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */
|
||||
#define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */
|
||||
#define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation flag */
|
||||
#define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */
|
||||
#define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */
|
||||
#define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */
|
||||
#define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */
|
||||
#define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */
|
||||
#define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */
|
||||
|
||||
/* TIMER interrupt flag */
|
||||
#define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */
|
||||
#define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */
|
||||
#define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */
|
||||
#define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */
|
||||
#define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */
|
||||
#define TIMER_INT_FLAG_CMT TIMER_INTF_CMTIF /*!< channel commutation interrupt flag */
|
||||
#define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */
|
||||
#define TIMER_INT_FLAG_BRK TIMER_INTF_BRKIF
|
||||
|
||||
/* TIMER DMA source enable */
|
||||
#define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */
|
||||
#define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */
|
||||
#define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */
|
||||
#define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */
|
||||
#define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */
|
||||
#define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */
|
||||
#define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */
|
||||
|
||||
/* channel DMA request source selection */
|
||||
#define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel y is sent when update event occurs */
|
||||
#define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel y is sent when channel y event occurs */
|
||||
|
||||
/* DMA access base address */
|
||||
#define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U))
|
||||
#define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */
|
||||
#define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */
|
||||
#define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */
|
||||
#define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */
|
||||
#define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */
|
||||
#define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */
|
||||
#define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */
|
||||
#define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */
|
||||
#define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */
|
||||
#define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */
|
||||
#define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */
|
||||
#define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */
|
||||
#define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */
|
||||
#define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */
|
||||
#define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */
|
||||
#define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */
|
||||
#define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */
|
||||
#define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */
|
||||
#define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */
|
||||
|
||||
/* DMA access burst length */
|
||||
#define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U))
|
||||
#define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */
|
||||
#define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */
|
||||
#define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */
|
||||
#define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */
|
||||
#define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */
|
||||
#define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */
|
||||
#define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */
|
||||
#define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */
|
||||
#define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */
|
||||
#define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */
|
||||
#define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */
|
||||
#define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */
|
||||
#define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */
|
||||
#define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */
|
||||
#define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */
|
||||
#define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */
|
||||
#define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */
|
||||
#define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */
|
||||
|
||||
/* TIMER software event generation source */
|
||||
#define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */
|
||||
#define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */
|
||||
#define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */
|
||||
#define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */
|
||||
#define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */
|
||||
#define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */
|
||||
#define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */
|
||||
#define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */
|
||||
|
||||
/* center-aligned mode selection */
|
||||
#define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U)))
|
||||
#define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */
|
||||
#define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */
|
||||
#define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */
|
||||
#define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */
|
||||
|
||||
/* TIMER prescaler reload mode */
|
||||
#define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */
|
||||
#define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */
|
||||
|
||||
/* count direction */
|
||||
#define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */
|
||||
#define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */
|
||||
|
||||
/* specify division ratio between TIMER clock and dead-time and sampling clock */
|
||||
#define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
|
||||
#define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1, fDTS=fTIMER_CK */
|
||||
#define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2, fDTS= fTIMER_CK/2 */
|
||||
#define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */
|
||||
|
||||
/* single pulse mode */
|
||||
#define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */
|
||||
#define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */
|
||||
|
||||
/* update source */
|
||||
#define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */
|
||||
#define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */
|
||||
|
||||
/* run mode off-state configure */
|
||||
#define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
|
||||
#define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled */
|
||||
|
||||
/* idle mode off-state configure */
|
||||
#define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals (CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */
|
||||
#define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled */
|
||||
|
||||
/* break input polarity */
|
||||
#define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */
|
||||
#define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */
|
||||
|
||||
/* output automatic enable */
|
||||
#define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */
|
||||
#define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */
|
||||
|
||||
/* complementary register protect control */
|
||||
#define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U)))
|
||||
#define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */
|
||||
#define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */
|
||||
#define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */
|
||||
#define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */
|
||||
|
||||
/* break input enable */
|
||||
#define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */
|
||||
#define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */
|
||||
|
||||
/* TIMER channel n(n=0,1,2,3) */
|
||||
#define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0,2,13..16)) */
|
||||
#define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0,2,14)) */
|
||||
#define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0,2)) */
|
||||
#define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0,2)) */
|
||||
#define TIMER_CH_0_1 ((uint16_t)0x0004U) /*!< TIMER channel 0 and 1 for function parameter */
|
||||
|
||||
/* channel enable state*/
|
||||
#define TIMER_CCX_ENABLE ((uint32_t)0x00000001U) /*!< channel enable */
|
||||
#define TIMER_CCX_DISABLE ((uint32_t)0x00000000U) /*!< channel disable */
|
||||
|
||||
/* channel complementary output enable state*/
|
||||
#define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */
|
||||
#define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */
|
||||
|
||||
/* channel output polarity */
|
||||
#define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */
|
||||
#define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */
|
||||
|
||||
/* channel complementary output polarity */
|
||||
#define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */
|
||||
#define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */
|
||||
|
||||
/* idle state of channel output */
|
||||
#define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */
|
||||
#define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */
|
||||
|
||||
/* idle state of channel complementary output */
|
||||
#define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */
|
||||
#define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */
|
||||
|
||||
/* channel output compare mode */
|
||||
#define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */
|
||||
#define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */
|
||||
#define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */
|
||||
#define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */
|
||||
#define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */
|
||||
#define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */
|
||||
#define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */
|
||||
#define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/
|
||||
|
||||
/* channel output compare shadow enable */
|
||||
#define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */
|
||||
#define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */
|
||||
|
||||
/* channel output compare fast enable */
|
||||
#define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */
|
||||
#define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */
|
||||
|
||||
/* channel output compare clear enable */
|
||||
#define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */
|
||||
#define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */
|
||||
|
||||
/* channel control shadow register update control */
|
||||
#define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers are updated when CMTG bit is set */
|
||||
#define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers are updated when CMTG bit is set or an rising edge of TRGI occurs */
|
||||
|
||||
/* channel input capture polarity */
|
||||
#define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */
|
||||
#define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */
|
||||
#define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */
|
||||
|
||||
/* TIMER input capture selection */
|
||||
#define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */
|
||||
#define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */
|
||||
#define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */
|
||||
|
||||
/* channel input capture prescaler */
|
||||
#define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */
|
||||
#define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */
|
||||
#define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4*/
|
||||
#define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */
|
||||
|
||||
/* trigger selection */
|
||||
#define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
|
||||
#define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */
|
||||
#define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */
|
||||
#define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */
|
||||
#define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */
|
||||
#define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */
|
||||
#define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */
|
||||
#define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */
|
||||
#define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< external trigger */
|
||||
|
||||
/* master mode control */
|
||||
#define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U))
|
||||
#define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */
|
||||
#define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */
|
||||
#define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */
|
||||
#define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channal0 as trigger output TRGO */
|
||||
#define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */
|
||||
#define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */
|
||||
#define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */
|
||||
#define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */
|
||||
|
||||
/* slave mode control */
|
||||
#define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U))
|
||||
#define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */
|
||||
#define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */
|
||||
#define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */
|
||||
#define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */
|
||||
#define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */
|
||||
#define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */
|
||||
#define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */
|
||||
#define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */
|
||||
|
||||
/* OCPRE clear source selection */
|
||||
#define TIMER_OCPRE_CLEAR_SOURCE_CLR ((uint8_t)0x00U) /*!< OCPRE_CLR_INT is connected to the OCPRE_CLR input */
|
||||
#define TIMER_OCPRE_CLEAR_SOURCE_ETIF ((uint8_t)0x01U) /*!< OCPRE_CLR_INT is connected to ETIF */
|
||||
#define TIMER_OCPRE_CLEAR_SOURCE_DISABLE ((uint8_t)0x02U) /*!< OCRC=0, and disable ETI */
|
||||
|
||||
/* master slave mode selection */
|
||||
#define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */
|
||||
#define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */
|
||||
|
||||
/* external trigger prescaler */
|
||||
#define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U))
|
||||
#define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */
|
||||
#define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */
|
||||
#define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */
|
||||
#define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */
|
||||
|
||||
/* external trigger polarity */
|
||||
#define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */
|
||||
#define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */
|
||||
|
||||
/* channel 0 trigger input selection */
|
||||
#define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */
|
||||
#define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */
|
||||
|
||||
/* TIMERx(x=0,2,13,14,15,16) write cc register selection */
|
||||
#define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */
|
||||
#define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */
|
||||
|
||||
/* the output value selection */
|
||||
#define TIMER_OUTSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< output value selection enable */
|
||||
#define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */
|
||||
|
||||
/* timer13 channel 0 input remap */
|
||||
#define TIMER13_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U))
|
||||
#define TIMER13_CI0_RMP_GPIO TIMER13_IRMP(0) /*!< timer13 channel 0 input is connected to GPIO(TIMER13_CH0) */
|
||||
#define TIMER13_CI0_RMP_RTCCLK TIMER13_IRMP(1) /*!< timer13 channel 0 input is connected to the RTCCLK */
|
||||
#define TIMER13_CI0_RMP_HXTAL_DIV32 TIMER13_IRMP(2) /*!< timer13 channel 0 input is connected to HXTAL/32 clock */
|
||||
#define TIMER13_CI0_RMP_CKOUTSEL TIMER13_IRMP(3) /*!< timer13 channel 0 input is connected to CKOUTSEL */
|
||||
|
||||
/* function declarations */
|
||||
/* TIMER timebase*/
|
||||
/* deinit a TIMER */
|
||||
void timer_deinit(uint32_t timer_periph);
|
||||
/* initialize TIMER init parameter struct */
|
||||
void timer_struct_para_init(timer_parameter_struct* initpara);
|
||||
/* initialize TIMER counter */
|
||||
void timer_init(uint32_t timer_periph, timer_parameter_struct* initpara);
|
||||
/* enable a TIMER */
|
||||
void timer_enable(uint32_t timer_periph);
|
||||
/* disable a TIMER */
|
||||
void timer_disable(uint32_t timer_periph);
|
||||
/* enable the auto reload shadow function */
|
||||
void timer_auto_reload_shadow_enable(uint32_t timer_periph);
|
||||
/* disable the auto reload shadow function */
|
||||
void timer_auto_reload_shadow_disable(uint32_t timer_periph);
|
||||
/* enable the update event */
|
||||
void timer_update_event_enable(uint32_t timer_periph);
|
||||
/* disable the update event */
|
||||
void timer_update_event_disable(uint32_t timer_periph);
|
||||
/* set TIMER counter alignment mode */
|
||||
void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned);
|
||||
/* set TIMER counter up direction */
|
||||
void timer_counter_up_direction(uint32_t timer_periph);
|
||||
/* set TIMER counter down direction */
|
||||
void timer_counter_down_direction(uint32_t timer_periph);
|
||||
/* configure TIMER prescaler */
|
||||
void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload);
|
||||
/* configure TIMER repetition register value */
|
||||
void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition);
|
||||
/* configure TIMER autoreload register value */
|
||||
void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload);
|
||||
/* configure TIMER counter register value */
|
||||
void timer_counter_value_config(uint32_t timer_periph , uint16_t counter);
|
||||
/* read TIMER counter value */
|
||||
uint32_t timer_counter_read(uint32_t timer_periph);
|
||||
/* read TIMER prescaler value */
|
||||
uint16_t timer_prescaler_read(uint32_t timer_periph);
|
||||
/* configure TIMER single pulse mode */
|
||||
void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode);
|
||||
/* configure TIMER update source */
|
||||
void timer_update_source_config(uint32_t timer_periph, uint32_t update);
|
||||
/* OCPRE clear source selection */
|
||||
void timer_ocpre_clear_source_config(uint32_t timer_periph, uint8_t ocpreclear);
|
||||
|
||||
/* TIMER interrupt and flag*/
|
||||
/* enable the TIMER interrupt */
|
||||
void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt);
|
||||
/* disable the TIMER interrupt */
|
||||
void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt);
|
||||
/* get timer interrupt flag */
|
||||
FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt);
|
||||
/* clear TIMER interrupt flag */
|
||||
void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt);
|
||||
/* get TIMER flags */
|
||||
FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag);
|
||||
/* clear TIMER flags */
|
||||
void timer_flag_clear(uint32_t timer_periph, uint32_t flag);
|
||||
|
||||
/* timer DMA and event*/
|
||||
/* enable the TIMER DMA */
|
||||
void timer_dma_enable(uint32_t timer_periph, uint16_t dma);
|
||||
/* disable the TIMER DMA */
|
||||
void timer_dma_disable(uint32_t timer_periph, uint16_t dma);
|
||||
/* channel DMA request source selection */
|
||||
void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request);
|
||||
/* configure the TIMER DMA transfer */
|
||||
void timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr, uint32_t dma_lenth);
|
||||
/* software generate events */
|
||||
void timer_event_software_generate(uint32_t timer_periph, uint16_t event);
|
||||
|
||||
/* TIMER channel complementary protection */
|
||||
/* initialize TIMER break parameter struct */
|
||||
void timer_break_struct_para_init(timer_break_parameter_struct* breakpara);
|
||||
/* configure TIMER break function */
|
||||
void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara);
|
||||
/* enable TIMER break function */
|
||||
void timer_break_enable(uint32_t timer_periph);
|
||||
/* disable TIMER break function */
|
||||
void timer_break_disable(uint32_t timer_periph);
|
||||
/* enable TIMER output automatic function */
|
||||
void timer_automatic_output_enable(uint32_t timer_periph);
|
||||
/* disable TIMER output automatic function */
|
||||
void timer_automatic_output_disable(uint32_t timer_periph);
|
||||
/* enable or disable TIMER primary output function */
|
||||
void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue);
|
||||
/* enable or disable channel capture/compare control shadow register */
|
||||
void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue);
|
||||
/* configure TIMER channel control shadow register update control */
|
||||
void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl);
|
||||
|
||||
/* TIMER channel output */
|
||||
/* initialize TIMER channel output parameter struct */
|
||||
void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara);
|
||||
/* configure TIMER channel output function */
|
||||
void timer_channel_output_config(uint32_t timer_periph,uint16_t channel, timer_oc_parameter_struct* ocpara);
|
||||
/* configure TIMER channel output compare mode */
|
||||
void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel,uint16_t ocmode);
|
||||
/* configure TIMER channel output pulse value */
|
||||
void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse);
|
||||
/* configure TIMER channel output shadow function */
|
||||
void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow);
|
||||
/* configure TIMER channel output fast function */
|
||||
void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast);
|
||||
/* configure TIMER channel output clear function */
|
||||
void timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear);
|
||||
/* configure TIMER channel output polarity */
|
||||
void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity);
|
||||
/* configure TIMER channel complementary output polarity */
|
||||
void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity);
|
||||
/* configure TIMER channel enable state */
|
||||
void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state);
|
||||
/* configure TIMER channel complementary output enable state */
|
||||
void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate);
|
||||
|
||||
/* TIMER channel input */
|
||||
/* initialize TIMER channel input parameter struct */
|
||||
void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara);
|
||||
/* configure TIMER input capture parameter */
|
||||
void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara);
|
||||
/* configure TIMER channel input capture prescaler value */
|
||||
void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler);
|
||||
/* read TIMER channel capture compare register value */
|
||||
uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel);
|
||||
/* configure TIMER input pwm capture function */
|
||||
void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm);
|
||||
/* configure TIMER hall sensor mode */
|
||||
void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode);
|
||||
|
||||
/* TIMER master and slave */
|
||||
/* select TIMER input trigger source */
|
||||
void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger);
|
||||
/* select TIMER master mode output trigger source */
|
||||
void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger);
|
||||
/* select TIMER slave mode */
|
||||
void timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode);
|
||||
/* configure TIMER master slave mode */
|
||||
void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave);
|
||||
/* configure TIMER external trigger input */
|
||||
void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter);
|
||||
/* configure TIMER quadrature decoder mode */
|
||||
void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity);
|
||||
/* configure TIMER internal clock mode */
|
||||
void timer_internal_clock_config(uint32_t timer_periph);
|
||||
/* configure TIMER the internal trigger as external clock input */
|
||||
void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger);
|
||||
/* configure TIMER the external trigger as external clock input */
|
||||
void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity,uint32_t extfilter);
|
||||
/* configure TIMER the external clock mode 0 */
|
||||
void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter);
|
||||
/* configure TIMER the external clock mode 1 */
|
||||
void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter);
|
||||
/* disable TIMER the external clock mode 1 */
|
||||
void timer_external_clock_mode1_disable(uint32_t timer_periph);
|
||||
/* configure TIMER channel remap function */
|
||||
void timer_channel_remap_config(uint32_t timer_periph,uint32_t remap);
|
||||
|
||||
/* TIMER configure */
|
||||
/* configure TIMER write CHxVAL register selection */
|
||||
void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel);
|
||||
/* configure TIMER output value selection */
|
||||
void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel);
|
||||
|
||||
#endif /* GD32E23X_TIMER_H */
|
||||
@@ -0,0 +1,592 @@
|
||||
/*!
|
||||
\file gd32e23x_usart.h
|
||||
\brief definitions for the USART
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_USART_H
|
||||
#define GD32E23X_USART_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* USARTx(x=0,1) definitions */
|
||||
#define USART0 (USART_BASE + 0x0000F400U)
|
||||
#define USART1 USART_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define USART_CTL0(usartx) REG32((usartx) + 0x00000000U) /*!< USART control register 0 */
|
||||
#define USART_CTL1(usartx) REG32((usartx) + 0x00000004U) /*!< USART control register 1 */
|
||||
#define USART_CTL2(usartx) REG32((usartx) + 0x00000008U) /*!< USART control register 2 */
|
||||
#define USART_BAUD(usartx) REG32((usartx) + 0x0000000CU) /*!< USART baud rate register */
|
||||
#define USART_GP(usartx) REG32((usartx) + 0x00000010U) /*!< USART guard time and prescaler register */
|
||||
#define USART_RT(usartx) REG32((usartx) + 0x00000014U) /*!< USART receiver timeout register */
|
||||
#define USART_CMD(usartx) REG32((usartx) + 0x00000018U) /*!< USART command register */
|
||||
#define USART_STAT(usartx) REG32((usartx) + 0x0000001CU) /*!< USART status register */
|
||||
#define USART_INTC(usartx) REG32((usartx) + 0x00000020U) /*!< USART status clear register */
|
||||
#define USART_RDATA(usartx) REG32((usartx) + 0x00000024U) /*!< USART receive data register */
|
||||
#define USART_TDATA(usartx) REG32((usartx) + 0x00000028U) /*!< USART transmit data register */
|
||||
#define USART_CHC(usartx) REG32((usartx) + 0x000000C0U) /*!< USART coherence control register */
|
||||
#define USART_RFCS(usartx) REG32((usartx) + 0x000000D0U) /*!< USART receive FIFO control and status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* USARTx_CTL0 */
|
||||
#define USART_CTL0_UEN BIT(0) /*!< USART enable */
|
||||
#define USART_CTL0_UESM BIT(1) /*!< USART enable in deep-sleep mode */
|
||||
#define USART_CTL0_REN BIT(2) /*!< receiver enable */
|
||||
#define USART_CTL0_TEN BIT(3) /*!< transmitter enable */
|
||||
#define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */
|
||||
#define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */
|
||||
#define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */
|
||||
#define USART_CTL0_TBEIE BIT(7) /*!< transmitter register empty interrupt enable */
|
||||
#define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */
|
||||
#define USART_CTL0_PM BIT(9) /*!< parity mode */
|
||||
#define USART_CTL0_PCEN BIT(10) /*!< parity control enable */
|
||||
#define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */
|
||||
#define USART_CTL0_WL BIT(12) /*!< word length */
|
||||
#define USART_CTL0_MEN BIT(13) /*!< mute mode enable */
|
||||
#define USART_CTL0_AMIE BIT(14) /*!< address match interrupt enable */
|
||||
#define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */
|
||||
#define USART_CTL0_DED BITS(16,20) /*!< driver enable deassertion time */
|
||||
#define USART_CTL0_DEA BITS(21,25) /*!< driver enable assertion time */
|
||||
#define USART_CTL0_RTIE BIT(26) /*!< receiver timeout interrupt enable */
|
||||
#define USART_CTL0_EBIE BIT(27) /*!< end of block interrupt enable */
|
||||
|
||||
/* USARTx_CTL1 */
|
||||
#define USART_CTL1_ADDM BIT(4) /*!< address detection mode */
|
||||
#define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */
|
||||
#define USART_CTL1_LBDIE BIT(6) /*!< LIN break detection interrupt enable */
|
||||
#define USART_CTL1_CLEN BIT(8) /*!< last bit clock pulse */
|
||||
#define USART_CTL1_CPH BIT(9) /*!< clock phase */
|
||||
#define USART_CTL1_CPL BIT(10) /*!< clock polarity */
|
||||
#define USART_CTL1_CKEN BIT(11) /*!< ck pin enable */
|
||||
#define USART_CTL1_STB BITS(12,13) /*!< stop bits length */
|
||||
#define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */
|
||||
#define USART_CTL1_STRP BIT(15) /*!< swap TX/RX pins */
|
||||
#define USART_CTL1_RINV BIT(16) /*!< RX pin level inversion */
|
||||
#define USART_CTL1_TINV BIT(17) /*!< TX pin level inversion */
|
||||
#define USART_CTL1_DINV BIT(18) /*!< data bit level inversion */
|
||||
#define USART_CTL1_MSBF BIT(19) /*!< most significant bit first */
|
||||
#define USART_CTL1_RTEN BIT(23) /*!< receiver timeout enable */
|
||||
#define USART_CTL1_ADDR BITS(24,31) /*!< address of the USART terminal */
|
||||
|
||||
/* USARTx_CTL2 */
|
||||
#define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable in multibuffer communication */
|
||||
#define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */
|
||||
#define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */
|
||||
#define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */
|
||||
#define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */
|
||||
#define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */
|
||||
#define USART_CTL2_DENR BIT(6) /*!< DMA enable for reception */
|
||||
#define USART_CTL2_DENT BIT(7) /*!< DMA enable for transmission */
|
||||
#define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */
|
||||
#define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */
|
||||
#define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */
|
||||
#define USART_CTL2_OSB BIT(11) /*!< one sample bit mode */
|
||||
#define USART_CTL2_OVRD BIT(12) /*!< overrun disable */
|
||||
#define USART_CTL2_DDRE BIT(13) /*!< disable DMA on reception error */
|
||||
#define USART_CTL2_DEM BIT(14) /*!< driver enable mode */
|
||||
#define USART_CTL2_DEP BIT(15) /*!< driver enable polarity mode */
|
||||
#define USART_CTL2_SCRTNUM BITS(17,19) /*!< smartcard auto-retry number */
|
||||
#define USART_CTL2_WUM BITS(20,21) /*!< wakeup mode from deep-sleep mode */
|
||||
#define USART_CTL2_WUIE BIT(22) /*!< wakeup from deep-sleep mode interrupt enable */
|
||||
|
||||
/* USARTx_BAUD */
|
||||
#define USART_BAUD_FRADIV BITS(0,3) /*!< fraction of baud-rate divider */
|
||||
#define USART_BAUD_INTDIV BITS(4,15) /*!< integer of baud-rate divider */
|
||||
|
||||
/* USARTx_GP */
|
||||
#define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */
|
||||
#define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */
|
||||
|
||||
/* USARTx_RT */
|
||||
#define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */
|
||||
#define USART_RT_BL BITS(24,31) /*!< block length */
|
||||
|
||||
/* USARTx_CMD */
|
||||
#define USART_CMD_SBKCMD BIT(1) /*!< send break command */
|
||||
#define USART_CMD_MMCMD BIT(2) /*!< mute mode command */
|
||||
#define USART_CMD_RXFCMD BIT(3) /*!< receive data flush command */
|
||||
#define USART_CMD_TXFCMD BIT(4) /*!< transmit data flush request */
|
||||
|
||||
/* USARTx_STAT */
|
||||
#define USART_STAT_PERR BIT(0) /*!< parity error flag */
|
||||
#define USART_STAT_FERR BIT(1) /*!< frame error flag */
|
||||
#define USART_STAT_NERR BIT(2) /*!< noise error flag */
|
||||
#define USART_STAT_ORERR BIT(3) /*!< overrun error */
|
||||
#define USART_STAT_IDLEF BIT(4) /*!< idle line detected flag */
|
||||
#define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */
|
||||
#define USART_STAT_TC BIT(6) /*!< transmission completed */
|
||||
#define USART_STAT_TBE BIT(7) /*!< transmit data register empty */
|
||||
#define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */
|
||||
#define USART_STAT_CTSF BIT(9) /*!< CTS change flag */
|
||||
#define USART_STAT_CTS BIT(10) /*!< CTS level */
|
||||
#define USART_STAT_RTF BIT(11) /*!< receiver timeout flag */
|
||||
#define USART_STAT_EBF BIT(12) /*!< end of block flag */
|
||||
#define USART_STAT_BSY BIT(16) /*!< busy flag */
|
||||
#define USART_STAT_AMF BIT(17) /*!< address match flag */
|
||||
#define USART_STAT_SBF BIT(18) /*!< send break flag */
|
||||
#define USART_STAT_RWU BIT(19) /*!< receiver wakeup from mute mode */
|
||||
#define USART_STAT_WUF BIT(20) /*!< wakeup from deep-sleep mode flag */
|
||||
#define USART_STAT_TEA BIT(21) /*!< transmit enable acknowledge flag */
|
||||
#define USART_STAT_REA BIT(22) /*!< receive enable acknowledge flag */
|
||||
|
||||
/* USARTx_INTC */
|
||||
#define USART_INTC_PEC BIT(0) /*!< parity error clear */
|
||||
#define USART_INTC_FEC BIT(1) /*!< frame error flag clear */
|
||||
#define USART_INTC_NEC BIT(2) /*!< noise detected clear */
|
||||
#define USART_INTC_OREC BIT(3) /*!< overrun error clear */
|
||||
#define USART_INTC_IDLEC BIT(4) /*!< idle line detected clear */
|
||||
#define USART_INTC_TCC BIT(6) /*!< transmission complete clear */
|
||||
#define USART_INTC_LBDC BIT(8) /*!< LIN break detected clear */
|
||||
#define USART_INTC_CTSC BIT(9) /*!< CTS change clear */
|
||||
#define USART_INTC_RTC BIT(11) /*!< receiver timeout clear */
|
||||
#define USART_INTC_EBC BIT(12) /*!< end of timeout clear */
|
||||
#define USART_INTC_AMC BIT(17) /*!< address match clear */
|
||||
#define USART_INTC_WUC BIT(20) /*!< wakeup from deep-sleep mode clear */
|
||||
|
||||
/* USARTx_RDATA */
|
||||
#define USART_RDATA_RDATA BITS(0,8) /*!< receive data value */
|
||||
|
||||
/* USARTx_TDATA */
|
||||
#define USART_TDATA_TDATA BITS(0,8) /*!< transmit data value */
|
||||
|
||||
/* USARTx_CHC */
|
||||
#define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */
|
||||
#define USART_CHC_EPERR BIT(8) /*!< early parity error flag */
|
||||
|
||||
/* USARTx_RFCS */
|
||||
#define USART_RFCS_ELNACK BIT(0) /*!< early NACK */
|
||||
#define USART_RFCS_RFEN BIT(8) /*!< receive FIFO enable */
|
||||
#define USART_RFCS_RFFIE BIT(9) /*!< receive FIFO full interrupt enable */
|
||||
#define USART_RFCS_RFE BIT(10) /*!< receive FIFO empty flag */
|
||||
#define USART_RFCS_RFF BIT(11) /*!< receive FIFO full flag */
|
||||
#define USART_RFCS_RFCNT BITS(12,14) /*!< receive FIFO counter number */
|
||||
#define USART_RFCS_RFFINT BIT(15) /*!< receive FIFO full interrupt flag */
|
||||
|
||||
/* constants definitions */
|
||||
/* define the USART bit position and its register index offset */
|
||||
#define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)))
|
||||
#define USART_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU)
|
||||
#define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\
|
||||
| (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)))
|
||||
#define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22)))
|
||||
#define USART_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16)
|
||||
|
||||
/* register offset */
|
||||
#define USART_CTL0_REG_OFFSET 0x00000000U /*!< CTL0 register offset */
|
||||
#define USART_CTL1_REG_OFFSET 0x00000004U /*!< CTL1 register offset */
|
||||
#define USART_CTL2_REG_OFFSET 0x00000008U /*!< CTL2 register offset */
|
||||
#define USART_STAT_REG_OFFSET 0x0000001CU /*!< STAT register offset */
|
||||
#define USART_CHC_REG_OFFSET 0x000000C0U /*!< CHC register offset */
|
||||
#define USART_RFCS_REG_OFFSET 0x000000D0U /*!< RFCS register offset */
|
||||
|
||||
/* USART flags */
|
||||
typedef enum{
|
||||
/* flags in STAT register */
|
||||
USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U), /*!< receive enable acknowledge flag */
|
||||
USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U), /*!< transmit enable acknowledge flag */
|
||||
USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U), /*!< wakeup from Deep-sleep mode flag */
|
||||
USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U), /*!< receiver wakeup from mute mode */
|
||||
USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U), /*!< send break flag */
|
||||
USART_FLAG_AM = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U), /*!< ADDR match flag */
|
||||
USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 16U), /*!< busy flag */
|
||||
USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 12U), /*!< end of block flag */
|
||||
USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout flag */
|
||||
USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 10U), /*!< CTS level */
|
||||
USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */
|
||||
USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */
|
||||
USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */
|
||||
USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */
|
||||
USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */
|
||||
USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected flag */
|
||||
USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */
|
||||
USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */
|
||||
USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */
|
||||
USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */
|
||||
/* flags in CHC register */
|
||||
USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */
|
||||
/* flags in RFCS register */
|
||||
USART_FLAG_RFFINT = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt flag */
|
||||
USART_FLAG_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 11U), /*!< receive FIFO full flag */
|
||||
USART_FLAG_RFE = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 10U), /*!< receive FIFO empty flag */
|
||||
}usart_flag_enum;
|
||||
|
||||
/* USART interrupt flags */
|
||||
typedef enum
|
||||
{
|
||||
/* interrupt flags in CTL0 register */
|
||||
USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U), /*!< end of block interrupt and flag */
|
||||
USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout interrupt and flag */
|
||||
USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U), /*!< address match interrupt and flag */
|
||||
USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */
|
||||
USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */
|
||||
USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */
|
||||
USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */
|
||||
USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */
|
||||
USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */
|
||||
/* interrupt flags in CTL1 register */
|
||||
USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */
|
||||
/* interrupt flags in CTL2 register */
|
||||
USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode interrupt and flag */
|
||||
USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */
|
||||
USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */
|
||||
USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */
|
||||
USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */
|
||||
/* interrupt flags in RFCS register */
|
||||
USART_INT_FLAG_RFF = USART_REGIDX_BIT2(USART_RFCS_REG_OFFSET, 9U, USART_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt and flag */
|
||||
}usart_interrupt_flag_enum;
|
||||
|
||||
/* USART interrupt enable or disable */
|
||||
typedef enum
|
||||
{
|
||||
/* interrupt in CTL0 register */
|
||||
USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U), /*!< end of block interrupt */
|
||||
USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U), /*!< receiver timeout interrupt */
|
||||
USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U), /*!< address match interrupt */
|
||||
USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */
|
||||
USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */
|
||||
USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */
|
||||
USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */
|
||||
USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */
|
||||
/* interrupt in CTL1 register */
|
||||
USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */
|
||||
/* interrupt in CTL2 register */
|
||||
USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U), /*!< wakeup from deep-sleep mode interrupt */
|
||||
USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */
|
||||
USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */
|
||||
/* interrupt in RFCS register */
|
||||
USART_INT_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 9U), /*!< receive FIFO full interrupt */
|
||||
}usart_interrupt_enum;
|
||||
|
||||
/* USART invert configure */
|
||||
typedef enum {
|
||||
/* data bit level inversion */
|
||||
USART_DINV_ENABLE, /*!< data bit level inversion */
|
||||
USART_DINV_DISABLE, /*!< data bit level not inversion */
|
||||
/* TX pin level inversion */
|
||||
USART_TXPIN_ENABLE, /*!< TX pin level inversion */
|
||||
USART_TXPIN_DISABLE, /*!< TX pin level not inversion */
|
||||
/* RX pin level inversion */
|
||||
USART_RXPIN_ENABLE, /*!< RX pin level inversion */
|
||||
USART_RXPIN_DISABLE, /*!< RX pin level not inversion */
|
||||
/* swap TX/RX pins */
|
||||
USART_SWAP_ENABLE, /*!< swap TX/RX pins */
|
||||
USART_SWAP_DISABLE, /*!< not swap TX/RX pins */
|
||||
}usart_invert_enum;
|
||||
|
||||
/* USART receiver configure */
|
||||
#define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2))
|
||||
#define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */
|
||||
#define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */
|
||||
|
||||
/* USART transmitter configure */
|
||||
#define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3))
|
||||
#define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */
|
||||
#define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */
|
||||
|
||||
/* USART parity bits definitions */
|
||||
#define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9))
|
||||
#define USART_PM_NONE CTL0_PM(0) /*!< no parity */
|
||||
#define USART_PM_EVEN CTL0_PM(2) /*!< even parity */
|
||||
#define USART_PM_ODD CTL0_PM(3) /*!< odd parity */
|
||||
|
||||
/* USART wakeup method in mute mode */
|
||||
#define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11))
|
||||
#define USART_WM_IDLE CTL0_WM(0) /*!< idle line */
|
||||
#define USART_WM_ADDR CTL0_WM(1) /*!< address match */
|
||||
|
||||
/* USART word length definitions */
|
||||
#define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12))
|
||||
#define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */
|
||||
#define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */
|
||||
|
||||
/* USART oversample mode */
|
||||
#define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15))
|
||||
#define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< oversampling by 8 */
|
||||
#define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< oversampling by 16 */
|
||||
|
||||
/* USART address detection mode */
|
||||
#define CTL1_ADDM(regval) (BIT(4) & ((uint32_t)(regval) << 4))
|
||||
#define USART_ADDM_4BIT CTL1_ADDM(0) /*!< 4-bit address detection */
|
||||
#define USART_ADDM_FULLBIT CTL1_ADDM(1) /*!< full-bit address detection */
|
||||
|
||||
/* USART LIN break frame length */
|
||||
#define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5))
|
||||
#define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits break detection */
|
||||
#define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits break detection */
|
||||
|
||||
/* USART last bit clock pulse */
|
||||
#define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
|
||||
#define USART_CLEN_NONE CTL1_CLEN(0) /*!< clock pulse of the last data bit (MSB) is not output to the CK pin */
|
||||
#define USART_CLEN_EN CTL1_CLEN(1) /*!< clock pulse of the last data bit (MSB) is output to the CK pin */
|
||||
|
||||
/* USART clock phase */
|
||||
#define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9))
|
||||
#define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */
|
||||
#define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */
|
||||
|
||||
/* USART clock polarity */
|
||||
#define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10))
|
||||
#define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */
|
||||
#define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */
|
||||
|
||||
/* USART stop bits definitions */
|
||||
#define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12))
|
||||
#define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */
|
||||
#define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */
|
||||
#define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */
|
||||
#define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */
|
||||
|
||||
/* USART data is transmitted/received with the LSB/MSB first */
|
||||
#define CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19))
|
||||
#define USART_MSBF_LSB CTL1_MSBF(0) /*!< LSB first */
|
||||
#define USART_MSBF_MSB CTL1_MSBF(1) /*!< MSB first */
|
||||
|
||||
/* USART IrDA low-power enable */
|
||||
#define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2))
|
||||
#define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */
|
||||
#define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */
|
||||
|
||||
/* DMA enable for reception */
|
||||
#define CTL2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6))
|
||||
#define USART_DENR_ENABLE CTL2_DENR(1) /*!< enable for reception */
|
||||
#define USART_DENR_DISABLE CTL2_DENR(0) /*!< disable for reception */
|
||||
|
||||
/* DMA enable for transmission */
|
||||
#define CTL2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7))
|
||||
#define USART_DENT_ENABLE CTL2_DENT(1) /*!< enable for transmission */
|
||||
#define USART_DENT_DISABLE CTL2_DENT(0) /*!< disable for transmission */
|
||||
|
||||
/* USART RTS hardware flow control configure */
|
||||
#define CTL2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8))
|
||||
#define USART_RTS_ENABLE CTL2_RTSEN(1) /*!< RTS hardware flow control enabled */
|
||||
#define USART_RTS_DISABLE CTL2_RTSEN(0) /*!< RTS hardware flow control disabled */
|
||||
|
||||
/* USART CTS hardware flow control configure */
|
||||
#define CTL2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9))
|
||||
#define USART_CTS_ENABLE CTL2_CTSEN(1) /*!< CTS hardware flow control enabled */
|
||||
#define USART_CTS_DISABLE CTL2_CTSEN(0) /*!< CTS hardware flow control disabled */
|
||||
|
||||
/* USART one sample bit method configure */
|
||||
#define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11))
|
||||
#define USART_OSB_1BIT CTL2_OSB(1) /*!< 1 sample bit */
|
||||
#define USART_OSB_3BIT CTL2_OSB(0) /*!< 3 sample bits */
|
||||
|
||||
/* USART driver enable polarity mode */
|
||||
#define CTL2_DEP(regval) (BIT(15) & ((uint32_t)(regval) << 15))
|
||||
#define USART_DEP_HIGH CTL2_DEP(0) /*!< DE signal is active high */
|
||||
#define USART_DEP_LOW CTL2_DEP(1) /*!< DE signal is active low */
|
||||
|
||||
/* USART wakeup mode from deep-sleep mode */
|
||||
#define CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20))
|
||||
#define USART_WUM_ADDR CTL2_WUM(0) /*!< WUF active on address match */
|
||||
#define USART_WUM_STARTB CTL2_WUM(2) /*!< WUF active on start bit */
|
||||
#define USART_WUM_RBNE CTL2_WUM(3) /*!< WUF active on RBNE */
|
||||
|
||||
/* USART hardware flow control coherence mode */
|
||||
#define CHC_HCM(regval) (BIT(0) & ((uint32_t)(regval) << 0))
|
||||
#define USART_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */
|
||||
#define USART_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* reset USART */
|
||||
void usart_deinit(uint32_t usart_periph);
|
||||
/* configure USART baud rate value */
|
||||
void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval);
|
||||
/* configure USART parity function */
|
||||
void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg);
|
||||
/* configure USART word length */
|
||||
void usart_word_length_set(uint32_t usart_periph, uint32_t wlen);
|
||||
/* configure USART stop bit length */
|
||||
void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen);
|
||||
/* enable USART */
|
||||
void usart_enable(uint32_t usart_periph);
|
||||
/* disable USART */
|
||||
void usart_disable(uint32_t usart_periph);
|
||||
/* configure USART transmitter */
|
||||
void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig);
|
||||
/* configure USART receiver */
|
||||
void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig);
|
||||
|
||||
/* USART normal mode communication */
|
||||
/* data is transmitted/received with the LSB/MSB first */
|
||||
void usart_data_first_config(uint32_t usart_periph, uint32_t msbf);
|
||||
/* configure USART inverted */
|
||||
void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara);
|
||||
/* enable the USART overrun function */
|
||||
void usart_overrun_enable(uint32_t usart_periph);
|
||||
/* disable the USART overrun function */
|
||||
void usart_overrun_disable(uint32_t usart_periph);
|
||||
/* configure the USART oversample mode */
|
||||
void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp);
|
||||
/* configure sample bit method */
|
||||
void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb);
|
||||
/* enable receiver timeout */
|
||||
void usart_receiver_timeout_enable(uint32_t usart_periph);
|
||||
/* disable receiver timeout */
|
||||
void usart_receiver_timeout_disable(uint32_t usart_periph);
|
||||
/* configure receiver timeout threshold */
|
||||
void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout);
|
||||
/* USART transmit data function */
|
||||
void usart_data_transmit(uint32_t usart_periph, uint32_t data);
|
||||
/* USART receive data function */
|
||||
uint16_t usart_data_receive(uint32_t usart_periph);
|
||||
|
||||
/* multi-processor communication */
|
||||
/* configure address of the USART */
|
||||
void usart_address_config(uint32_t usart_periph, uint8_t addr);
|
||||
/* configure address detection mode */
|
||||
void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod);
|
||||
/* enable mute mode */
|
||||
void usart_mute_mode_enable(uint32_t usart_periph);
|
||||
/* disable mute mode */
|
||||
void usart_mute_mode_disable(uint32_t usart_periph);
|
||||
/* configure wakeup method in mute mode */
|
||||
void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod);
|
||||
|
||||
/* LIN mode communication */
|
||||
/* enable LIN mode */
|
||||
void usart_lin_mode_enable(uint32_t usart_periph);
|
||||
/* disable LIN mode */
|
||||
void usart_lin_mode_disable(uint32_t usart_periph);
|
||||
/* LIN break detection length */
|
||||
void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen);
|
||||
|
||||
/* half-duplex communication */
|
||||
/* enable half-duplex mode */
|
||||
void usart_halfduplex_enable(uint32_t usart_periph);
|
||||
/* disable half-duplex mode */
|
||||
void usart_halfduplex_disable(uint32_t usart_periph);
|
||||
|
||||
/* synchronous communication */
|
||||
/* enable clock */
|
||||
void usart_clock_enable(uint32_t usart_periph);
|
||||
/* disable clock */
|
||||
void usart_clock_disable(uint32_t usart_periph);
|
||||
/* configure USART synchronous mode parameters */
|
||||
void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl);
|
||||
|
||||
/* smartcard communication */
|
||||
/* configure guard time value in smartcard mode */
|
||||
void usart_guard_time_config(uint32_t usart_periph, uint32_t guat);
|
||||
/* enable smartcard mode */
|
||||
void usart_smartcard_mode_enable(uint32_t usart_periph);
|
||||
/* disable smartcard mode */
|
||||
void usart_smartcard_mode_disable(uint32_t usart_periph);
|
||||
/* enable NACK in smartcard mode */
|
||||
void usart_smartcard_mode_nack_enable(uint32_t usart_periph);
|
||||
/* disable NACK in smartcard mode */
|
||||
void usart_smartcard_mode_nack_disable(uint32_t usart_periph);
|
||||
/* enable early NACK in smartcard mode */
|
||||
void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph);
|
||||
/* disable early NACK in smartcard mode */
|
||||
void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph);
|
||||
/* configure smartcard auto-retry number */
|
||||
void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum);
|
||||
/* configure block length */
|
||||
void usart_block_length_config(uint32_t usart_periph, uint32_t bl);
|
||||
|
||||
/* IrDA communication */
|
||||
/* enable IrDA mode */
|
||||
void usart_irda_mode_enable(uint32_t usart_periph);
|
||||
/* disable IrDA mode */
|
||||
void usart_irda_mode_disable(uint32_t usart_periph);
|
||||
/* configure the peripheral clock prescaler */
|
||||
void usart_prescaler_config(uint32_t usart_periph, uint32_t psc);
|
||||
/* configure IrDA low-power */
|
||||
void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp);
|
||||
|
||||
/* hardware flow communication */
|
||||
/* configure hardware flow control RTS */
|
||||
void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig);
|
||||
/* configure hardware flow control CTS */
|
||||
void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig);
|
||||
|
||||
/* coherence control */
|
||||
/* configure hardware flow control coherence mode */
|
||||
void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm);
|
||||
|
||||
/* enable RS485 driver */
|
||||
void usart_rs485_driver_enable(uint32_t usart_periph);
|
||||
/* disable RS485 driver */
|
||||
void usart_rs485_driver_disable(uint32_t usart_periph);
|
||||
/* configure driver enable assertion time */
|
||||
void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime);
|
||||
/* configure driver enable de-assertion time */
|
||||
void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime);
|
||||
/* configure driver enable polarity mode */
|
||||
void usart_depolarity_config(uint32_t usart_periph, uint32_t dep);
|
||||
|
||||
/* USART DMA */
|
||||
/* configure USART DMA for reception */
|
||||
void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd);
|
||||
/* configure USART DMA for transmission */
|
||||
void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd);
|
||||
/* disable DMA on reception error */
|
||||
void usart_reception_error_dma_disable(uint32_t usart_periph);
|
||||
/* enable DMA on reception error */
|
||||
void usart_reception_error_dma_enable(uint32_t usart_periph);
|
||||
|
||||
/* enable USART to wakeup the mcu from deep-sleep mode */
|
||||
void usart_wakeup_enable(uint32_t usart_periph);
|
||||
/* disable USART to wakeup the mcu from deep-sleep mode */
|
||||
void usart_wakeup_disable(uint32_t usart_periph);
|
||||
/* configure the USART wakeup mode from deep-sleep mode */
|
||||
void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum);
|
||||
|
||||
/* USART receive FIFO */
|
||||
/* enable receive FIFO */
|
||||
void usart_receive_fifo_enable(uint32_t usart_periph);
|
||||
/* disable receive FIFO */
|
||||
void usart_receive_fifo_disable(uint32_t usart_periph);
|
||||
/* read receive FIFO counter number */
|
||||
uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph);
|
||||
|
||||
/* flag & interrupt functions */
|
||||
/* get flag in STAT/RFCS register */
|
||||
FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag);
|
||||
/* clear USART status */
|
||||
void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag);
|
||||
/* enable USART interrupt */
|
||||
void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt);
|
||||
/* disable USART interrupt */
|
||||
void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt);
|
||||
/* enable USART command */
|
||||
void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype);
|
||||
/* get USART interrupt and flag status */
|
||||
FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag);
|
||||
/* clear USART interrupt flag */
|
||||
void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum flag);
|
||||
|
||||
#endif /* GD32E23X_USART_H */
|
||||
@@ -0,0 +1,94 @@
|
||||
/*!
|
||||
\file gd32e23x_wwdgt.h
|
||||
\brief definitions for the WWDGT
|
||||
|
||||
\version 2019-02-19, V1.0.0, firmware for GD32E23x
|
||||
\version 2020-12-12, V1.1.0, firmware for GD32E23x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
All rights reserved.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32E23X_WWDGT_H
|
||||
#define GD32E23X_WWDGT_H
|
||||
|
||||
#include "gd32e23x.h"
|
||||
|
||||
/* WWDGT definitions */
|
||||
#define WWDGT WWDGT_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */
|
||||
#define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */
|
||||
#define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* WWDGT_CTL */
|
||||
#define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */
|
||||
#define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */
|
||||
|
||||
/* WWDGT_CFG */
|
||||
#define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */
|
||||
#define WWDGT_CFG_PSC BITS(7,8) /*!< WWDGT prescaler divider value */
|
||||
#define WWDGT_CFG_EWIE BIT(9) /*!< WWDGT early wakeup interrupt enable */
|
||||
|
||||
/* WWDGT_STAT */
|
||||
#define WWDGT_STAT_EWIF BIT(0) /*!< WWDGT early wakeup interrupt flag */
|
||||
|
||||
/* constants definitions */
|
||||
#define CFG_PSC(regval) (BITS(7,8) & ((uint32_t)(regval) << 7U)) /*!< write value to WWDGT_CFG_PSC bit field */
|
||||
#define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0)) /*!< the time base of WWDGT = (PCLK1/4096)/1 */
|
||||
#define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1)) /*!< the time base of WWDGT = (PCLK1/4096)/2 */
|
||||
#define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2)) /*!< the time base of WWDGT = (PCLK1/4096)/4 */
|
||||
#define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3)) /*!< the time base of WWDGT = (PCLK1/4096)/8 */
|
||||
|
||||
/*!< write value to WWDGT_CTL_CNT bit field */
|
||||
#define CTL_CNT(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U))
|
||||
/*!< write value to WWDGT_CFG_WIN bit field */
|
||||
#define CFG_WIN(regval) (BITS(0,6) & ((uint32_t)(regval) << 0U))
|
||||
|
||||
/* function declarations */
|
||||
/* reset the window watchdog timer configuration */
|
||||
void wwdgt_deinit(void);
|
||||
/* start the window watchdog timer counter */
|
||||
void wwdgt_enable(void);
|
||||
|
||||
/* configure the window watchdog timer counter value */
|
||||
void wwdgt_counter_update(uint16_t counter_value);
|
||||
/* configure counter value, window value, and prescaler divider value */
|
||||
void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler);
|
||||
|
||||
/* check early wakeup interrupt state of WWDGT */
|
||||
FlagStatus wwdgt_flag_get(void);
|
||||
/* clear early wakeup interrupt state of WWDGT */
|
||||
void wwdgt_flag_clear(void);
|
||||
/* enable early wakeup interrupt of WWDGT */
|
||||
void wwdgt_interrupt_enable(void);
|
||||
|
||||
#endif /* GD32E23X_WWDGT_H */
|
||||
@@ -0,0 +1,58 @@
|
||||
/*!
|
||||
\file system_gd32e23x.h
|
||||
\brief CMSIS Cortex-M23 Device Peripheral Access Layer Header File for
|
||||
GD32E23x Device Series
|
||||
*/
|
||||
|
||||
/* Copyright (c) 2012 ARM LIMITED
|
||||
|
||||
All rights reserved.
|
||||
Redistribution and use in source and binary forms, with or without
|
||||
modification, are permitted provided that the following conditions are met:
|
||||
- Redistributions of source code must retain the above copyright
|
||||
notice, this list of conditions and the following disclaimer.
|
||||
- Redistributions in binary form must reproduce the above copyright
|
||||
notice, this list of conditions and the following disclaimer in the
|
||||
documentation and/or other materials provided with the distribution.
|
||||
- Neither the name of ARM nor the names of its contributors may be used
|
||||
to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
*
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
---------------------------------------------------------------------------*/
|
||||
|
||||
/* This file refers the CMSIS standard, some adjustments are made according to GigaDevice chips */
|
||||
|
||||
#ifndef SYSTEM_GD32E23X_H
|
||||
#define SYSTEM_GD32E23X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* system clock frequency (core clock) */
|
||||
extern uint32_t SystemCoreClock;
|
||||
|
||||
/* function declarations */
|
||||
/* initialize the system and update the SystemCoreClock variable */
|
||||
extern void SystemInit (void);
|
||||
/* update the SystemCoreClock with current core clock retrieved from cpu registers */
|
||||
extern void SystemCoreClockUpdate (void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* SYSTEM_GD32E23X_H */
|
||||
@@ -0,0 +1,356 @@
|
||||
/*!
|
||||
\file gd32f30x.h
|
||||
\brief general definitions for GD32F30x
|
||||
|
||||
\version 2017-02-10, V1.0.0, firmware for GD32F30x
|
||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x
|
||||
\version 2018-12-25, V2.0.0, firmware for GD32F30x
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F30x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F30X_H
|
||||
#define GD32F30X_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/* define GD32F30x */
|
||||
#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL)
|
||||
/* #define GD32F30X_HD */
|
||||
/* #define GD32F30X_XD */
|
||||
/* #define GD32F30X_CL */
|
||||
#endif /* define GD32F30x */
|
||||
|
||||
#if !defined (GD32F30X_HD) && !defined (GD32F30X_XD) && !defined (GD32F30X_CL)
|
||||
#error "Please select the target GD32F30x device in gd32f30x.h file"
|
||||
#endif /* undefine GD32F30x tip */
|
||||
|
||||
/* define value of high speed crystal oscillator (HXTAL) in Hz */
|
||||
#if !defined HXTAL_VALUE
|
||||
#ifdef GD32F30X_CL
|
||||
#define HXTAL_VALUE ((uint32_t)25000000) /*!< value of the external oscillator in Hz */
|
||||
#else
|
||||
#define HXTAL_VALUE ((uint32_t)8000000) /* !< from 4M to 32M *!< value of the external oscillator in Hz*/
|
||||
#endif /* HXTAL_VALUE */
|
||||
#endif /* high speed crystal oscillator value */
|
||||
|
||||
/* define startup timeout value of high speed crystal oscillator (HXTAL) */
|
||||
#if !defined (HXTAL_STARTUP_TIMEOUT)
|
||||
#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0xFFFF)
|
||||
#endif /* high speed crystal oscillator startup timeout */
|
||||
|
||||
/* define value of internal 48MHz RC oscillator (IRC48M) in Hz */
|
||||
#if !defined (IRC48M_VALUE)
|
||||
#define IRC48M_VALUE ((uint32_t)48000000)
|
||||
#endif /* internal 48MHz RC oscillator value */
|
||||
|
||||
/* define value of internal 8MHz RC oscillator (IRC8M) in Hz */
|
||||
#if !defined (IRC8M_VALUE)
|
||||
#define IRC8M_VALUE ((uint32_t)8000000)
|
||||
#endif /* internal 8MHz RC oscillator value */
|
||||
|
||||
/* define startup timeout value of internal 8MHz RC oscillator (IRC8M) */
|
||||
#if !defined (IRC8M_STARTUP_TIMEOUT)
|
||||
#define IRC8M_STARTUP_TIMEOUT ((uint16_t)0x0500)
|
||||
#endif /* internal 8MHz RC oscillator startup timeout */
|
||||
|
||||
/* define value of internal 40KHz RC oscillator(IRC40K) in Hz */
|
||||
#if !defined (IRC40K_VALUE)
|
||||
#define IRC40K_VALUE ((uint32_t)40000)
|
||||
#endif /* internal 40KHz RC oscillator value */
|
||||
|
||||
/* define value of low speed crystal oscillator (LXTAL)in Hz */
|
||||
#if !defined (LXTAL_VALUE)
|
||||
#define LXTAL_VALUE ((uint32_t)32768)
|
||||
#endif /* low speed crystal oscillator value */
|
||||
|
||||
/* GD32F30x firmware library version number V1.0 */
|
||||
#define __GD32F30x_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __GD32F30x_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
|
||||
#define __GD32F30x_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
|
||||
#define __GD32F30x_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __GD32F30x_STDPERIPH_VERSION ((__GD32F30x_STDPERIPH_VERSION_MAIN << 24)\
|
||||
|(__GD32F30x_STDPERIPH_VERSION_SUB1 << 16)\
|
||||
|(__GD32F30x_STDPERIPH_VERSION_SUB2 << 8)\
|
||||
|(__GD32F30x_STDPERIPH_VERSION_RC))
|
||||
|
||||
/* configuration of the Cortex-M4 processor and core peripherals */
|
||||
#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
|
||||
#define __MPU_PRESENT 1 /*!< GD32F30x provide MPU */
|
||||
#define __NVIC_PRIO_BITS 4 /*!< GD32F30x uses 4 bits for the priority levels */
|
||||
#define __Vendor_SysTickConfig 0 /*!< set to 1 if different sysTick config is used */
|
||||
#define __FPU_PRESENT 1 /*!< FPU present */
|
||||
/* define interrupt number */
|
||||
typedef enum IRQn
|
||||
{
|
||||
/* Cortex-M4 processor exceptions numbers */
|
||||
NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
|
||||
MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */
|
||||
BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */
|
||||
UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */
|
||||
SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */
|
||||
DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */
|
||||
PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */
|
||||
SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */
|
||||
/* interruput numbers */
|
||||
WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */
|
||||
LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
|
||||
TAMPER_IRQn = 2, /*!< tamper through EXTI line detect */
|
||||
RTC_IRQn = 3, /*!< RTC through EXTI line interrupt */
|
||||
FMC_IRQn = 4, /*!< FMC interrupt */
|
||||
RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
|
||||
EXTI0_IRQn = 6, /*!< EXTI line 0 interrupt */
|
||||
EXTI1_IRQn = 7, /*!< EXTI line 1 interrupt */
|
||||
EXTI2_IRQn = 8, /*!< EXTI line 2 interrupt */
|
||||
EXTI3_IRQn = 9, /*!< EXTI line 3 interrupt */
|
||||
EXTI4_IRQn = 10, /*!< EXTI line 4 interrupt */
|
||||
DMA0_Channel0_IRQn = 11, /*!< DMA0 channel0 interrupt */
|
||||
DMA0_Channel1_IRQn = 12, /*!< DMA0 channel1 interrupt */
|
||||
DMA0_Channel2_IRQn = 13, /*!< DMA0 channel2 interrupt */
|
||||
DMA0_Channel3_IRQn = 14, /*!< DMA0 channel3 interrupt */
|
||||
DMA0_Channel4_IRQn = 15, /*!< DMA0 channel4 interrupt */
|
||||
DMA0_Channel5_IRQn = 16, /*!< DMA0 channel5 interrupt */
|
||||
DMA0_Channel6_IRQn = 17, /*!< DMA0 channel6 interrupt */
|
||||
ADC0_1_IRQn = 18, /*!< ADC0 and ADC1 interrupt */
|
||||
#ifdef GD32F30X_HD
|
||||
USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
|
||||
USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
|
||||
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */
|
||||
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */
|
||||
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
||||
TIMER0_BRK_IRQn = 24, /*!< TIMER0 break interrupt */
|
||||
TIMER0_UP_IRQn = 25, /*!< TIMER0 update interrupt */
|
||||
TIMER0_TRG_CMT_IRQn = 26, /*!< TIMER0 trigger and commutation interrupt */
|
||||
TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
|
||||
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
||||
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
||||
TIMER3_IRQn = 30, /*!< TIMER3 interrupt */
|
||||
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
||||
SPI1_IRQn = 36, /*!< SPI1 interrupt */
|
||||
USART0_IRQn = 37, /*!< USART0 interrupt */
|
||||
USART1_IRQn = 38, /*!< USART1 interrupt */
|
||||
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||||
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
|
||||
USBD_WKUP_IRQn = 42, /*!< USBD Wakeup interrupt */
|
||||
TIMER7_BRK_IRQn = 43, /*!< TIMER7 break interrupt */
|
||||
TIMER7_UP_IRQn = 44, /*!< TIMER7 update interrupt */
|
||||
TIMER7_TRG_CMT_IRQn = 45, /*!< TIMER7 trigger and commutation interrupt */
|
||||
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
|
||||
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
|
||||
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
||||
SDIO_IRQn = 49, /*!< SDIO global interrupt */
|
||||
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
||||
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
|
||||
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
||||
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
||||
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
|
||||
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
||||
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global Interrupt */
|
||||
#endif /* GD32F30X_HD */
|
||||
|
||||
#ifdef GD32F30X_XD
|
||||
USBD_HP_CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
|
||||
USBD_LP_CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
|
||||
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */
|
||||
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */
|
||||
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
||||
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupt */
|
||||
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupt */
|
||||
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupt */
|
||||
TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
|
||||
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
||||
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
||||
TIMER3_IRQn = 30, /*!< TIMER3 interrupt */
|
||||
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
||||
SPI1_IRQn = 36, /*!< SPI1 interrupt */
|
||||
USART0_IRQn = 37, /*!< USART0 interrupt */
|
||||
USART1_IRQn = 38, /*!< USART1 interrupt */
|
||||
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||||
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
|
||||
USBD_WKUP_IRQn = 42, /*!< USBD wakeup interrupt */
|
||||
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupt */
|
||||
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupt */
|
||||
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupt */
|
||||
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
|
||||
ADC2_IRQn = 47, /*!< ADC2 global interrupt */
|
||||
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
||||
SDIO_IRQn = 49, /*!< SDIO global interrupt */
|
||||
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
||||
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
|
||||
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
||||
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
||||
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
|
||||
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
||||
DMA1_Channel3_Channel4_IRQn = 59, /*!< DMA1 channel3 and channel4 global interrupt */
|
||||
#endif /* GD32F30X_XD */
|
||||
|
||||
#ifdef GD32F30X_CL
|
||||
CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupt */
|
||||
CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupt */
|
||||
CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupt */
|
||||
CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupt */
|
||||
EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
|
||||
TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 break and TIMER8 interrupt */
|
||||
TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 update and TIMER9 interrupt */
|
||||
TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 trigger and commutation and TIMER10 interrupt */
|
||||
TIMER0_Channel_IRQn = 27, /*!< TIMER0 channel capture compare interrupt */
|
||||
TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
|
||||
TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
|
||||
TIMER3_IRQn = 30, /*!< TIMER3 interrupt */
|
||||
I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
|
||||
I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
|
||||
I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
|
||||
I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
|
||||
SPI0_IRQn = 35, /*!< SPI0 interrupt */
|
||||
SPI1_IRQn = 36, /*!< SPI1 interrupt */
|
||||
USART0_IRQn = 37, /*!< USART0 interrupt */
|
||||
USART1_IRQn = 38, /*!< USART1 interrupt */
|
||||
USART2_IRQn = 39, /*!< USART2 interrupt */
|
||||
EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
|
||||
RTC_Alarm_IRQn = 41, /*!< RTC alarm interrupt */
|
||||
USBFS_WKUP_IRQn = 42, /*!< USBFS wakeup interrupt */
|
||||
TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 break and TIMER11 interrupt */
|
||||
TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 update and TIMER12 interrupt */
|
||||
TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 trigger and commutation and TIMER13 interrupt */
|
||||
TIMER7_Channel_IRQn = 46, /*!< TIMER7 channel capture compare interrupt */
|
||||
EXMC_IRQn = 48, /*!< EXMC global interrupt */
|
||||
TIMER4_IRQn = 50, /*!< TIMER4 global interrupt */
|
||||
SPI2_IRQn = 51, /*!< SPI2 global interrupt */
|
||||
UART3_IRQn = 52, /*!< UART3 global interrupt */
|
||||
UART4_IRQn = 53, /*!< UART4 global interrupt */
|
||||
TIMER5_IRQn = 54, /*!< TIMER5 global interrupt */
|
||||
TIMER6_IRQn = 55, /*!< TIMER6 global interrupt */
|
||||
DMA1_Channel0_IRQn = 56, /*!< DMA1 channel0 global interrupt */
|
||||
DMA1_Channel1_IRQn = 57, /*!< DMA1 channel1 global interrupt */
|
||||
DMA1_Channel2_IRQn = 58, /*!< DMA1 channel2 global interrupt */
|
||||
DMA1_Channel3_IRQn = 59, /*!< DMA1 channel3 global interrupt */
|
||||
DMA1_Channel4_IRQn = 60, /*!< DMA1 channel3 global interrupt */
|
||||
ENET_IRQn = 61, /*!< ENET global interrupt */
|
||||
ENET_WKUP_IRQn = 62, /*!< ENET Wakeup interrupt */
|
||||
CAN1_TX_IRQn = 63, /*!< CAN1 TX interrupt */
|
||||
CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 interrupt */
|
||||
CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 interrupt */
|
||||
CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC interrupt */
|
||||
USBFS_IRQn = 67, /*!< USBFS global interrupt */
|
||||
#endif /* GD32F30X_CL */
|
||||
|
||||
} IRQn_Type;
|
||||
|
||||
/* includes */
|
||||
#include "core_cm4.h"
|
||||
#include "system_gd32f30x.h"
|
||||
#include <stdint.h>
|
||||
|
||||
/* enum definitions */
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus;
|
||||
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
|
||||
|
||||
/* bit operations */
|
||||
#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
|
||||
#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
|
||||
#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
|
||||
#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
|
||||
#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
|
||||
#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
|
||||
|
||||
/* main flash and SRAM memory map */
|
||||
#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
|
||||
#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
|
||||
#define OB_BASE ((uint32_t)0x1FFFF800U) /*!< OB base address */
|
||||
#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
|
||||
#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
|
||||
|
||||
/* peripheral memory map */
|
||||
#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
|
||||
#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
|
||||
#define AHB1_BUS_BASE ((uint32_t)0x40018000U) /*!< ahb1 base address */
|
||||
#define AHB3_BUS_BASE ((uint32_t)0x60000000U) /*!< ahb3 base address */
|
||||
|
||||
/* advanced peripheral bus 1 memory map */
|
||||
#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
|
||||
#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
|
||||
#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
|
||||
#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
|
||||
#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
|
||||
#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
|
||||
#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
|
||||
#define USBD_BASE (APB1_BUS_BASE + 0x00005C00U) /*!< USBD base address */
|
||||
#define USBD_RAM_BASE (APB1_BUS_BASE + 0x00006000U) /*!< USBD RAM base address */
|
||||
#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
|
||||
#define BKP_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< BKP base address */
|
||||
#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
|
||||
#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
|
||||
#define CTC_BASE (APB1_BUS_BASE + 0x0000C800U) /*!< CTC base address */
|
||||
|
||||
/* advanced peripheral bus 2 memory map */
|
||||
#define AFIO_BASE (APB2_BUS_BASE + 0x00000000U) /*!< AFIO base address */
|
||||
#define EXTI_BASE (APB2_BUS_BASE + 0x00000400U) /*!< EXTI base address */
|
||||
#define GPIO_BASE (APB2_BUS_BASE + 0x00000800U) /*!< GPIO base address */
|
||||
#define ADC_BASE (APB2_BUS_BASE + 0x00002400U) /*!< ADC base address */
|
||||
|
||||
/* advanced high performance bus 1 memory map */
|
||||
#define SDIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< SDIO base address */
|
||||
#define DMA_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< DMA base address */
|
||||
#define RCU_BASE (AHB1_BUS_BASE + 0x00009000U) /*!< RCU base address */
|
||||
#define FMC_BASE (AHB1_BUS_BASE + 0x0000A000U) /*!< FMC base address */
|
||||
#define CRC_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< CRC base address */
|
||||
#define ENET_BASE (AHB1_BUS_BASE + 0x00010000U) /*!< ENET base address */
|
||||
#define USBFS_BASE (AHB1_BUS_BASE + 0x0FFE8000U) /*!< USBFS base address */
|
||||
|
||||
/* define marco USE_STDPERIPH_DRIVER */
|
||||
#if !defined USE_STDPERIPH_DRIVER
|
||||
#define USE_STDPERIPH_DRIVER
|
||||
#endif
|
||||
#ifdef USE_STDPERIPH_DRIVER
|
||||
#include "gd32f30x_libopt.h"
|
||||
#endif /* USE_STDPERIPH_DRIVER */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
@@ -0,0 +1,403 @@
|
||||
/*!
|
||||
\file gd32f30x_adc.h
|
||||
\brief definitions for the ADC
|
||||
|
||||
\version 2017-02-10, V1.0.0, firmware for GD32F30x
|
||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x
|
||||
\version 2018-12-25, V2.0.0, firmware for GD32F30x
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F30x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F30X_ADC_H
|
||||
#define GD32F30X_ADC_H
|
||||
|
||||
#include "gd32f30x.h"
|
||||
|
||||
/* ADC definitions */
|
||||
#define ADC0 ADC_BASE
|
||||
#define ADC1 (ADC_BASE + 0x400U)
|
||||
#if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
|
||||
#define ADC2 (ADC_BASE + 0x1800U)
|
||||
#endif
|
||||
|
||||
/* registers definitions */
|
||||
#define ADC_STAT(adcx) REG32((adcx) + 0x00U) /*!< ADC status register */
|
||||
#define ADC_CTL0(adcx) REG32((adcx) + 0x04U) /*!< ADC control register 0 */
|
||||
#define ADC_CTL1(adcx) REG32((adcx) + 0x08U) /*!< ADC control register 1 */
|
||||
#define ADC_SAMPT0(adcx) REG32((adcx) + 0x0CU) /*!< ADC sampling time register 0 */
|
||||
#define ADC_SAMPT1(adcx) REG32((adcx) + 0x10U) /*!< ADC sampling time register 1 */
|
||||
#define ADC_IOFF0(adcx) REG32((adcx) + 0x14U) /*!< ADC inserted channel data offset register 0 */
|
||||
#define ADC_IOFF1(adcx) REG32((adcx) + 0x18U) /*!< ADC inserted channel data offset register 1 */
|
||||
#define ADC_IOFF2(adcx) REG32((adcx) + 0x1CU) /*!< ADC inserted channel data offset register 2 */
|
||||
#define ADC_IOFF3(adcx) REG32((adcx) + 0x20U) /*!< ADC inserted channel data offset register 3 */
|
||||
#define ADC_WDHT(adcx) REG32((adcx) + 0x24U) /*!< ADC watchdog high threshold register */
|
||||
#define ADC_WDLT(adcx) REG32((adcx) + 0x28U) /*!< ADC watchdog low threshold register */
|
||||
#define ADC_RSQ0(adcx) REG32((adcx) + 0x2CU) /*!< ADC regular sequence register 0 */
|
||||
#define ADC_RSQ1(adcx) REG32((adcx) + 0x30U) /*!< ADC regular sequence register 1 */
|
||||
#define ADC_RSQ2(adcx) REG32((adcx) + 0x34U) /*!< ADC regular sequence register 2 */
|
||||
#define ADC_ISQ(adcx) REG32((adcx) + 0x38U) /*!< ADC inserted sequence register */
|
||||
#define ADC_IDATA0(adcx) REG32((adcx) + 0x3CU) /*!< ADC inserted data register 0 */
|
||||
#define ADC_IDATA1(adcx) REG32((adcx) + 0x40U) /*!< ADC inserted data register 1 */
|
||||
#define ADC_IDATA2(adcx) REG32((adcx) + 0x44U) /*!< ADC inserted data register 2 */
|
||||
#define ADC_IDATA3(adcx) REG32((adcx) + 0x48U) /*!< ADC inserted data register 3 */
|
||||
#define ADC_RDATA(adcx) REG32((adcx) + 0x4CU) /*!< ADC regular data register */
|
||||
#define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x80U) /*!< ADC oversampling control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* ADC_STAT */
|
||||
#define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */
|
||||
#define ADC_STAT_EOC BIT(1) /*!< end of conversion */
|
||||
#define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */
|
||||
#define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */
|
||||
#define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */
|
||||
|
||||
/* ADC_CTL0 */
|
||||
#define ADC_CTL0_WDCHSEL BITS(0,4) /*!< analog watchdog channel select bits */
|
||||
#define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */
|
||||
#define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */
|
||||
#define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */
|
||||
#define ADC_CTL0_SM BIT(8) /*!< scan mode */
|
||||
#define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */
|
||||
#define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */
|
||||
#define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */
|
||||
#define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */
|
||||
#define ADC_CTL0_DISNUM BITS(13,15) /*!< discontinuous mode channel count */
|
||||
#define ADC_CTL0_SYNCM BITS(16,19) /*!< sync mode selection */
|
||||
#define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */
|
||||
#define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */
|
||||
#define ADC_CTL0_DRES BITS(24,25) /*!< ADC data resolution */
|
||||
|
||||
/* ADC_CTL1 */
|
||||
#define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */
|
||||
#define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */
|
||||
#define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */
|
||||
#define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */
|
||||
#define ADC_CTL1_DMA BIT(8) /*!< direct memory access mode */
|
||||
#define ADC_CTL1_DAL BIT(11) /*!< data alignment */
|
||||
#define ADC_CTL1_ETSIC BITS(12,14) /*!< external trigger select for inserted channel */
|
||||
#define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */
|
||||
#define ADC_CTL1_ETSRC BITS(17,19) /*!< external trigger select for regular channel */
|
||||
#define ADC_CTL1_ETERC BIT(20) /*!< external trigger conversion mode for inserted channels */
|
||||
#define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */
|
||||
#define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */
|
||||
#define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */
|
||||
|
||||
/* ADC_SAMPTx x=0..1 */
|
||||
#define ADC_SAMPTX_SPTN BITS(0,2) /*!< channel x sample time selection */
|
||||
|
||||
/* ADC_IOFFx x=0..3 */
|
||||
#define ADC_IOFFX_IOFF BITS(0,11) /*!< data offset for inserted channel x */
|
||||
|
||||
/* ADC_WDHT */
|
||||
#define ADC_WDHT_WDHT BITS(0,11) /*!< analog watchdog high threshold */
|
||||
|
||||
/* ADC_WDLT */
|
||||
#define ADC_WDLT_WDLT BITS(0,11) /*!< analog watchdog low threshold */
|
||||
|
||||
/* ADC_RSQx */
|
||||
#define ADC_RSQX_RSQN BITS(0,4) /*!< x conversion in regular sequence */
|
||||
#define ADC_RSQ0_RL BITS(20,23) /*!< regular channel sequence length */
|
||||
|
||||
/* ADC_ISQ */
|
||||
#define ADC_ISQ_ISQN BITS(0,4) /*!< x conversion in regular sequence */
|
||||
#define ADC_ISQ_IL BITS(20,21) /*!< inserted sequence length */
|
||||
|
||||
/* ADC_IDATAx x=0..3*/
|
||||
#define ADC_IDATAX_IDATAN BITS(0,15) /*!< inserted data x */
|
||||
|
||||
/* ADC_RDATA */
|
||||
#define ADC_RDATA_RDATA BITS(0,15) /*!< regular data */
|
||||
#define ADC_RDATA_ADC1RDTR BITS(16,31) /*!< ADC1 regular channel data */
|
||||
|
||||
/* ADC_OVSAMPCTL */
|
||||
#define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */
|
||||
#define ADC_OVSAMPCTL_OVSR BITS(2,4) /*!< oversampling ratio */
|
||||
#define ADC_OVSAMPCTL_OVSS BITS(5,8) /*!< oversampling shift */
|
||||
#define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */
|
||||
#define ADC_OVSAMPCTL_DRES BITS(12,13) /*!< oversampling shift */
|
||||
|
||||
|
||||
/* constants definitions */
|
||||
/* ADC status flag */
|
||||
#define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */
|
||||
#define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */
|
||||
#define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */
|
||||
#define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */
|
||||
#define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */
|
||||
|
||||
/* adc_ctl0 register value */
|
||||
#define CTL0_DISNUM(regval) (BITS(13,15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */
|
||||
|
||||
/* ADC special function definitions */
|
||||
#define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */
|
||||
#define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */
|
||||
#define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */
|
||||
|
||||
/* ADC synchronization mode */
|
||||
#define CTL0_SYNCM(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */
|
||||
#define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */
|
||||
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */
|
||||
#define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */
|
||||
#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */
|
||||
#define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */
|
||||
#define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */
|
||||
#define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */
|
||||
#define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */
|
||||
#define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */
|
||||
#define ADC_DAUL_INSERTED_TRRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */
|
||||
|
||||
/* ADC data alignment */
|
||||
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */
|
||||
#define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */
|
||||
|
||||
/* ADC external trigger select for regular channel */
|
||||
#define CTL1_ETSRC(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< timer 0 CC0 event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< timer 0 CC1 event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< timer 1 CC1 event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< timer 2 TRGO event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< timer 3 CC3 event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6) /*!< timer 7 TRGO event select */
|
||||
#define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */
|
||||
#define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */
|
||||
|
||||
#define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0) /*!< timer 2 CC0 event select */
|
||||
#define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1) /*!< timer 1 CC2 event select */
|
||||
#define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< timer 0 CC2 event select */
|
||||
#define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3) /*!< timer 7 CC0 event select */
|
||||
#define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4) /*!< timer 7 TRGO event select */
|
||||
#define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5) /*!< timer 4 CC0 event select */
|
||||
#define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< timer 4 CC2 event select */
|
||||
|
||||
/* ADC external trigger select for inserted channel */
|
||||
#define CTL1_ETSIC(regval) (BITS(12,14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< timer 0 TRGO event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< timer 0 CC3 event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< timer 1 TRGO event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< timer 1 CC0 event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< timer 2 CC3 event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< timer 3 TRGO event select */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */
|
||||
#define ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6) /*!< timer 7 CC3 event select */
|
||||
#define ADC0_1_2_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */
|
||||
|
||||
#define ADC2_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< timer 0 TRGO event select */
|
||||
#define ADC2_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< timer 0 CC3 event select */
|
||||
#define ADC2_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(2) /*!< timer 3 CC2 event select */
|
||||
#define ADC2_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(3) /*!< timer 7 CC1 event select */
|
||||
#define ADC2_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(4) /*!< timer 7 CC3 event select */
|
||||
#define ADC2_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(5) /*!< timer 4 TRGO event select */
|
||||
#define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6) /*!< timer 4 CC3 event select */
|
||||
|
||||
/* ADC channel sample time */
|
||||
#define SAMPTX_SPT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */
|
||||
#define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */
|
||||
#define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */
|
||||
|
||||
/* adc_ioffx register value */
|
||||
#define IOFFX_IOFF(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */
|
||||
|
||||
/* adc_wdht register value */
|
||||
#define WDHT_WDHT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */
|
||||
|
||||
/* adc_wdlt register value */
|
||||
#define WDLT_WDLT(regval) (BITS(0,11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */
|
||||
|
||||
/* adc_rsqx register value */
|
||||
#define RSQ0_RL(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */
|
||||
|
||||
/* adc_isq register value */
|
||||
#define ISQ_IL(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */
|
||||
|
||||
/* adc_ovsampctl register value */
|
||||
/* ADC resolution */
|
||||
#define OVSAMPCTL_DRES(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */
|
||||
#define ADC_RESOLUTION_12B OVSAMPCTL_DRES(0) /*!< 12-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_10B OVSAMPCTL_DRES(1) /*!< 10-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_8B OVSAMPCTL_DRES(2) /*!< 8-bit ADC resolution */
|
||||
#define ADC_RESOLUTION_6B OVSAMPCTL_DRES(3) /*!< 6-bit ADC resolution */
|
||||
|
||||
/* oversampling shift */
|
||||
#define OVSAMPCTL_OVSS(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */
|
||||
#define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */
|
||||
#define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */
|
||||
|
||||
/* oversampling ratio */
|
||||
#define OVSAMPCTL_OVSR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */
|
||||
#define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */
|
||||
|
||||
/* triggered oversampling */
|
||||
#define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */
|
||||
#define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */
|
||||
|
||||
/* ADC channel group definitions */
|
||||
#define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< adc regular channel group */
|
||||
#define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< adc inserted channel group */
|
||||
#define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */
|
||||
|
||||
#define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */
|
||||
|
||||
/* ADC inserted channel definitions */
|
||||
#define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< adc inserted channel 0 */
|
||||
#define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< adc inserted channel 1 */
|
||||
#define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< adc inserted channel 2 */
|
||||
#define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< adc inserted channel 3 */
|
||||
|
||||
/* ADC channel definitions */
|
||||
#define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */
|
||||
#define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */
|
||||
#define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */
|
||||
#define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */
|
||||
#define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */
|
||||
#define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */
|
||||
#define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */
|
||||
#define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */
|
||||
#define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */
|
||||
#define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */
|
||||
#define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */
|
||||
#define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */
|
||||
#define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */
|
||||
#define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */
|
||||
#define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */
|
||||
#define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */
|
||||
#define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */
|
||||
#define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */
|
||||
|
||||
/* ADC interrupt */
|
||||
#define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */
|
||||
#define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */
|
||||
#define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */
|
||||
|
||||
/* ADC interrupt flag */
|
||||
#define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt flag */
|
||||
#define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */
|
||||
#define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */
|
||||
|
||||
/* function declarations */
|
||||
/* reset ADC */
|
||||
void adc_deinit(uint32_t adc_periph);
|
||||
/* enable ADC interface */
|
||||
void adc_enable(uint32_t adc_periph);
|
||||
/* disable ADC interface */
|
||||
void adc_disable(uint32_t adc_periph);
|
||||
/* ADC calibration and reset calibration */
|
||||
void adc_calibration_enable(uint32_t adc_periph);
|
||||
/* enable DMA request */
|
||||
void adc_dma_mode_enable(uint32_t adc_periph);
|
||||
/* disable DMA request */
|
||||
void adc_dma_mode_disable(uint32_t adc_periph);
|
||||
/* enable the temperature sensor and Vrefint channel */
|
||||
void adc_tempsensor_vrefint_enable(void);
|
||||
/* disable the temperature sensor and Vrefint channel */
|
||||
void adc_tempsensor_vrefint_disable(void);
|
||||
|
||||
/* configure ADC resolution */
|
||||
void adc_resolution_config(uint32_t adc_periph , uint32_t resolution);
|
||||
/* configure ADC discontinuous mode */
|
||||
void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length);
|
||||
|
||||
/* configure the ADC mode */
|
||||
void adc_mode_config(uint32_t mode);
|
||||
/* enable or disable ADC special function */
|
||||
void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue);
|
||||
/* configure ADC data alignment */
|
||||
void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment);
|
||||
/* configure the length of regular channel group or inserted channel group */
|
||||
void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length);
|
||||
/* configure ADC regular channel */
|
||||
void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
|
||||
/* configure ADC inserted channel */
|
||||
void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time);
|
||||
/* configure ADC inserted channel offset */
|
||||
void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset);
|
||||
/* enable ADC external trigger */
|
||||
void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue);
|
||||
/* configure ADC external trigger source */
|
||||
void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source);
|
||||
/* enable ADC software trigger */
|
||||
void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group);
|
||||
|
||||
/* read ADC regular group data register */
|
||||
uint16_t adc_regular_data_read(uint32_t adc_periph);
|
||||
/* read ADC inserted group data register */
|
||||
uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel);
|
||||
/* read the last ADC0 and ADC1 conversion result data in sync mode */
|
||||
uint32_t adc_sync_mode_convert_value_read(void);
|
||||
|
||||
/* get the ADC flag bits */
|
||||
FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag);
|
||||
/* clear the ADC flag bits */
|
||||
void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag);
|
||||
/* get the ADC interrupt bits */
|
||||
FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt);
|
||||
/* clear the ADC flag */
|
||||
void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt);
|
||||
/* enable ADC interrupt */
|
||||
void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt);
|
||||
/* disable ADC interrupt */
|
||||
void adc_interrupt_disable(uint32_t adc_periph , uint32_t adc_interrupt);
|
||||
|
||||
/* configure ADC analog watchdog single channel */
|
||||
void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel);
|
||||
/* configure ADC analog watchdog group channel */
|
||||
void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group);
|
||||
/* disable ADC analog watchdog */
|
||||
void adc_watchdog_disable(uint32_t adc_periph);
|
||||
/* configure ADC analog watchdog threshold */
|
||||
void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold);
|
||||
|
||||
/* configure ADC oversample mode */
|
||||
void adc_oversample_mode_config(uint32_t adc_periph , uint32_t mode , uint16_t shift , uint8_t ratio);
|
||||
/* enable ADC oversample mode */
|
||||
void adc_oversample_mode_enable(uint32_t adc_periph);
|
||||
/* disable ADC oversample mode */
|
||||
void adc_oversample_mode_disable(uint32_t adc_periph);
|
||||
#endif /* GD32F30X_ADC_H */
|
||||
@@ -0,0 +1,244 @@
|
||||
/*!
|
||||
\file gd32f30x_bkp.h
|
||||
\brief definitions for the BKP
|
||||
|
||||
\version 2017-02-10, V1.0.0, firmware for GD32F30x
|
||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x
|
||||
\version 2018-12-25, V2.0.0, firmware for GD32F30x
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F30x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F30X_BKP_H
|
||||
#define GD32F30X_BKP_H
|
||||
|
||||
#include "gd32f30x.h"
|
||||
|
||||
/* BKP definitions */
|
||||
#define BKP BKP_BASE /*!< BKP base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define BKP_DATA0 REG16((BKP) + 0x04U) /*!< BKP data register 0 */
|
||||
#define BKP_DATA1 REG16((BKP) + 0x08U) /*!< BKP data register 1 */
|
||||
#define BKP_DATA2 REG16((BKP) + 0x0CU) /*!< BKP data register 2 */
|
||||
#define BKP_DATA3 REG16((BKP) + 0x10U) /*!< BKP data register 3 */
|
||||
#define BKP_DATA4 REG16((BKP) + 0x14U) /*!< BKP data register 4 */
|
||||
#define BKP_DATA5 REG16((BKP) + 0x18U) /*!< BKP data register 5 */
|
||||
#define BKP_DATA6 REG16((BKP) + 0x1CU) /*!< BKP data register 6 */
|
||||
#define BKP_DATA7 REG16((BKP) + 0x20U) /*!< BKP data register 7 */
|
||||
#define BKP_DATA8 REG16((BKP) + 0x24U) /*!< BKP data register 8 */
|
||||
#define BKP_DATA9 REG16((BKP) + 0x28U) /*!< BKP data register 9 */
|
||||
#define BKP_DATA10 REG16((BKP) + 0x40U) /*!< BKP data register 10 */
|
||||
#define BKP_DATA11 REG16((BKP) + 0x44U) /*!< BKP data register 11 */
|
||||
#define BKP_DATA12 REG16((BKP) + 0x48U) /*!< BKP data register 12 */
|
||||
#define BKP_DATA13 REG16((BKP) + 0x4CU) /*!< BKP data register 13 */
|
||||
#define BKP_DATA14 REG16((BKP) + 0x50U) /*!< BKP data register 14 */
|
||||
#define BKP_DATA15 REG16((BKP) + 0x54U) /*!< BKP data register 15 */
|
||||
#define BKP_DATA16 REG16((BKP) + 0x58U) /*!< BKP data register 16 */
|
||||
#define BKP_DATA17 REG16((BKP) + 0x5CU) /*!< BKP data register 17 */
|
||||
#define BKP_DATA18 REG16((BKP) + 0x60U) /*!< BKP data register 18 */
|
||||
#define BKP_DATA19 REG16((BKP) + 0x64U) /*!< BKP data register 19 */
|
||||
#define BKP_DATA20 REG16((BKP) + 0x68U) /*!< BKP data register 20 */
|
||||
#define BKP_DATA21 REG16((BKP) + 0x6CU) /*!< BKP data register 21 */
|
||||
#define BKP_DATA22 REG16((BKP) + 0x70U) /*!< BKP data register 22 */
|
||||
#define BKP_DATA23 REG16((BKP) + 0x74U) /*!< BKP data register 23 */
|
||||
#define BKP_DATA24 REG16((BKP) + 0x78U) /*!< BKP data register 24 */
|
||||
#define BKP_DATA25 REG16((BKP) + 0x7CU) /*!< BKP data register 25 */
|
||||
#define BKP_DATA26 REG16((BKP) + 0x80U) /*!< BKP data register 26 */
|
||||
#define BKP_DATA27 REG16((BKP) + 0x84U) /*!< BKP data register 27 */
|
||||
#define BKP_DATA28 REG16((BKP) + 0x88U) /*!< BKP data register 28 */
|
||||
#define BKP_DATA29 REG16((BKP) + 0x8CU) /*!< BKP data register 29 */
|
||||
#define BKP_DATA30 REG16((BKP) + 0x90U) /*!< BKP data register 30 */
|
||||
#define BKP_DATA31 REG16((BKP) + 0x94U) /*!< BKP data register 31 */
|
||||
#define BKP_DATA32 REG16((BKP) + 0x98U) /*!< BKP data register 32 */
|
||||
#define BKP_DATA33 REG16((BKP) + 0x9CU) /*!< BKP data register 33 */
|
||||
#define BKP_DATA34 REG16((BKP) + 0xA0U) /*!< BKP data register 34 */
|
||||
#define BKP_DATA35 REG16((BKP) + 0xA4U) /*!< BKP data register 35 */
|
||||
#define BKP_DATA36 REG16((BKP) + 0xA8U) /*!< BKP data register 36 */
|
||||
#define BKP_DATA37 REG16((BKP) + 0xACU) /*!< BKP data register 37 */
|
||||
#define BKP_DATA38 REG16((BKP) + 0xB0U) /*!< BKP data register 38 */
|
||||
#define BKP_DATA39 REG16((BKP) + 0xB4U) /*!< BKP data register 39 */
|
||||
#define BKP_DATA40 REG16((BKP) + 0xB8U) /*!< BKP data register 40 */
|
||||
#define BKP_DATA41 REG16((BKP) + 0xBCU) /*!< BKP data register 41 */
|
||||
#define BKP_OCTL REG16((BKP) + 0x2CU) /*!< RTC signal output control register */
|
||||
#define BKP_TPCTL REG16((BKP) + 0x30U) /*!< tamper pin control register */
|
||||
#define BKP_TPCS REG16((BKP) + 0x34U) /*!< tamper control and status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* BKP_DATA */
|
||||
#define BKP_DATA BITS(0,15) /*!< backup data */
|
||||
|
||||
/* BKP_OCTL */
|
||||
#define BKP_OCTL_RCCV BITS(0,6) /*!< RTC clock calibration value */
|
||||
#define BKP_OCTL_COEN BIT(7) /*!< RTC clock calibration output enable */
|
||||
#define BKP_OCTL_ASOEN BIT(8) /*!< RTC alarm or second signal output enable */
|
||||
#define BKP_OCTL_ROSEL BIT(9) /*!< RTC output selection */
|
||||
#define BKP_OCTL_CCOSEL BIT(14) /*!< RTC clock output selection */
|
||||
#define BKP_OCTL_CALDIR BIT(15) /*!< RTC clock calibration direction */
|
||||
|
||||
/* BKP_TPCTL */
|
||||
#define BKP_TPCTL_TPEN BIT(0) /*!< tamper detection enable */
|
||||
#define BKP_TPCTL_TPAL BIT(1) /*!< tamper pin active level */
|
||||
|
||||
/* BKP_TPCS */
|
||||
#define BKP_TPCS_TER BIT(0) /*!< tamper event reset */
|
||||
#define BKP_TPCS_TIR BIT(1) /*!< tamper interrupt reset */
|
||||
#define BKP_TPCS_TPIE BIT(2) /*!< tamper interrupt enable */
|
||||
#define BKP_TPCS_TEF BIT(8) /*!< tamper event flag */
|
||||
#define BKP_TPCS_TIF BIT(9) /*!< tamper interrupt flag */
|
||||
|
||||
/* constants definitions */
|
||||
/* BKP register */
|
||||
#define BKP_DATA0_9(number) REG16((BKP) + 0x04U + (number) * 0x04U)
|
||||
#define BKP_DATA10_41(number) REG16((BKP) + 0x40U + ((number)-10U) * 0x04U)
|
||||
|
||||
/* get data of BKP data register */
|
||||
#define BKP_DATA_GET(regval) GET_BITS((uint32_t)(regval), 0, 15)
|
||||
|
||||
/* RTC clock calibration value */
|
||||
#define OCTL_RCCV(regval) (BITS(0,6) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* RTC output selection */
|
||||
#define RTC_OUTPUT_ALARM_PULSE ((uint16_t)0x0000U) /*!< RTC alarm pulse is selected as the RTC output */
|
||||
#define RTC_OUTPUT_SECOND_PULSE ((uint16_t)0x0200U) /*!< RTC second pulse is selected as the RTC output */
|
||||
|
||||
/* RTC clock output selection */
|
||||
#define RTC_CLOCK_DIV_64 ((uint16_t)0x0000U) /*!< RTC clock div 64 */
|
||||
#define RTC_CLOCK_DIV_1 ((uint16_t)0x4000U) /*!< RTC clock div 1 */
|
||||
|
||||
/* RTC clock calibration direction */
|
||||
#define RTC_CLOCK_SLOWED_DOWN ((uint16_t)0x0000U) /*!< RTC clock slow down */
|
||||
#define RTC_CLOCK_SPEED_UP ((uint16_t)0x8000U) /*!< RTC clock speed up */
|
||||
|
||||
/* tamper pin active level */
|
||||
#define TAMPER_PIN_ACTIVE_HIGH ((uint16_t)0x0000U) /*!< the tamper pin is active high */
|
||||
#define TAMPER_PIN_ACTIVE_LOW ((uint16_t)0x0002U) /*!< the tamper pin is active low */
|
||||
|
||||
/* tamper flag */
|
||||
#define BKP_FLAG_TAMPER BKP_TPCS_TEF /*!< tamper event flag */
|
||||
|
||||
/* tamper interrupt flag */
|
||||
#define BKP_INT_FLAG_TAMPER BKP_TPCS_TIF /*!< tamper interrupt flag */
|
||||
|
||||
/* BKP data register number */
|
||||
typedef enum
|
||||
{
|
||||
BKP_DATA_0 = 1, /*!< BKP data register 0 */
|
||||
BKP_DATA_1, /*!< BKP data register 1 */
|
||||
BKP_DATA_2, /*!< BKP data register 2 */
|
||||
BKP_DATA_3, /*!< BKP data register 3 */
|
||||
BKP_DATA_4, /*!< BKP data register 4 */
|
||||
BKP_DATA_5, /*!< BKP data register 5 */
|
||||
BKP_DATA_6, /*!< BKP data register 6 */
|
||||
BKP_DATA_7, /*!< BKP data register 7 */
|
||||
BKP_DATA_8, /*!< BKP data register 8 */
|
||||
BKP_DATA_9, /*!< BKP data register 9 */
|
||||
BKP_DATA_10, /*!< BKP data register 10 */
|
||||
BKP_DATA_11, /*!< BKP data register 11 */
|
||||
BKP_DATA_12, /*!< BKP data register 12 */
|
||||
BKP_DATA_13, /*!< BKP data register 13 */
|
||||
BKP_DATA_14, /*!< BKP data register 14 */
|
||||
BKP_DATA_15, /*!< BKP data register 15 */
|
||||
BKP_DATA_16, /*!< BKP data register 16 */
|
||||
BKP_DATA_17, /*!< BKP data register 17 */
|
||||
BKP_DATA_18, /*!< BKP data register 18 */
|
||||
BKP_DATA_19, /*!< BKP data register 19 */
|
||||
BKP_DATA_20, /*!< BKP data register 20 */
|
||||
BKP_DATA_21, /*!< BKP data register 21 */
|
||||
BKP_DATA_22, /*!< BKP data register 22 */
|
||||
BKP_DATA_23, /*!< BKP data register 23 */
|
||||
BKP_DATA_24, /*!< BKP data register 24 */
|
||||
BKP_DATA_25, /*!< BKP data register 25 */
|
||||
BKP_DATA_26, /*!< BKP data register 26 */
|
||||
BKP_DATA_27, /*!< BKP data register 27 */
|
||||
BKP_DATA_28, /*!< BKP data register 28 */
|
||||
BKP_DATA_29, /*!< BKP data register 29 */
|
||||
BKP_DATA_30, /*!< BKP data register 30 */
|
||||
BKP_DATA_31, /*!< BKP data register 31 */
|
||||
BKP_DATA_32, /*!< BKP data register 32 */
|
||||
BKP_DATA_33, /*!< BKP data register 33 */
|
||||
BKP_DATA_34, /*!< BKP data register 34 */
|
||||
BKP_DATA_35, /*!< BKP data register 35 */
|
||||
BKP_DATA_36, /*!< BKP data register 36 */
|
||||
BKP_DATA_37, /*!< BKP data register 37 */
|
||||
BKP_DATA_38, /*!< BKP data register 38 */
|
||||
BKP_DATA_39, /*!< BKP data register 39 */
|
||||
BKP_DATA_40, /*!< BKP data register 40 */
|
||||
BKP_DATA_41, /*!< BKP data register 41 */
|
||||
}bkp_data_register_enum;
|
||||
|
||||
/* function declarations */
|
||||
/* reset BKP registers */
|
||||
void bkp_deinit(void);
|
||||
/* write BKP data register */
|
||||
void bkp_write_data(bkp_data_register_enum register_number, uint16_t data);
|
||||
/* read BKP data register */
|
||||
uint16_t bkp_read_data(bkp_data_register_enum register_number);
|
||||
|
||||
/* RTC related functions */
|
||||
/* enable RTC clock calibration output */
|
||||
void bkp_rtc_calibration_output_enable(void);
|
||||
/* disable RTC clock calibration output */
|
||||
void bkp_rtc_calibration_output_disable(void);
|
||||
/* enable RTC alarm or second signal output */
|
||||
void bkp_rtc_signal_output_enable(void);
|
||||
/* disable RTC alarm or second signal output */
|
||||
void bkp_rtc_signal_output_disable(void);
|
||||
/* RTC output selection */
|
||||
void bkp_rtc_output_select(uint16_t outputsel);
|
||||
/* RTC clock output selection */
|
||||
void bkp_rtc_clock_output_select(uint16_t clocksel);
|
||||
/* RTC clock calibration direction */
|
||||
void bkp_rtc_clock_calibration_direction(uint16_t direction);
|
||||
/* set RTC clock calibration value */
|
||||
void bkp_rtc_calibration_value_set(uint8_t value);
|
||||
|
||||
/* tamper pin related functions */
|
||||
/* enable tamper pin detection */
|
||||
void bkp_tamper_detection_enable(void);
|
||||
/* disable tamper pin detection */
|
||||
void bkp_tamper_detection_disable(void);
|
||||
/* set tamper pin active level */
|
||||
void bkp_tamper_active_level_set(uint16_t level);
|
||||
/* enable tamper pin interrupt */
|
||||
void bkp_tamper_interrupt_enable(void);
|
||||
/* disable tamper pin interrupt */
|
||||
void bkp_tamper_interrupt_disable(void);
|
||||
|
||||
/* flag functions */
|
||||
/* get BKP flag state */
|
||||
FlagStatus bkp_flag_get(uint16_t flag);
|
||||
/* clear BKP flag state */
|
||||
void bkp_flag_clear(uint16_t flag);
|
||||
/* get BKP interrupt flag state */
|
||||
FlagStatus bkp_interrupt_flag_get(uint16_t flag);
|
||||
/* clear BKP interrupt flag state */
|
||||
void bkp_interrupt_flag_clear(uint16_t flag);
|
||||
|
||||
#endif /* GD32F30X_BKP_H */
|
||||
@@ -0,0 +1,749 @@
|
||||
/*!
|
||||
\file gd32f30x_can.h
|
||||
\brief definitions for the CAN
|
||||
|
||||
\version 2017-02-10, V1.0.0, firmware for GD32F30x
|
||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x
|
||||
\version 2018-12-25, V2.0.0, firmware for GD32F30x
|
||||
\version 2019-11-27, V2.0.1, firmware for GD32F30x
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F30x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F30X_CAN_H
|
||||
#define GD32F30X_CAN_H
|
||||
|
||||
#include "gd32f30x.h"
|
||||
|
||||
/* CAN definitions */
|
||||
#define CAN0 CAN_BASE /*!< CAN0 base address */
|
||||
#define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define CAN_CTL(canx) REG32((canx) + 0x00000000U) /*!< CAN control register */
|
||||
#define CAN_STAT(canx) REG32((canx) + 0x00000004U) /*!< CAN status register */
|
||||
#define CAN_TSTAT(canx) REG32((canx) + 0x00000008U) /*!< CAN transmit status register*/
|
||||
#define CAN_RFIFO0(canx) REG32((canx) + 0x0000000CU) /*!< CAN receive FIFO0 register */
|
||||
#define CAN_RFIFO1(canx) REG32((canx) + 0x00000010U) /*!< CAN receive FIFO1 register */
|
||||
#define CAN_INTEN(canx) REG32((canx) + 0x00000014U) /*!< CAN interrupt enable register */
|
||||
#define CAN_ERR(canx) REG32((canx) + 0x00000018U) /*!< CAN error register */
|
||||
#define CAN_BT(canx) REG32((canx) + 0x0000001CU) /*!< CAN bit timing register */
|
||||
#define CAN_TMI0(canx) REG32((canx) + 0x00000180U) /*!< CAN transmit mailbox0 identifier register */
|
||||
#define CAN_TMP0(canx) REG32((canx) + 0x00000184U) /*!< CAN transmit mailbox0 property register */
|
||||
#define CAN_TMDATA00(canx) REG32((canx) + 0x00000188U) /*!< CAN transmit mailbox0 data0 register */
|
||||
#define CAN_TMDATA10(canx) REG32((canx) + 0x0000018CU) /*!< CAN transmit mailbox0 data1 register */
|
||||
#define CAN_TMI1(canx) REG32((canx) + 0x00000190U) /*!< CAN transmit mailbox1 identifier register */
|
||||
#define CAN_TMP1(canx) REG32((canx) + 0x00000194U) /*!< CAN transmit mailbox1 property register */
|
||||
#define CAN_TMDATA01(canx) REG32((canx) + 0x00000198U) /*!< CAN transmit mailbox1 data0 register */
|
||||
#define CAN_TMDATA11(canx) REG32((canx) + 0x0000019CU) /*!< CAN transmit mailbox1 data1 register */
|
||||
#define CAN_TMI2(canx) REG32((canx) + 0x000001A0U) /*!< CAN transmit mailbox2 identifier register */
|
||||
#define CAN_TMP2(canx) REG32((canx) + 0x000001A4U) /*!< CAN transmit mailbox2 property register */
|
||||
#define CAN_TMDATA02(canx) REG32((canx) + 0x000001A8U) /*!< CAN transmit mailbox2 data0 register */
|
||||
#define CAN_TMDATA12(canx) REG32((canx) + 0x000001ACU) /*!< CAN transmit mailbox2 data1 register */
|
||||
#define CAN_RFIFOMI0(canx) REG32((canx) + 0x000001B0U) /*!< CAN receive FIFO0 mailbox identifier register */
|
||||
#define CAN_RFIFOMP0(canx) REG32((canx) + 0x000001B4U) /*!< CAN receive FIFO0 mailbox property register */
|
||||
#define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x000001B8U) /*!< CAN receive FIFO0 mailbox data0 register */
|
||||
#define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x000001BCU) /*!< CAN receive FIFO0 mailbox data1 register */
|
||||
#define CAN_RFIFOMI1(canx) REG32((canx) + 0x000001C0U) /*!< CAN receive FIFO1 mailbox identifier register */
|
||||
#define CAN_RFIFOMP1(canx) REG32((canx) + 0x000001C4U) /*!< CAN receive FIFO1 mailbox property register */
|
||||
#define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x000001C8U) /*!< CAN receive FIFO1 mailbox data0 register */
|
||||
#define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x000001CCU) /*!< CAN receive FIFO1 mailbox data1 register */
|
||||
#define CAN_FCTL(canx) REG32((canx) + 0x00000200U) /*!< CAN filter control register */
|
||||
#define CAN_FMCFG(canx) REG32((canx) + 0x00000204U) /*!< CAN filter mode register */
|
||||
#define CAN_FSCFG(canx) REG32((canx) + 0x0000020CU) /*!< CAN filter scale register */
|
||||
#define CAN_FAFIFO(canx) REG32((canx) + 0x00000214U) /*!< CAN filter associated FIFO register */
|
||||
#define CAN_FW(canx) REG32((canx) + 0x0000021CU) /*!< CAN filter working register */
|
||||
#define CAN_F0DATA0(canx) REG32((canx) + 0x00000240U) /*!< CAN filter 0 data 0 register */
|
||||
#define CAN_F1DATA0(canx) REG32((canx) + 0x00000248U) /*!< CAN filter 1 data 0 register */
|
||||
#define CAN_F2DATA0(canx) REG32((canx) + 0x00000250U) /*!< CAN filter 2 data 0 register */
|
||||
#define CAN_F3DATA0(canx) REG32((canx) + 0x00000258U) /*!< CAN filter 3 data 0 register */
|
||||
#define CAN_F4DATA0(canx) REG32((canx) + 0x00000260U) /*!< CAN filter 4 data 0 register */
|
||||
#define CAN_F5DATA0(canx) REG32((canx) + 0x00000268U) /*!< CAN filter 5 data 0 register */
|
||||
#define CAN_F6DATA0(canx) REG32((canx) + 0x00000270U) /*!< CAN filter 6 data 0 register */
|
||||
#define CAN_F7DATA0(canx) REG32((canx) + 0x00000278U) /*!< CAN filter 7 data 0 register */
|
||||
#define CAN_F8DATA0(canx) REG32((canx) + 0x00000280U) /*!< CAN filter 8 data 0 register */
|
||||
#define CAN_F9DATA0(canx) REG32((canx) + 0x00000288U) /*!< CAN filter 9 data 0 register */
|
||||
#define CAN_F10DATA0(canx) REG32((canx) + 0x00000290U) /*!< CAN filter 10 data 0 register */
|
||||
#define CAN_F11DATA0(canx) REG32((canx) + 0x00000298U) /*!< CAN filter 11 data 0 register */
|
||||
#define CAN_F12DATA0(canx) REG32((canx) + 0x000002A0U) /*!< CAN filter 12 data 0 register */
|
||||
#define CAN_F13DATA0(canx) REG32((canx) + 0x000002A8U) /*!< CAN filter 13 data 0 register */
|
||||
#define CAN_F14DATA0(canx) REG32((canx) + 0x000002B0U) /*!< CAN filter 14 data 0 register */
|
||||
#define CAN_F15DATA0(canx) REG32((canx) + 0x000002B8U) /*!< CAN filter 15 data 0 register */
|
||||
#define CAN_F16DATA0(canx) REG32((canx) + 0x000002C0U) /*!< CAN filter 16 data 0 register */
|
||||
#define CAN_F17DATA0(canx) REG32((canx) + 0x000002C8U) /*!< CAN filter 17 data 0 register */
|
||||
#define CAN_F18DATA0(canx) REG32((canx) + 0x000002D0U) /*!< CAN filter 18 data 0 register */
|
||||
#define CAN_F19DATA0(canx) REG32((canx) + 0x000002D8U) /*!< CAN filter 19 data 0 register */
|
||||
#define CAN_F20DATA0(canx) REG32((canx) + 0x000002E0U) /*!< CAN filter 20 data 0 register */
|
||||
#define CAN_F21DATA0(canx) REG32((canx) + 0x000002E8U) /*!< CAN filter 21 data 0 register */
|
||||
#define CAN_F22DATA0(canx) REG32((canx) + 0x000002F0U) /*!< CAN filter 22 data 0 register */
|
||||
#define CAN_F23DATA0(canx) REG32((canx) + 0x000003F8U) /*!< CAN filter 23 data 0 register */
|
||||
#define CAN_F24DATA0(canx) REG32((canx) + 0x00000300U) /*!< CAN filter 24 data 0 register */
|
||||
#define CAN_F25DATA0(canx) REG32((canx) + 0x00000308U) /*!< CAN filter 25 data 0 register */
|
||||
#define CAN_F26DATA0(canx) REG32((canx) + 0x00000310U) /*!< CAN filter 26 data 0 register */
|
||||
#define CAN_F27DATA0(canx) REG32((canx) + 0x00000318U) /*!< CAN filter 27 data 0 register */
|
||||
#define CAN_F0DATA1(canx) REG32((canx) + 0x00000244U) /*!< CAN filter 0 data 1 register */
|
||||
#define CAN_F1DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 1 data 1 register */
|
||||
#define CAN_F2DATA1(canx) REG32((canx) + 0x00000254U) /*!< CAN filter 2 data 1 register */
|
||||
#define CAN_F3DATA1(canx) REG32((canx) + 0x0000025CU) /*!< CAN filter 3 data 1 register */
|
||||
#define CAN_F4DATA1(canx) REG32((canx) + 0x00000264U) /*!< CAN filter 4 data 1 register */
|
||||
#define CAN_F5DATA1(canx) REG32((canx) + 0x0000026CU) /*!< CAN filter 5 data 1 register */
|
||||
#define CAN_F6DATA1(canx) REG32((canx) + 0x00000274U) /*!< CAN filter 6 data 1 register */
|
||||
#define CAN_F7DATA1(canx) REG32((canx) + 0x0000027CU) /*!< CAN filter 7 data 1 register */
|
||||
#define CAN_F8DATA1(canx) REG32((canx) + 0x00000284U) /*!< CAN filter 8 data 1 register */
|
||||
#define CAN_F9DATA1(canx) REG32((canx) + 0x0000028CU) /*!< CAN filter 9 data 1 register */
|
||||
#define CAN_F10DATA1(canx) REG32((canx) + 0x00000294U) /*!< CAN filter 10 data 1 register */
|
||||
#define CAN_F11DATA1(canx) REG32((canx) + 0x0000029CU) /*!< CAN filter 11 data 1 register */
|
||||
#define CAN_F12DATA1(canx) REG32((canx) + 0x000002A4U) /*!< CAN filter 12 data 1 register */
|
||||
#define CAN_F13DATA1(canx) REG32((canx) + 0x000002ACU) /*!< CAN filter 13 data 1 register */
|
||||
#define CAN_F14DATA1(canx) REG32((canx) + 0x000002B4U) /*!< CAN filter 14 data 1 register */
|
||||
#define CAN_F15DATA1(canx) REG32((canx) + 0x000002BCU) /*!< CAN filter 15 data 1 register */
|
||||
#define CAN_F16DATA1(canx) REG32((canx) + 0x000002C4U) /*!< CAN filter 16 data 1 register */
|
||||
#define CAN_F17DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 17 data 1 register */
|
||||
#define CAN_F18DATA1(canx) REG32((canx) + 0x000002D4U) /*!< CAN filter 18 data 1 register */
|
||||
#define CAN_F19DATA1(canx) REG32((canx) + 0x000002DCU) /*!< CAN filter 19 data 1 register */
|
||||
#define CAN_F20DATA1(canx) REG32((canx) + 0x000002E4U) /*!< CAN filter 20 data 1 register */
|
||||
#define CAN_F21DATA1(canx) REG32((canx) + 0x000002ECU) /*!< CAN filter 21 data 1 register */
|
||||
#define CAN_F22DATA1(canx) REG32((canx) + 0x000002F4U) /*!< CAN filter 22 data 1 register */
|
||||
#define CAN_F23DATA1(canx) REG32((canx) + 0x000002FCU) /*!< CAN filter 23 data 1 register */
|
||||
#define CAN_F24DATA1(canx) REG32((canx) + 0x00000304U) /*!< CAN filter 24 data 1 register */
|
||||
#define CAN_F25DATA1(canx) REG32((canx) + 0x0000030CU) /*!< CAN filter 25 data 1 register */
|
||||
#define CAN_F26DATA1(canx) REG32((canx) + 0x00000314U) /*!< CAN filter 26 data 1 register */
|
||||
#define CAN_F27DATA1(canx) REG32((canx) + 0x0000031CU) /*!< CAN filter 27 data 1 register */
|
||||
|
||||
/* CAN transmit mailbox bank */
|
||||
#define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */
|
||||
#define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */
|
||||
#define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */
|
||||
#define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */
|
||||
|
||||
/* CAN filter bank */
|
||||
#define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */
|
||||
#define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */
|
||||
|
||||
/* CAN receive FIFO mailbox bank */
|
||||
#define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */
|
||||
#define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */
|
||||
#define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */
|
||||
#define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CAN_CTL */
|
||||
#define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */
|
||||
#define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */
|
||||
#define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */
|
||||
#define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */
|
||||
#define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */
|
||||
#define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */
|
||||
#define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */
|
||||
#define CAN_CTL_TTC BIT(7) /*!< time triggered communication */
|
||||
#define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */
|
||||
#define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */
|
||||
|
||||
/* CAN_STAT */
|
||||
#define CAN_STAT_IWS BIT(0) /*!< initial working state */
|
||||
#define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */
|
||||
#define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/
|
||||
#define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */
|
||||
#define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */
|
||||
#define CAN_STAT_TS BIT(8) /*!< transmitting state */
|
||||
#define CAN_STAT_RS BIT(9) /*!< receiving state */
|
||||
#define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */
|
||||
#define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */
|
||||
|
||||
/* CAN_TSTAT */
|
||||
#define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */
|
||||
#define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */
|
||||
#define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */
|
||||
#define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */
|
||||
#define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */
|
||||
#define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */
|
||||
#define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */
|
||||
#define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */
|
||||
#define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */
|
||||
#define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */
|
||||
#define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */
|
||||
#define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */
|
||||
#define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */
|
||||
#define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */
|
||||
#define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */
|
||||
#define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */
|
||||
#define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */
|
||||
#define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */
|
||||
#define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */
|
||||
#define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */
|
||||
#define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */
|
||||
#define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */
|
||||
|
||||
/* CAN_RFIFO0 */
|
||||
#define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */
|
||||
#define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */
|
||||
#define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */
|
||||
#define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */
|
||||
|
||||
/* CAN_RFIFO1 */
|
||||
#define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */
|
||||
#define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */
|
||||
#define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */
|
||||
#define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */
|
||||
|
||||
/* CAN_INTEN */
|
||||
#define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */
|
||||
#define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */
|
||||
#define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */
|
||||
#define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */
|
||||
#define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */
|
||||
#define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */
|
||||
#define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */
|
||||
#define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */
|
||||
#define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */
|
||||
#define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */
|
||||
#define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */
|
||||
#define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */
|
||||
#define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */
|
||||
#define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */
|
||||
|
||||
/* CAN_ERR */
|
||||
#define CAN_ERR_WERR BIT(0) /*!< warning error */
|
||||
#define CAN_ERR_PERR BIT(1) /*!< passive error */
|
||||
#define CAN_ERR_BOERR BIT(2) /*!< bus-off error */
|
||||
#define CAN_ERR_ERRN BITS(4,6) /*!< error number */
|
||||
#define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */
|
||||
#define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */
|
||||
|
||||
/* CAN_BT */
|
||||
#define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */
|
||||
#define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */
|
||||
#define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */
|
||||
#define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */
|
||||
#define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */
|
||||
#define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */
|
||||
|
||||
/* CAN_TMIx */
|
||||
#define CAN_TMI_TEN BIT(0) /*!< transmit enable */
|
||||
#define CAN_TMI_FT BIT(1) /*!< frame type */
|
||||
#define CAN_TMI_FF BIT(2) /*!< frame format */
|
||||
#define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */
|
||||
#define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */
|
||||
|
||||
/* CAN_TMPx */
|
||||
#define CAN_TMP_DLENC BITS(0,3) /*!< data length code */
|
||||
#define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */
|
||||
#define CAN_TMP_TS BITS(16,31) /*!< time stamp */
|
||||
|
||||
/* CAN_TMDATA0x */
|
||||
#define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */
|
||||
#define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */
|
||||
#define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */
|
||||
#define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */
|
||||
|
||||
/* CAN_TMDATA1x */
|
||||
#define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */
|
||||
#define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */
|
||||
#define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */
|
||||
#define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */
|
||||
|
||||
/* CAN_RFIFOMIx */
|
||||
#define CAN_RFIFOMI_FT BIT(1) /*!< frame type */
|
||||
#define CAN_RFIFOMI_FF BIT(2) /*!< frame format */
|
||||
#define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */
|
||||
#define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */
|
||||
|
||||
/* CAN_RFIFOMPx */
|
||||
#define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */
|
||||
#define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */
|
||||
#define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */
|
||||
|
||||
/* CAN_RFIFOMDATA0x */
|
||||
#define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */
|
||||
#define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */
|
||||
#define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */
|
||||
#define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */
|
||||
|
||||
/* CAN_RFIFOMDATA1x */
|
||||
#define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */
|
||||
#define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */
|
||||
#define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */
|
||||
#define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */
|
||||
|
||||
/* CAN_FCTL */
|
||||
#define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */
|
||||
#define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */
|
||||
|
||||
/* CAN_FMCFG */
|
||||
#define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask */
|
||||
|
||||
/* CAN_FSCFG */
|
||||
#define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits */
|
||||
|
||||
/* CAN_FAFIFO */
|
||||
#define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */
|
||||
|
||||
/* CAN_FW */
|
||||
#define CAN_FW_FW(regval) BIT(regval) /*!< filter working */
|
||||
|
||||
/* CAN_FxDATAy */
|
||||
#define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */
|
||||
|
||||
/* constants definitions */
|
||||
/* define the CAN bit position and its register index offset */
|
||||
#define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6)))
|
||||
#define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
|
||||
#define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
|
||||
#define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12)))
|
||||
#define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
|
||||
#define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
|
||||
|
||||
/* register offset */
|
||||
#define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */
|
||||
#define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */
|
||||
#define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */
|
||||
#define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */
|
||||
#define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */
|
||||
|
||||
/* CAN flags */
|
||||
typedef enum {
|
||||
/* flags in STAT register */
|
||||
CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */
|
||||
CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */
|
||||
CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */
|
||||
CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */
|
||||
CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */
|
||||
CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */
|
||||
CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */
|
||||
CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */
|
||||
CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */
|
||||
/* flags in TSTAT register */
|
||||
CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in TX FIFO */
|
||||
CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in TX FIFO */
|
||||
CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in TX FIFO */
|
||||
CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */
|
||||
CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */
|
||||
CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */
|
||||
CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */
|
||||
CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */
|
||||
CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */
|
||||
CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */
|
||||
CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */
|
||||
CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */
|
||||
CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */
|
||||
CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */
|
||||
CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */
|
||||
CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */
|
||||
CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */
|
||||
CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */
|
||||
/* flags in RFIFO0 register */
|
||||
CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */
|
||||
CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */
|
||||
/* flags in RFIFO1 register */
|
||||
CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */
|
||||
CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */
|
||||
/* flags in ERR register */
|
||||
CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */
|
||||
CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */
|
||||
CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */
|
||||
} can_flag_enum;
|
||||
|
||||
/* CAN interrupt flags */
|
||||
typedef enum {
|
||||
/* interrupt flags in STAT register */
|
||||
CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */
|
||||
CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */
|
||||
CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */
|
||||
/* interrupt flags in TSTAT register */
|
||||
CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */
|
||||
CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */
|
||||
CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */
|
||||
/* interrupt flags in RFIFO0 register */
|
||||
CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */
|
||||
CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */
|
||||
CAN_INT_FLAG_RFL0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 2U, 1U), /*!< receive FIFO0 not empty interrupt flag */
|
||||
/* interrupt flags in RFIFO0 register */
|
||||
CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */
|
||||
CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */
|
||||
CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO1 not empty interrupt flag */
|
||||
/* interrupt flags in ERR register */
|
||||
CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */
|
||||
CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */
|
||||
CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */
|
||||
CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */
|
||||
} can_interrupt_flag_enum;
|
||||
|
||||
/* CAN initiliaze parameters structure */
|
||||
typedef struct {
|
||||
uint8_t working_mode; /*!< CAN working mode */
|
||||
uint8_t resync_jump_width; /*!< CAN resynchronization jump width */
|
||||
uint8_t time_segment_1; /*!< time segment 1 */
|
||||
uint8_t time_segment_2; /*!< time segment 2 */
|
||||
ControlStatus time_triggered; /*!< time triggered communication mode */
|
||||
ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */
|
||||
ControlStatus auto_wake_up; /*!< automatic wake-up mode */
|
||||
ControlStatus auto_retrans; /*!< automatic retransmission mode */
|
||||
ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */
|
||||
ControlStatus trans_fifo_order; /*!< transmit FIFO order */
|
||||
uint16_t prescaler; /*!< baudrate prescaler */
|
||||
} can_parameter_struct;
|
||||
|
||||
/* CAN transmit message structure */
|
||||
typedef struct {
|
||||
uint32_t tx_sfid; /*!< standard format frame identifier */
|
||||
uint32_t tx_efid; /*!< extended format frame identifier */
|
||||
uint8_t tx_ff; /*!< format of frame, standard or extended format */
|
||||
uint8_t tx_ft; /*!< type of frame, data or remote */
|
||||
uint8_t tx_dlen; /*!< data length */
|
||||
uint8_t tx_data[8]; /*!< transmit data */
|
||||
} can_trasnmit_message_struct;
|
||||
|
||||
/* CAN receive message structure */
|
||||
typedef struct {
|
||||
uint32_t rx_sfid; /*!< standard format frame identifier */
|
||||
uint32_t rx_efid; /*!< extended format frame identifier */
|
||||
uint8_t rx_ff; /*!< format of frame, standard or extended format */
|
||||
uint8_t rx_ft; /*!< type of frame, data or remote */
|
||||
uint8_t rx_dlen; /*!< data length */
|
||||
uint8_t rx_data[8]; /*!< receive data */
|
||||
uint8_t rx_fi; /*!< filtering index */
|
||||
} can_receive_message_struct;
|
||||
|
||||
/* CAN filter parameters structure */
|
||||
typedef struct {
|
||||
uint16_t filter_list_high; /*!< filter list number high bits */
|
||||
uint16_t filter_list_low; /*!< filter list number low bits */
|
||||
uint16_t filter_mask_high; /*!< filter mask number high bits */
|
||||
uint16_t filter_mask_low; /*!< filter mask number low bits */
|
||||
uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */
|
||||
uint16_t filter_number; /*!< filter number */
|
||||
uint16_t filter_mode; /*!< filter mode, list or mask */
|
||||
uint16_t filter_bits; /*!< filter scale */
|
||||
ControlStatus filter_enable; /*!< filter work or not */
|
||||
} can_filter_parameter_struct;
|
||||
|
||||
/* CAN errors */
|
||||
typedef enum {
|
||||
CAN_ERROR_NONE = 0, /*!< no error */
|
||||
CAN_ERROR_FILL, /*!< fill error */
|
||||
CAN_ERROR_FORMATE, /*!< format error */
|
||||
CAN_ERROR_ACK, /*!< ACK error */
|
||||
CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */
|
||||
CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */
|
||||
CAN_ERROR_CRC, /*!< CRC error */
|
||||
CAN_ERROR_SOFTWARECFG, /*!< software configure */
|
||||
} can_error_enum;
|
||||
|
||||
/* transmit states */
|
||||
typedef enum {
|
||||
CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */
|
||||
CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */
|
||||
CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */
|
||||
CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */
|
||||
} can_transmit_state_enum;
|
||||
|
||||
typedef enum {
|
||||
CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */
|
||||
CAN_FILTER_STRUCT, /* CAN filter parameters struct */
|
||||
CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */
|
||||
CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */
|
||||
} can_struct_type_enum;
|
||||
|
||||
/* CAN baudrate prescaler */
|
||||
#define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* CAN bit segment 1 */
|
||||
#define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16))
|
||||
|
||||
/* CAN bit segment 2 */
|
||||
#define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20))
|
||||
|
||||
/* CAN resynchronization jump width */
|
||||
#define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24))
|
||||
|
||||
/* CAN communication mode */
|
||||
#define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30))
|
||||
|
||||
/* CAN FDATA high 16 bits */
|
||||
#define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16))
|
||||
|
||||
/* CAN FDATA low 16 bits */
|
||||
#define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* CAN1 filter start bank_number */
|
||||
#define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8))
|
||||
|
||||
/* CAN transmit mailbox extended identifier */
|
||||
#define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3))
|
||||
|
||||
/* CAN transmit mailbox standard identifier */
|
||||
#define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21))
|
||||
|
||||
/* transmit data byte 0 */
|
||||
#define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* transmit data byte 1 */
|
||||
#define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
|
||||
|
||||
/* transmit data byte 2 */
|
||||
#define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
|
||||
|
||||
/* transmit data byte 3 */
|
||||
#define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
|
||||
|
||||
/* transmit data byte 4 */
|
||||
#define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* transmit data byte 5 */
|
||||
#define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8))
|
||||
|
||||
/* transmit data byte 6 */
|
||||
#define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16))
|
||||
|
||||
/* transmit data byte 7 */
|
||||
#define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24))
|
||||
|
||||
/* receive mailbox extended identifier */
|
||||
#define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U)
|
||||
|
||||
/* receive mailbox standard identifier */
|
||||
#define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U)
|
||||
|
||||
/* receive data length */
|
||||
#define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0U, 3U)
|
||||
|
||||
/* the index of the filter by which the frame is passed */
|
||||
#define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
|
||||
|
||||
/* receive data byte 0 */
|
||||
#define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0U, 7U)
|
||||
|
||||
/* receive data byte 1 */
|
||||
#define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
|
||||
|
||||
/* receive data byte 2 */
|
||||
#define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16U, 23U)
|
||||
|
||||
/* receive data byte 3 */
|
||||
#define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24U, 31U)
|
||||
|
||||
/* receive data byte 4 */
|
||||
#define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0U, 7U)
|
||||
|
||||
/* receive data byte 5 */
|
||||
#define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8U, 15U)
|
||||
|
||||
/* receive data byte 6 */
|
||||
#define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16U, 23U)
|
||||
|
||||
/* receive data byte 7 */
|
||||
#define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U)
|
||||
|
||||
/* error number */
|
||||
#define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U)
|
||||
|
||||
/* transmit error count */
|
||||
#define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U)
|
||||
|
||||
/* receive error count */
|
||||
#define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U)
|
||||
|
||||
/* CAN errors */
|
||||
#define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4))
|
||||
#define CAN_ERRN_0 ERR_ERRN(0U) /*!< no error */
|
||||
#define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */
|
||||
#define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */
|
||||
#define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */
|
||||
#define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */
|
||||
#define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */
|
||||
#define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */
|
||||
#define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */
|
||||
|
||||
#define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */
|
||||
|
||||
/* CAN communication mode */
|
||||
#define CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */
|
||||
#define CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */
|
||||
#define CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */
|
||||
#define CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */
|
||||
|
||||
/* CAN resynchronisation jump width */
|
||||
#define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
|
||||
#define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
|
||||
#define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
|
||||
#define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
|
||||
|
||||
/* CAN time segment 1 */
|
||||
#define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
|
||||
#define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
|
||||
#define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
|
||||
#define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
|
||||
#define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */
|
||||
#define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */
|
||||
#define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */
|
||||
#define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */
|
||||
#define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */
|
||||
#define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */
|
||||
#define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */
|
||||
#define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */
|
||||
#define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */
|
||||
#define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */
|
||||
#define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */
|
||||
#define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */
|
||||
|
||||
/* CAN time segment 2 */
|
||||
#define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */
|
||||
#define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */
|
||||
#define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */
|
||||
#define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */
|
||||
#define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */
|
||||
#define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */
|
||||
#define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */
|
||||
#define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */
|
||||
|
||||
/* CAN mailbox number */
|
||||
#define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */
|
||||
#define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */
|
||||
#define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */
|
||||
#define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */
|
||||
|
||||
/* CAN frame format */
|
||||
#define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */
|
||||
#define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */
|
||||
|
||||
/* CAN receive FIFO */
|
||||
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */
|
||||
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */
|
||||
|
||||
/* frame number of receive FIFO */
|
||||
#define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */
|
||||
|
||||
#define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */
|
||||
#define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */
|
||||
|
||||
/* CAN working mode */
|
||||
#define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */
|
||||
#define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */
|
||||
#define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */
|
||||
|
||||
/* filter bits */
|
||||
#define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */
|
||||
#define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */
|
||||
|
||||
/* filter mode */
|
||||
#define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */
|
||||
#define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */
|
||||
|
||||
/* filter 16 bits mask */
|
||||
#define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */
|
||||
|
||||
/* frame type */
|
||||
#define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */
|
||||
#define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */
|
||||
|
||||
/* CAN timeout */
|
||||
#define CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */
|
||||
|
||||
/* interrupt enable bits */
|
||||
#define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */
|
||||
#define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */
|
||||
#define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */
|
||||
#define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */
|
||||
#define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */
|
||||
#define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */
|
||||
#define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */
|
||||
#define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */
|
||||
#define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */
|
||||
#define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */
|
||||
#define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */
|
||||
#define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */
|
||||
#define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */
|
||||
#define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* deinitialize CAN */
|
||||
void can_deinit(uint32_t can_periph);
|
||||
/* initialize CAN structure */
|
||||
void can_struct_para_init(can_struct_type_enum type, void *p_struct);
|
||||
/* initialize CAN */
|
||||
ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init);
|
||||
/* CAN filter initialization */
|
||||
void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init);
|
||||
|
||||
/* function configuration */
|
||||
/* set can1 filter start bank number */
|
||||
void can1_filter_start_bank(uint8_t start_bank);
|
||||
/* enable functions */
|
||||
/* CAN debug freeze enable */
|
||||
void can_debug_freeze_enable(uint32_t can_periph);
|
||||
/* CAN debug freeze disable */
|
||||
void can_debug_freeze_disable(uint32_t can_periph);
|
||||
/* CAN time trigger mode enable */
|
||||
void can_time_trigger_mode_enable(uint32_t can_periph);
|
||||
/* CAN time trigger mode disable */
|
||||
void can_time_trigger_mode_disable(uint32_t can_periph);
|
||||
|
||||
/* transmit functions */
|
||||
/* transmit CAN message */
|
||||
uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message);
|
||||
/* get CAN transmit state */
|
||||
can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number);
|
||||
/* stop CAN transmission */
|
||||
void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number);
|
||||
/* CAN receive message */
|
||||
void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message);
|
||||
/* CAN release FIFO */
|
||||
void can_fifo_release(uint32_t can_periph, uint8_t fifo_number);
|
||||
/* CAN receive message length */
|
||||
uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number);
|
||||
/* CAN working mode */
|
||||
ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode);
|
||||
/* CAN wakeup from sleep mode */
|
||||
ErrStatus can_wakeup(uint32_t can_periph);
|
||||
|
||||
/* CAN get error type */
|
||||
can_error_enum can_error_get(uint32_t can_periph);
|
||||
/* get CAN receive error number */
|
||||
uint8_t can_receive_error_number_get(uint32_t can_periph);
|
||||
/* get CAN transmit error number */
|
||||
uint8_t can_transmit_error_number_get(uint32_t can_periph);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* CAN get flag state */
|
||||
FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag);
|
||||
/* CAN clear flag state */
|
||||
void can_flag_clear(uint32_t can_periph, can_flag_enum flag);
|
||||
/* CAN interrupt enable */
|
||||
void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt);
|
||||
/* CAN interrupt disable */
|
||||
void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt);
|
||||
/* CAN get interrupt flag state */
|
||||
FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag);
|
||||
/* CAN clear interrupt flag state */
|
||||
void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag);
|
||||
|
||||
#endif /* GD32F30X_CAN_H */
|
||||
@@ -0,0 +1,81 @@
|
||||
/*!
|
||||
\file gd32f30x_crc.h
|
||||
\brief definitions for the CRC
|
||||
|
||||
\version 2017-02-10, V1.0.0, firmware for GD32F30x
|
||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x
|
||||
\version 2018-12-25, V2.0.0, firmware for GD32F30x
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F30x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F30X_CRC_H
|
||||
#define GD32F30X_CRC_H
|
||||
|
||||
#include "gd32f30x.h"
|
||||
|
||||
/* CRC definitions */
|
||||
#define CRC CRC_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define CRC_DATA REG32(CRC + 0x00U) /*!< CRC data register */
|
||||
#define CRC_FDATA REG32(CRC + 0x04U) /*!< CRC free data register */
|
||||
#define CRC_CTL REG32(CRC + 0x08U) /*!< CRC control register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CRC_DATA */
|
||||
#define CRC_DATA_DATA BITS(0,31) /*!< CRC calculation result bits */
|
||||
|
||||
/* CRC_FDATA */
|
||||
#define CRC_FDATA_FDATA BITS(0,7) /*!< CRC free data bits */
|
||||
|
||||
/* CRC_CTL */
|
||||
#define CRC_CTL_RST BIT(0) /*!< CRC reset CRC_DATA register bit */
|
||||
|
||||
|
||||
/* function declarations */
|
||||
/* deinit CRC calculation unit */
|
||||
void crc_deinit(void);
|
||||
|
||||
/* reset data register(CRC_DATA) to the value of 0xFFFFFFFF */
|
||||
void crc_data_register_reset(void);
|
||||
/* read the value of the data register */
|
||||
uint32_t crc_data_register_read(void);
|
||||
|
||||
/* read the value of the free data register */
|
||||
uint8_t crc_free_data_register_read(void);
|
||||
/* write data to the free data register */
|
||||
void crc_free_data_register_write(uint8_t free_data);
|
||||
|
||||
/* calculate the CRC value of a 32-bit data */
|
||||
uint32_t crc_single_data_calculate(uint32_t sdata);
|
||||
/* calculate the CRC value of an array of 32-bit values */
|
||||
uint32_t crc_block_data_calculate(const uint32_t *array, uint32_t size);
|
||||
|
||||
#endif /* GD32F30X_CRC_H */
|
||||
@@ -0,0 +1,185 @@
|
||||
/*!
|
||||
\file gd32f30x_ctc.h
|
||||
\brief definitions for the CTC
|
||||
|
||||
\version 2017-02-10, V1.0.0, firmware for GD32F30x
|
||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x
|
||||
\version 2018-12-25, V2.0.0, firmware for GD32F30x
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F30x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F30X_CTC_H
|
||||
#define GD32F30X_CTC_H
|
||||
|
||||
#include "gd32f30x.h"
|
||||
|
||||
/* CTC definitions */
|
||||
#define CTC CTC_BASE /*!< CTC base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define CTC_CTL0 REG32((CTC) + 0x00000000U) /*!< CTC control register 0 */
|
||||
#define CTC_CTL1 REG32((CTC) + 0x00000004U) /*!< CTC control register 1 */
|
||||
#define CTC_STAT REG32((CTC) + 0x00000008U) /*!< CTC status register */
|
||||
#define CTC_INTC REG32((CTC) + 0x0000000CU) /*!< CTC interrupt clear register */
|
||||
|
||||
/* bits definitions */
|
||||
/* CTC_CTL0 */
|
||||
#define CTC_CTL0_CKOKIE BIT(0) /*!< clock trim OK(CKOKIF) interrupt enable */
|
||||
#define CTC_CTL0_CKWARNIE BIT(1) /*!< clock trim warning(CKWARNIF) interrupt enable */
|
||||
#define CTC_CTL0_ERRIE BIT(2) /*!< error(ERRIF) interrupt enable */
|
||||
#define CTC_CTL0_EREFIE BIT(3) /*!< EREFIF interrupt enable */
|
||||
#define CTC_CTL0_CNTEN BIT(5) /*!< CTC counter enable */
|
||||
#define CTC_CTL0_AUTOTRIM BIT(6) /*!< hardware automatically trim mode */
|
||||
#define CTC_CTL0_SWREFPUL BIT(7) /*!< software reference source sync pulse */
|
||||
#define CTC_CTL0_TRIMVALUE BITS(8,13) /*!< IRC48M trim value */
|
||||
|
||||
/* CTC_CTL1 */
|
||||
#define CTC_CTL1_RLVALUE BITS(0,15) /*!< CTC counter reload value */
|
||||
#define CTC_CTL1_CKLIM BITS(16,23) /*!< clock trim base limit value */
|
||||
#define CTC_CTL1_REFPSC BITS(24,26) /*!< reference signal source prescaler */
|
||||
#define CTC_CTL1_REFSEL BITS(28,29) /*!< reference signal source selection */
|
||||
#define CTC_CTL1_REFPOL BIT(31) /*!< reference signal source polarity */
|
||||
|
||||
/* CTC_STAT */
|
||||
#define CTC_STAT_CKOKIF BIT(0) /*!< clock trim OK interrupt flag */
|
||||
#define CTC_STAT_CKWARNIF BIT(1) /*!< clock trim warning interrupt flag */
|
||||
#define CTC_STAT_ERRIF BIT(2) /*!< error interrupt flag */
|
||||
#define CTC_STAT_EREFIF BIT(3) /*!< expect reference interrupt flag */
|
||||
#define CTC_STAT_CKERR BIT(8) /*!< clock trim error bit */
|
||||
#define CTC_STAT_REFMISS BIT(9) /*!< reference sync pulse miss */
|
||||
#define CTC_STAT_TRIMERR BIT(10) /*!< trim value error bit */
|
||||
#define CTC_STAT_REFDIR BIT(15) /*!< CTC trim counter direction when reference sync pulse occurred */
|
||||
#define CTC_STAT_REFCAP BITS(16,31) /*!< CTC counter capture when reference sync pulse occurred */
|
||||
|
||||
/* CTC_INTC */
|
||||
#define CTC_INTC_CKOKIC BIT(0) /*!< CKOKIF interrupt clear bit */
|
||||
#define CTC_INTC_CKWARNIC BIT(1) /*!< CKWARNIF interrupt clear bit */
|
||||
#define CTC_INTC_ERRIC BIT(2) /*!< ERRIF interrupt clear bit */
|
||||
#define CTC_INTC_EREFIC BIT(3) /*!< EREFIF interrupt clear bit */
|
||||
|
||||
/* constants definitions */
|
||||
/* hardware automatically trim mode definitions */
|
||||
#define CTC_HARDWARE_TRIM_MODE_ENABLE CTC_CTL0_AUTOTRIM /*!< hardware automatically trim mode enable*/
|
||||
#define CTC_HARDWARE_TRIM_MODE_DISABLE ((uint32_t)0x00000000U) /*!< hardware automatically trim mode disable*/
|
||||
|
||||
/* reference signal source polarity definitions */
|
||||
#define CTC_REFSOURCE_POLARITY_FALLING CTC_CTL1_REFPOL /*!< reference signal source polarity is falling edge*/
|
||||
#define CTC_REFSOURCE_POLARITY_RISING ((uint32_t)0x00000000U) /*!< reference signal source polarity is rising edge*/
|
||||
|
||||
/* reference signal source selection definitions */
|
||||
#define CTL1_REFSEL(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
|
||||
#define CTC_REFSOURCE_GPIO CTL1_REFSEL(0) /*!< GPIO is selected */
|
||||
#define CTC_REFSOURCE_LXTAL CTL1_REFSEL(1) /*!< LXTAL is selected */
|
||||
|
||||
/* reference signal source prescaler definitions */
|
||||
#define CTL1_REFPSC(regval) (BITS(24,26) & ((uint32_t)(regval) << 24))
|
||||
#define CTC_REFSOURCE_PSC_OFF CTL1_REFPSC(0) /*!< reference signal not divided */
|
||||
#define CTC_REFSOURCE_PSC_DIV2 CTL1_REFPSC(1) /*!< reference signal divided by 2 */
|
||||
#define CTC_REFSOURCE_PSC_DIV4 CTL1_REFPSC(2) /*!< reference signal divided by 4 */
|
||||
#define CTC_REFSOURCE_PSC_DIV8 CTL1_REFPSC(3) /*!< reference signal divided by 8 */
|
||||
#define CTC_REFSOURCE_PSC_DIV16 CTL1_REFPSC(4) /*!< reference signal divided by 16 */
|
||||
#define CTC_REFSOURCE_PSC_DIV32 CTL1_REFPSC(5) /*!< reference signal divided by 32 */
|
||||
#define CTC_REFSOURCE_PSC_DIV64 CTL1_REFPSC(6) /*!< reference signal divided by 64 */
|
||||
#define CTC_REFSOURCE_PSC_DIV128 CTL1_REFPSC(7) /*!< reference signal divided by 128 */
|
||||
|
||||
/* CTC interrupt enable definitions */
|
||||
#define CTC_INT_CKOK CTC_CTL0_CKOKIE /*!< clock trim OK interrupt enable */
|
||||
#define CTC_INT_CKWARN CTC_CTL0_CKWARNIE /*!< clock trim warning interrupt enable */
|
||||
#define CTC_INT_ERR CTC_CTL0_ERRIE /*!< error interrupt enable */
|
||||
#define CTC_INT_EREF CTC_CTL0_EREFIE /*!< expect reference interrupt enable */
|
||||
|
||||
/* CTC interrupt source definitions */
|
||||
#define CTC_INT_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK interrupt flag */
|
||||
#define CTC_INT_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning interrupt flag */
|
||||
#define CTC_INT_FLAG_ERR CTC_STAT_ERRIF /*!< error interrupt flag */
|
||||
#define CTC_INT_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference interrupt flag */
|
||||
#define CTC_INT_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
|
||||
#define CTC_INT_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
|
||||
#define CTC_INT_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error */
|
||||
|
||||
/* CTC flag definitions */
|
||||
#define CTC_FLAG_CKOK CTC_STAT_CKOKIF /*!< clock trim OK flag */
|
||||
#define CTC_FLAG_CKWARN CTC_STAT_CKWARNIF /*!< clock trim warning flag */
|
||||
#define CTC_FLAG_ERR CTC_STAT_ERRIF /*!< error flag */
|
||||
#define CTC_FLAG_EREF CTC_STAT_EREFIF /*!< expect reference flag */
|
||||
#define CTC_FLAG_CKERR CTC_STAT_CKERR /*!< clock trim error bit */
|
||||
#define CTC_FLAG_REFMISS CTC_STAT_REFMISS /*!< reference sync pulse miss */
|
||||
#define CTC_FLAG_TRIMERR CTC_STAT_TRIMERR /*!< trim value error bit */
|
||||
|
||||
/* function declarations */
|
||||
/* reset ctc clock trim controller */
|
||||
void ctc_deinit(void);
|
||||
/* enable CTC trim counter */
|
||||
void ctc_counter_enable(void);
|
||||
/* disable CTC trim counter */
|
||||
void ctc_counter_disable(void);
|
||||
|
||||
/* configure the IRC48M trim value */
|
||||
void ctc_irc48m_trim_value_config(uint8_t trim_value);
|
||||
/* generate software reference source sync pulse */
|
||||
void ctc_software_refsource_pulse_generate(void);
|
||||
/* configure hardware automatically trim mode */
|
||||
void ctc_hardware_trim_mode_config(uint32_t hardmode);
|
||||
|
||||
/* configure reference signal source polarity */
|
||||
void ctc_refsource_polarity_config(uint32_t polarity);
|
||||
/* select reference signal source */
|
||||
void ctc_refsource_signal_select(uint32_t refs);
|
||||
/* configure reference signal source prescaler */
|
||||
void ctc_refsource_prescaler_config(uint32_t prescaler);
|
||||
/* configure clock trim base limit value */
|
||||
void ctc_clock_limit_value_config(uint8_t limit_value);
|
||||
/* configure CTC counter reload value */
|
||||
void ctc_counter_reload_value_config(uint16_t reload_value);
|
||||
|
||||
/* read CTC counter capture value when reference sync pulse occurred */
|
||||
uint16_t ctc_counter_capture_value_read(void);
|
||||
/* read CTC trim counter direction when reference sync pulse occurred */
|
||||
FlagStatus ctc_counter_direction_read(void);
|
||||
/* read CTC counter reload value */
|
||||
uint16_t ctc_counter_reload_value_read(void);
|
||||
/* read the IRC48M trim value */
|
||||
uint8_t ctc_irc48m_trim_value_read(void);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get CTC flag */
|
||||
FlagStatus ctc_flag_get(uint32_t flag);
|
||||
/* clear CTC flag */
|
||||
void ctc_flag_clear(uint32_t flag);
|
||||
/* enable the CTC interrupt */
|
||||
void ctc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable the CTC interrupt */
|
||||
void ctc_interrupt_disable(uint32_t interrupt);
|
||||
/* get CTC interrupt flag */
|
||||
FlagStatus ctc_interrupt_flag_get(uint32_t int_flag);
|
||||
/* clear CTC interrupt flag */
|
||||
void ctc_interrupt_flag_clear(uint32_t int_flag);
|
||||
|
||||
#endif /* GD32F30X_CTC_H */
|
||||
@@ -0,0 +1,250 @@
|
||||
/*!
|
||||
\file gd32f30x_dac.h
|
||||
\brief definitions for the DAC
|
||||
|
||||
\version 2017-02-10, V1.0.0, firmware for GD32F30x
|
||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x
|
||||
\version 2018-12-25, V2.0.0, firmware for GD32F30x
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F30x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F30X_DAC_H
|
||||
#define GD32F30X_DAC_H
|
||||
|
||||
#include "gd32f30x.h"
|
||||
|
||||
/* DACx(x=0,1) definitions */
|
||||
#define DAC DAC_BASE
|
||||
#define DAC0 0U
|
||||
#define DAC1 1U
|
||||
|
||||
/* registers definitions */
|
||||
#define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */
|
||||
#define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */
|
||||
#define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */
|
||||
#define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */
|
||||
#define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */
|
||||
#define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */
|
||||
#define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */
|
||||
#define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */
|
||||
#define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */
|
||||
#define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */
|
||||
#define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */
|
||||
#define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */
|
||||
#define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DAC_CTL */
|
||||
#define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */
|
||||
#define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */
|
||||
#define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */
|
||||
#define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */
|
||||
#define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */
|
||||
#define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */
|
||||
#define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */
|
||||
#define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */
|
||||
#define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */
|
||||
#define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */
|
||||
#define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */
|
||||
#define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */
|
||||
#define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */
|
||||
#define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */
|
||||
|
||||
/* DAC_SWT */
|
||||
#define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */
|
||||
#define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */
|
||||
|
||||
/* DAC0_R12DH */
|
||||
#define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */
|
||||
|
||||
/* DAC0_L12DH */
|
||||
#define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */
|
||||
|
||||
/* DAC0_R8DH */
|
||||
#define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */
|
||||
|
||||
/* DAC1_R12DH */
|
||||
#define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */
|
||||
|
||||
/* DAC1_L12DH */
|
||||
#define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */
|
||||
|
||||
/* DAC1_R8DH */
|
||||
#define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */
|
||||
|
||||
/* DACC_R12DH */
|
||||
#define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */
|
||||
#define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */
|
||||
|
||||
/* DACC_L12DH */
|
||||
#define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */
|
||||
#define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */
|
||||
|
||||
/* DACC_R8DH */
|
||||
#define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */
|
||||
#define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */
|
||||
|
||||
/* DAC0_DO */
|
||||
#define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */
|
||||
|
||||
/* DAC1_DO */
|
||||
#define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */
|
||||
|
||||
/* constants definitions */
|
||||
/* DAC trigger source */
|
||||
#define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3))
|
||||
#define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */
|
||||
#if (defined(GD32F30X_HD) || defined(GD32F30X_XD))
|
||||
#define DAC_TRIGGER_T7_TRGO CTL_DTSEL(1) /*!< TIMER7 TRGO */
|
||||
#elif defined(GD32F30X_CL)
|
||||
#define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */
|
||||
#endif /* GD32F30X_HD and GD32F30X_XD */
|
||||
#define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */
|
||||
#define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */
|
||||
#define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */
|
||||
#define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */
|
||||
#define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */
|
||||
#define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */
|
||||
|
||||
/* DAC noise wave mode */
|
||||
#define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6))
|
||||
#define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */
|
||||
#define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */
|
||||
#define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */
|
||||
|
||||
/* DAC noise wave bit width */
|
||||
#define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8))
|
||||
#define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */
|
||||
#define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */
|
||||
#define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */
|
||||
#define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */
|
||||
#define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */
|
||||
#define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */
|
||||
#define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */
|
||||
#define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */
|
||||
#define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */
|
||||
#define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */
|
||||
#define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */
|
||||
#define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */
|
||||
|
||||
/* unmask LFSR bits in DAC LFSR noise mode */
|
||||
#define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */
|
||||
#define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */
|
||||
#define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */
|
||||
#define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */
|
||||
#define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */
|
||||
#define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */
|
||||
#define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */
|
||||
#define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */
|
||||
#define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */
|
||||
#define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */
|
||||
#define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */
|
||||
#define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */
|
||||
|
||||
/* DAC data alignment */
|
||||
#define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0))
|
||||
#define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */
|
||||
#define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */
|
||||
#define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */
|
||||
|
||||
/* triangle amplitude in DAC triangle noise mode */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */
|
||||
#define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* deinitialize DAC */
|
||||
void dac_deinit(void);
|
||||
/* enable DAC */
|
||||
void dac_enable(uint32_t dac_periph);
|
||||
/* disable DAC */
|
||||
void dac_disable(uint32_t dac_periph);
|
||||
/* enable DAC DMA */
|
||||
void dac_dma_enable(uint32_t dac_periph);
|
||||
/* disable DAC DMA */
|
||||
void dac_dma_disable(uint32_t dac_periph);
|
||||
/* enable DAC output buffer */
|
||||
void dac_output_buffer_enable(uint32_t dac_periph);
|
||||
/* disable DAC output buffer */
|
||||
void dac_output_buffer_disable(uint32_t dac_periph);
|
||||
/* get the last data output value */
|
||||
uint16_t dac_output_value_get(uint32_t dac_periph);
|
||||
/* set DAC data holding register value */
|
||||
void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data);
|
||||
|
||||
/* DAC trigger configuration */
|
||||
/* enable DAC trigger */
|
||||
void dac_trigger_enable(uint32_t dac_periph);
|
||||
/* disable DAC trigger */
|
||||
void dac_trigger_disable(uint32_t dac_periph);
|
||||
/* configure DAC trigger source */
|
||||
void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource);
|
||||
/* enable DAC software trigger */
|
||||
void dac_software_trigger_enable(uint32_t dac_periph);
|
||||
/* disable DAC software trigger */
|
||||
void dac_software_trigger_disable(uint32_t dac_periph);
|
||||
|
||||
/* DAC wave mode configuration */
|
||||
/* configure DAC wave mode */
|
||||
void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode);
|
||||
/* configure DAC wave bit width */
|
||||
void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width);
|
||||
/* configure DAC LFSR noise mode */
|
||||
void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits);
|
||||
/* configure DAC triangle noise mode */
|
||||
void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude);
|
||||
|
||||
/* DAC concurrent mode configuration */
|
||||
/* enable DAC concurrent mode */
|
||||
void dac_concurrent_enable(void);
|
||||
/* disable DAC concurrent mode */
|
||||
void dac_concurrent_disable(void);
|
||||
/* enable DAC concurrent software trigger */
|
||||
void dac_concurrent_software_trigger_enable(void);
|
||||
/* disable DAC concurrent software trigger */
|
||||
void dac_concurrent_software_trigger_disable(void);
|
||||
/* enable DAC concurrent buffer function */
|
||||
void dac_concurrent_output_buffer_enable(void);
|
||||
/* disable DAC concurrent buffer function */
|
||||
void dac_concurrent_output_buffer_disable(void);
|
||||
/* set DAC concurrent mode data holding register value */
|
||||
void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1);
|
||||
|
||||
#endif /* GD32F30X_DAC_H */
|
||||
@@ -0,0 +1,149 @@
|
||||
/*!
|
||||
\file gd32f30x_dbg.h
|
||||
\brief definitions for the DBG
|
||||
|
||||
\version 2017-02-10, V1.0.0, firmware for GD32F30x
|
||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x
|
||||
\version 2018-12-25, V2.0.0, firmware for GD32F30x
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F30x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F30X_DBG_H
|
||||
#define GD32F30X_DBG_H
|
||||
|
||||
#include "gd32f30x.h"
|
||||
|
||||
/* DBG definitions */
|
||||
#define DBG DBG_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */
|
||||
#define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */
|
||||
|
||||
/* bits definitions */
|
||||
/* DBG_ID */
|
||||
#define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */
|
||||
|
||||
/* DBG_CTL0 */
|
||||
#define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */
|
||||
#define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */
|
||||
#define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */
|
||||
#define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */
|
||||
#define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */
|
||||
#define DBG_CTL0_TIMER1_HOLD BIT(11) /*!< hold TIMER1 counter when core is halted */
|
||||
#define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */
|
||||
#define DBG_CTL0_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */
|
||||
#define DBG_CTL0_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */
|
||||
#define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */
|
||||
#define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */
|
||||
#define DBG_CTL0_TIMER7_HOLD BIT(17) /*!< hold TIMER7 counter when core is halted */
|
||||
#define DBG_CTL0_TIMER4_HOLD BIT(18) /*!< hold TIMER4 counter when core is halted */
|
||||
#define DBG_CTL0_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */
|
||||
#define DBG_CTL0_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */
|
||||
#ifdef GD32F30X_CL
|
||||
#define DBG_CTL0_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */
|
||||
#endif /* GD32F30X_CL */
|
||||
#ifndef GD32F30X_HD
|
||||
#define DBG_CTL0_TIMER11_HOLD BIT(25) /*!< hold TIMER11 counter when core is halted */
|
||||
#define DBG_CTL0_TIMER12_HOLD BIT(26) /*!< hold TIMER12 counter when core is halted */
|
||||
#define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */
|
||||
#define DBG_CTL0_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */
|
||||
#define DBG_CTL0_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */
|
||||
#define DBG_CTL0_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */
|
||||
#endif /* GD32F30X_HD */
|
||||
|
||||
/* constants definitions */
|
||||
#define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */
|
||||
#define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */
|
||||
#define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */
|
||||
|
||||
/* define the peripheral debug hold bit position and its register index offset */
|
||||
#define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos))
|
||||
#define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6)))
|
||||
#define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
|
||||
/* register index */
|
||||
enum dbg_reg_idx
|
||||
{
|
||||
DBG_IDX_CTL0 = 0x04U
|
||||
};
|
||||
|
||||
typedef enum
|
||||
{
|
||||
DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< debug FWDGT kept when core is halted */
|
||||
DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< debug WWDGT kept when core is halted */
|
||||
DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), /*!< hold TIMER0 counter when core is halted */
|
||||
DBG_TIMER1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 11U), /*!< hold TIMER1 counter when core is halted */
|
||||
DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< hold TIMER2 counter when core is halted */
|
||||
DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 13U), /*!< hold TIMER3 counter when core is halted */
|
||||
DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 14U), /*!< debug CAN0 kept when core is halted */
|
||||
DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< hold I2C0 smbus when core is halted */
|
||||
DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< hold I2C1 smbus when core is halted */
|
||||
DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 17U), /*!< hold TIMER7 counter when core is halted */
|
||||
DBG_TIMER4_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 18U), /*!< hold TIMER4 counter when core is halted */
|
||||
DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U), /*!< hold TIMER5 counter when core is halted */
|
||||
DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 20U), /*!< hold TIMER6 counter when core is halted */
|
||||
#ifdef GD32F30X_CL
|
||||
DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 21U), /*!< debug CAN1 kept when core is halted */
|
||||
#endif /* GD32F30X_CL */
|
||||
#ifndef GD32F30X_HD
|
||||
DBG_TIMER11_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 25U), /*!< hold TIMER11 counter when core is halted */
|
||||
DBG_TIMER12_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 26U), /*!< hold TIMER12 counter when core is halted */
|
||||
DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), /*!< hold TIMER13 counter when core is halted */
|
||||
DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 28U), /*!< hold TIMER8 counter when core is halted */
|
||||
DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 29U), /*!< hold TIMER9 counter when core is halted */
|
||||
DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 30U), /*!< hold TIMER10 counter when core is halted */
|
||||
#endif /* GD32F30X_HD */
|
||||
}dbg_periph_enum;
|
||||
|
||||
/* function declarations */
|
||||
/* deinitialize the DBG */
|
||||
void dbg_deinit(void);
|
||||
/* read DBG_ID code register */
|
||||
uint32_t dbg_id_get(void);
|
||||
|
||||
/* enable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_enable(uint32_t dbg_low_power);
|
||||
/* disable low power behavior when the MCU is in debug mode */
|
||||
void dbg_low_power_disable(uint32_t dbg_low_power);
|
||||
|
||||
/* enable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_enable(dbg_periph_enum dbg_periph);
|
||||
/* disable peripheral behavior when the MCU is in debug mode */
|
||||
void dbg_periph_disable(dbg_periph_enum dbg_periph);
|
||||
|
||||
/* enable trace pin assignment */
|
||||
void dbg_trace_pin_enable(void);
|
||||
/* disable trace pin assignment */
|
||||
void dbg_trace_pin_disable(void);
|
||||
|
||||
#endif /* GD32F30X_DBG_H */
|
||||
@@ -0,0 +1,285 @@
|
||||
/*!
|
||||
\file gd32f30x_dma.h
|
||||
\brief definitions for the DMA
|
||||
|
||||
\version 2017-02-10, V1.0.0, firmware for GD32F30x
|
||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x
|
||||
\version 2018-12-25, V2.0.0, firmware for GD32F30x
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F30x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F30X_DMA_H
|
||||
#define GD32F30X_DMA_H
|
||||
|
||||
#include "gd32f30x.h"
|
||||
|
||||
/* DMA definitions */
|
||||
#define DMA0 (DMA_BASE) /*!< DMA0 base address */
|
||||
#define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */
|
||||
#define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */
|
||||
|
||||
#define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */
|
||||
#define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */
|
||||
#define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */
|
||||
#define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */
|
||||
|
||||
#define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */
|
||||
#define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */
|
||||
#define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */
|
||||
#define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */
|
||||
|
||||
#define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */
|
||||
#define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */
|
||||
#define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */
|
||||
#define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */
|
||||
|
||||
#define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */
|
||||
#define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */
|
||||
#define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */
|
||||
#define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */
|
||||
|
||||
#define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */
|
||||
#define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */
|
||||
#define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */
|
||||
#define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */
|
||||
|
||||
#define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */
|
||||
#define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */
|
||||
#define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */
|
||||
#define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */
|
||||
|
||||
#define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */
|
||||
#define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */
|
||||
#define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */
|
||||
#define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */
|
||||
|
||||
/* bits definitions */
|
||||
/* DMA_INTF */
|
||||
#define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */
|
||||
#define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */
|
||||
#define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */
|
||||
#define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */
|
||||
|
||||
/* DMA_INTC */
|
||||
#define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */
|
||||
#define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */
|
||||
#define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */
|
||||
#define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */
|
||||
|
||||
/* DMA_CHxCTL, x=0..6 */
|
||||
#define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */
|
||||
#define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */
|
||||
#define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */
|
||||
#define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */
|
||||
#define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */
|
||||
#define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */
|
||||
#define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */
|
||||
#define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */
|
||||
#define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */
|
||||
#define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */
|
||||
#define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */
|
||||
#define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */
|
||||
|
||||
/* DMA_CHxCNT,x=0..6 */
|
||||
#define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */
|
||||
|
||||
/* DMA_CHxPADDR,x=0..6 */
|
||||
#define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */
|
||||
|
||||
/* DMA_CHxMADDR,x=0..6 */
|
||||
#define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */
|
||||
|
||||
/* constants definitions */
|
||||
/* DMA channel select */
|
||||
typedef enum
|
||||
{
|
||||
DMA_CH0 = 0, /*!< DMA Channel0 */
|
||||
DMA_CH1, /*!< DMA Channel1 */
|
||||
DMA_CH2, /*!< DMA Channel2 */
|
||||
DMA_CH3, /*!< DMA Channel3 */
|
||||
DMA_CH4, /*!< DMA Channel4 */
|
||||
DMA_CH5, /*!< DMA Channel5 */
|
||||
DMA_CH6 /*!< DMA Channel6 */
|
||||
} dma_channel_enum;
|
||||
|
||||
/* DMA initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t periph_addr; /*!< peripheral base address */
|
||||
uint32_t periph_width; /*!< transfer data size of peripheral */
|
||||
uint32_t memory_addr; /*!< memory base address */
|
||||
uint32_t memory_width; /*!< transfer data size of memory */
|
||||
uint32_t number; /*!< channel transfer number */
|
||||
uint32_t priority; /*!< channel priority level */
|
||||
uint8_t periph_inc; /*!< peripheral increasing mode */
|
||||
uint8_t memory_inc; /*!< memory increasing mode */
|
||||
uint8_t direction; /*!< channel data transfer direction */
|
||||
|
||||
} dma_parameter_struct;
|
||||
|
||||
#define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */
|
||||
|
||||
/* DMA_register address */
|
||||
#define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */
|
||||
#define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */
|
||||
|
||||
/* DMA reset value */
|
||||
#define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */
|
||||
#define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */
|
||||
#define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */
|
||||
#define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */
|
||||
#define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \
|
||||
DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */
|
||||
|
||||
/* DMA_INTF register */
|
||||
/* interrupt flag bits */
|
||||
#define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */
|
||||
#define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */
|
||||
|
||||
/* flag bits */
|
||||
#define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */
|
||||
#define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */
|
||||
#define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */
|
||||
#define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */
|
||||
|
||||
/* DMA_CHxCTL register */
|
||||
/* interrupt enable bits */
|
||||
#define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */
|
||||
#define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */
|
||||
#define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */
|
||||
|
||||
/* transfer direction */
|
||||
#define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x0000U) /*!< read from peripheral and write to memory */
|
||||
#define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x0001U) /*!< read from memory and write to peripheral */
|
||||
|
||||
/* peripheral increasing mode */
|
||||
#define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x0000U) /*!< next address of peripheral is fixed address mode */
|
||||
#define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of peripheral is increasing address mode */
|
||||
|
||||
/* memory increasing mode */
|
||||
#define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x0000U) /*!< next address of memory is fixed address mode */
|
||||
#define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of memory is increasing address mode */
|
||||
|
||||
/* transfer data size of peripheral */
|
||||
#define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */
|
||||
#define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data size of peripheral is 8-bit */
|
||||
#define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data size of peripheral is 16-bit */
|
||||
#define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data size of peripheral is 32-bit */
|
||||
|
||||
/* transfer data size of memory */
|
||||
#define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */
|
||||
#define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data size of memory is 8-bit */
|
||||
#define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data size of memory is 16-bit */
|
||||
#define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data size of memory is 32-bit */
|
||||
|
||||
/* channel priority level */
|
||||
#define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */
|
||||
#define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */
|
||||
#define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */
|
||||
#define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */
|
||||
#define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */
|
||||
|
||||
/* memory to memory mode */
|
||||
#define DMA_MEMORY_TO_MEMORY_DISABLE ((uint32_t)0x00000000U)
|
||||
#define DMA_MEMORY_TO_MEMORY_ENABLE ((uint32_t)0x00000001U)
|
||||
|
||||
/* DMA_CHxCNT register */
|
||||
/* transfer counter */
|
||||
#define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */
|
||||
|
||||
/* function declarations */
|
||||
/* DMA deinitialization and initialization functions */
|
||||
/* deinitialize DMA a channel registers */
|
||||
void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* initialize the parameters of DMA struct with the default values */
|
||||
void dma_struct_para_init(dma_parameter_struct* init_struct);
|
||||
/* initialize DMA channel */
|
||||
void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct* init_struct);
|
||||
/* enable DMA circulation mode */
|
||||
void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable DMA circulation mode */
|
||||
void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* enable memory to memory mode */
|
||||
void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable memory to memory mode */
|
||||
void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* enable DMA channel */
|
||||
void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable DMA channel */
|
||||
void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
|
||||
/* DMA configuration functions */
|
||||
/* set DMA peripheral base address */
|
||||
void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
|
||||
/* set DMA memory base address */
|
||||
void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address);
|
||||
/* set the number of remaining data to be transferred by the DMA */
|
||||
void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number);
|
||||
/* get the number of remaining data to be transferred by the DMA */
|
||||
uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* configure priority level of DMA channel */
|
||||
void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority);
|
||||
/* configure transfer data size of memory */
|
||||
void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth);
|
||||
/* configure transfer data size of peripheral */
|
||||
void dma_periph_width_config (uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth);
|
||||
/* enable next address increasement algorithm of memory */
|
||||
void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable next address increasement algorithm of memory */
|
||||
void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* enable next address increasement algorithm of peripheral */
|
||||
void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* disable next address increasement algorithm of peripheral */
|
||||
void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx);
|
||||
/* configure the direction of data transfer on the channel */
|
||||
void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction);
|
||||
|
||||
/* flag and interrupt functions */
|
||||
/* check DMA flag is set or not */
|
||||
FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||
/* clear DMA a channel flag */
|
||||
void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||
/* check DMA flag and interrupt enable bit is set or not */
|
||||
FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||
/* clear DMA a channel flag */
|
||||
void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag);
|
||||
/* enable DMA interrupt */
|
||||
void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
||||
/* disable DMA interrupt */
|
||||
void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source);
|
||||
|
||||
#endif /* GD32F30X_DMA_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,446 @@
|
||||
/*!
|
||||
\file gd32f30x_exmc.h
|
||||
\brief definitions for the EXMC
|
||||
|
||||
\version 2017-02-10, V1.0.0, firmware for GD32F30x
|
||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x
|
||||
\version 2018-12-25, V2.0.0, firmware for GD32F30x
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F30x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F30X_EXMC_H
|
||||
#define GD32F30X_EXMC_H
|
||||
|
||||
#include "gd32f30x.h"
|
||||
|
||||
/* EXMC definitions */
|
||||
#define EXMC (EXMC_BASE) /*!< EXMC register base address */
|
||||
|
||||
/* registers definitions */
|
||||
/* NOR/PSRAM */
|
||||
#define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register0 */
|
||||
#define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register0 */
|
||||
#define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register0 */
|
||||
|
||||
#define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register1 */
|
||||
#define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register1 */
|
||||
#define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register1 */
|
||||
|
||||
#define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register2 */
|
||||
#define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register2 */
|
||||
#define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register2 */
|
||||
|
||||
#define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register3 */
|
||||
#define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register3 */
|
||||
#define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register3 */
|
||||
|
||||
/* NAND/PC card */
|
||||
#define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register1 */
|
||||
#define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register1 */
|
||||
#define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register1 */
|
||||
#define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register1 */
|
||||
#define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register1 */
|
||||
|
||||
#define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register2 */
|
||||
#define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register2 */
|
||||
#define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register2 */
|
||||
#define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register2 */
|
||||
#define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register2 */
|
||||
|
||||
#define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register3 */
|
||||
#define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register3 */
|
||||
#define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register3 */
|
||||
#define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register3 */
|
||||
#define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register */
|
||||
|
||||
/* bits definitions */
|
||||
/* EXMC_SNCTLx,x=0..3 */
|
||||
#define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */
|
||||
#define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing enable */
|
||||
#define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */
|
||||
#define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */
|
||||
#define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */
|
||||
#define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */
|
||||
#define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */
|
||||
#define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */
|
||||
#define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */
|
||||
#define EXMC_SNCTL_WREN BIT(12) /*!< write enable */
|
||||
#define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */
|
||||
#define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */
|
||||
#define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait enable */
|
||||
#define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */
|
||||
#define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write config */
|
||||
|
||||
/* EXMC_SNTCFGx,x=0..3 */
|
||||
#define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */
|
||||
#define EXMC_SNTCFG_AHLD BITS(4,7) /*!< asynchronous address hold time */
|
||||
#define EXMC_SNTCFG_DSET BITS(8,15) /*!< asynchronous data setup time */
|
||||
#define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */
|
||||
#define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */
|
||||
#define EXMC_SNTCFG_DLAT BITS(24,27) /*!< synchronous data latency for NOR flash */
|
||||
#define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */
|
||||
|
||||
/* EXMC_SNWTCFGx,x=0..3 */
|
||||
#define EXMC_SNWTCFG_WASET BITS(0,3) /*!< asynchronous address setup time */
|
||||
#define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< asynchronous address hold time */
|
||||
#define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< asynchronous data setup time */
|
||||
#define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */
|
||||
#define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */
|
||||
|
||||
/* EXMC_NPCTLx,x=1..3 */
|
||||
#define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */
|
||||
#define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */
|
||||
#define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */
|
||||
#define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */
|
||||
#define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */
|
||||
#define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */
|
||||
#define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */
|
||||
#define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */
|
||||
|
||||
/* EXMC_NPINTENx,x=1..3 */
|
||||
#define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */
|
||||
#define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */
|
||||
#define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */
|
||||
#define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */
|
||||
#define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */
|
||||
#define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */
|
||||
#define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */
|
||||
|
||||
/* EXMC_NPCTCFGx,x=1..3 */
|
||||
#define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */
|
||||
#define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */
|
||||
#define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */
|
||||
#define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */
|
||||
|
||||
/* EXMC_NPATCFGx,x=1..3 */
|
||||
#define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */
|
||||
#define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */
|
||||
#define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */
|
||||
#define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */
|
||||
|
||||
/* EXMC_PIOTCFG3 */
|
||||
#define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */
|
||||
#define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */
|
||||
#define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */
|
||||
#define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */
|
||||
|
||||
/* EXMC_NECCx,x=1,2 */
|
||||
#define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */
|
||||
|
||||
/* constants definitions */
|
||||
/* EXMC NOR/SRAM timing initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t asyn_access_mode; /*!< asynchronous access mode */
|
||||
uint32_t syn_data_latency; /*!< configure the data latency */
|
||||
uint32_t syn_clk_division; /*!< configure the clock divide ratio */
|
||||
uint32_t bus_latency; /*!< configure the bus latency */
|
||||
uint32_t asyn_data_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
|
||||
uint32_t asyn_address_holdtime; /*!< configure the address hold time,asynchronous access mode valid */
|
||||
uint32_t asyn_address_setuptime; /*!< configure the data setup time,asynchronous access mode valid */
|
||||
}exmc_norsram_timing_parameter_struct;
|
||||
|
||||
/* EXMC NOR/SRAM initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */
|
||||
uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */
|
||||
uint32_t extended_mode; /*!< enable or disable the extended mode */
|
||||
uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */
|
||||
uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */
|
||||
uint32_t memory_write; /*!< enable or disable the write operation */
|
||||
uint32_t nwait_config; /*!< NWAIT signal configuration */
|
||||
uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */
|
||||
uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */
|
||||
uint32_t burst_mode; /*!< enable or disable the burst mode */
|
||||
uint32_t databus_width; /*!< specifies the databus width of external memory */
|
||||
uint32_t memory_type; /*!< specifies the type of external memory */
|
||||
uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */
|
||||
exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing
|
||||
parameters for read if the extended mode is used */
|
||||
exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extended mode is used */
|
||||
}exmc_norsram_parameter_struct;
|
||||
|
||||
/* EXMC NAND/PC card timing initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */
|
||||
uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */
|
||||
uint32_t waittime; /*!< configure the minimum wait time */
|
||||
uint32_t setuptime; /*!< configure the address setup time */
|
||||
}exmc_nand_pccard_timing_parameter_struct;
|
||||
|
||||
/* EXMC NAND initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t nand_bank; /*!< select the bank of NAND */
|
||||
uint32_t ecc_size; /*!< the page size for the ECC calculation */
|
||||
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
|
||||
uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
|
||||
uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */
|
||||
uint32_t databus_width; /*!< the NAND flash databus width */
|
||||
uint32_t wait_feature; /*!< enable or disable the wait feature */
|
||||
exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */
|
||||
exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */
|
||||
}exmc_nand_parameter_struct;
|
||||
|
||||
/* EXMC PC card initialize struct */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */
|
||||
uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */
|
||||
uint32_t wait_feature; /*!< enable or disable the wait feature */
|
||||
exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for PC card common space */
|
||||
exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for PC card attribute space */
|
||||
exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for PC card IO space */
|
||||
}exmc_pccard_parameter_struct;
|
||||
|
||||
/* EXMC_register address */
|
||||
#define EXMC_SNCTL(region) REG32(EXMC + 0x08U * (region)) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */
|
||||
#define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */
|
||||
#define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U * (region)) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */
|
||||
|
||||
#define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U * (bank)) /*!< EXMC NAND/PC card control registers, bank = 1,2,3 */
|
||||
#define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U * (bank)) /*!< EXMC NAND/PC card interrupt enable registers, bank = 1,2,3 */
|
||||
#define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U * (bank)) /*!< EXMC NAND/PC card common space timing configuration registers, bank = 1,2,3 */
|
||||
#define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U * (bank)) /*!< EXMC NAND/PC card attribute space timing configuration registers, bank = 1,2,3 */
|
||||
#define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U * (bank)) /*!< EXMC NAND ECC registers, bank = 1,2 */
|
||||
|
||||
/* CRAM page size */
|
||||
#define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16))
|
||||
#define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */
|
||||
#define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */
|
||||
#define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */
|
||||
#define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */
|
||||
#define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */
|
||||
|
||||
/* NOR bank memory data bus width */
|
||||
#define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width is 8 bits */
|
||||
#define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width is 16 bits */
|
||||
|
||||
/* NOR bank memory type */
|
||||
#define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2))
|
||||
#define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */
|
||||
#define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */
|
||||
#define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */
|
||||
|
||||
/* asynchronous access mode */
|
||||
#define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28))
|
||||
#define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */
|
||||
#define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */
|
||||
#define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */
|
||||
#define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */
|
||||
|
||||
/* data latency for NOR flash */
|
||||
#define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24))
|
||||
#define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency of first burst access is 2 EXMC_CLK */
|
||||
#define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency of first burst access is 3 EXMC_CLK */
|
||||
#define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency of first burst access is 4 EXMC_CLK */
|
||||
#define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency of first burst access is 5 EXMC_CLK */
|
||||
#define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency of first burst access is 6 EXMC_CLK */
|
||||
#define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency of first burst access is 7 EXMC_CLK */
|
||||
#define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency of first burst access is 8 EXMC_CLK */
|
||||
#define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency of first burst access is 9 EXMC_CLK */
|
||||
#define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency of first burst access is 10 EXMC_CLK */
|
||||
#define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency of first burst access is 11 EXMC_CLK */
|
||||
#define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency of first burst access is 12 EXMC_CLK */
|
||||
#define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency of first burst access is 13 EXMC_CLK */
|
||||
#define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency of first burst access is 14 EXMC_CLK */
|
||||
#define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency of first burst access is 15 EXMC_CLK */
|
||||
#define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency of first burst access is 16 EXMC_CLK */
|
||||
#define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency of first burst access is 17 EXMC_CLK */
|
||||
|
||||
/* synchronous clock divide ratio */
|
||||
#define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20))
|
||||
#define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */
|
||||
#define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = HCLK/2 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = HCLK/3 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = HCLK/4 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = HCLK/5 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = HCLK/6 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = HCLK/7 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = HCLK/8 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = HCLK/9 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = HCLK/10 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = HCLK/11 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = HCLK/12 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = HCLK/13 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = HCLK/14 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = HCLK/15 */
|
||||
#define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = HCLK/16 */
|
||||
|
||||
/* ECC size */
|
||||
#define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17))
|
||||
#define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* ECC size is 256 bytes */
|
||||
#define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* ECC size is 512 bytes */
|
||||
#define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* ECC size is 1024 bytes */
|
||||
#define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* ECC size is 2048 bytes */
|
||||
#define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* ECC size is 4096 bytes */
|
||||
#define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* ECC size is 8192 bytes */
|
||||
|
||||
/* ALE to RE delay */
|
||||
#define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13))
|
||||
#define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */
|
||||
#define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */
|
||||
|
||||
/* CLE to RE delay */
|
||||
#define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9))
|
||||
#define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */
|
||||
#define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */
|
||||
|
||||
/* NAND bank memory data bus width */
|
||||
#define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4))
|
||||
#define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width is 8 bits */
|
||||
#define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width is 16 bits */
|
||||
|
||||
/* EXMC NOR/SRAM bank region definition */
|
||||
#define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */
|
||||
#define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */
|
||||
#define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */
|
||||
#define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */
|
||||
|
||||
/* EXMC NOR/SRAM write mode */
|
||||
#define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */
|
||||
#define EXMC_SYN_WRITE EXMC_SNCTL_SYNCWR /*!< synchronous write mode */
|
||||
|
||||
/* EXMC NWAIT signal configuration */
|
||||
#define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */
|
||||
#define EXMC_NWAIT_CONFIG_DURING EXMC_SNCTL_NRWTCFG /*!< NWAIT signal is active during wait state */
|
||||
|
||||
/* EXMC NWAIT signal polarity configuration */
|
||||
#define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */
|
||||
#define EXMC_NWAIT_POLARITY_HIGH EXMC_SNCTL_NRWTPOL /*!< high level is active of NWAIT */
|
||||
|
||||
/* EXMC NAND/PC card bank definition */
|
||||
#define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< bank1 NAND flash */
|
||||
#define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< bank2 NAND flash */
|
||||
#define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< bank3 PC card */
|
||||
|
||||
/* EXMC flag bits */
|
||||
#define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */
|
||||
#define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */
|
||||
#define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */
|
||||
#define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */
|
||||
|
||||
/* EXMC interrupt flag bits */
|
||||
#define EXMC_NAND_PCCARD_INT_FLAG_RISE EXMC_NPINTEN_INTREN /*!< rising edge interrupt and flag */
|
||||
#define EXMC_NAND_PCCARD_INT_FLAG_LEVEL EXMC_NPINTEN_INTHEN /*!< high-level interrupt and flag */
|
||||
#define EXMC_NAND_PCCARD_INT_FLAG_FALL EXMC_NPINTEN_INTFEN /*!< falling edge interrupt and flag */
|
||||
|
||||
/* function declarations */
|
||||
/* initialization functions */
|
||||
/* NOR/SRAM */
|
||||
/* deinitialize EXMC NOR/SRAM region */
|
||||
void exmc_norsram_deinit(uint32_t exmc_norsram_region);
|
||||
/* initialize exmc_norsram_parameter_struct with the default values */
|
||||
void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
|
||||
/* initialize EXMC NOR/SRAM region */
|
||||
void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct);
|
||||
/* enable EXMC NOR/SRAM region */
|
||||
void exmc_norsram_enable(uint32_t exmc_norsram_region);
|
||||
/* disable EXMC NOR/SRAM region */
|
||||
void exmc_norsram_disable(uint32_t exmc_norsram_region);
|
||||
/* NAND */
|
||||
/* deinitialize EXMC NAND bank */
|
||||
void exmc_nand_deinit(uint32_t exmc_nand_bank);
|
||||
/* initialize exmc_norsram_parameter_struct with the default values */
|
||||
void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
|
||||
/* initialize EXMC NAND bank */
|
||||
void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct);
|
||||
/* enable EXMC NAND bank */
|
||||
void exmc_nand_enable(uint32_t exmc_nand_bank);
|
||||
/* disable EXMC NAND bank */
|
||||
void exmc_nand_disable(uint32_t exmc_nand_bank);
|
||||
/* PC card */
|
||||
/* deinitialize EXMC PC card bank */
|
||||
void exmc_pccard_deinit(void);
|
||||
/* initialize exmc_pccard_parameter_struct parameter with the default values */
|
||||
void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
|
||||
/* initialize EXMC PC card bank */
|
||||
void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct);
|
||||
/* enable EXMC PC card bank */
|
||||
void exmc_pccard_enable(void);
|
||||
/* disable EXMC PC card bank */
|
||||
void exmc_pccard_disable(void);
|
||||
|
||||
/* function configuration */
|
||||
/* NOR/SRAM */
|
||||
/* configure CRAM page size */
|
||||
void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size);
|
||||
/* NAND */
|
||||
/* enable or disable the EXMC NAND ECC function */
|
||||
void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue);
|
||||
/* get the EXMC ECC value */
|
||||
uint32_t exmc_ecc_get(uint32_t exmc_nand_bank);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* enable EXMC interrupt */
|
||||
void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt);
|
||||
/* disable EXMC interrupt */
|
||||
void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt);
|
||||
/* get EXMC flag status */
|
||||
FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag);
|
||||
/* clear EXMC flag status */
|
||||
void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag);
|
||||
/* get EXMC interrupt flag */
|
||||
FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt);
|
||||
/* clear EXMC interrupt flag */
|
||||
void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt);
|
||||
|
||||
#endif /* GD32F30X_EXMC_H */
|
||||
@@ -0,0 +1,258 @@
|
||||
/*!
|
||||
\file gd32f30x_exti.h
|
||||
\brief definitions for the EXTI
|
||||
|
||||
\version 2017-02-10, V1.0.0, firmware for GD32F30x
|
||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x
|
||||
\version 2018-12-25, V2.0.0, firmware for GD32F30x
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F30x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F30X_EXTI_H
|
||||
#define GD32F30X_EXTI_H
|
||||
|
||||
#include "gd32f30x.h"
|
||||
|
||||
/* EXTI definitions */
|
||||
#define EXTI EXTI_BASE
|
||||
|
||||
/* registers definitions */
|
||||
#define EXTI_INTEN REG32(EXTI + 0x00U) /*!< interrupt enable register */
|
||||
#define EXTI_EVEN REG32(EXTI + 0x04U) /*!< event enable register */
|
||||
#define EXTI_RTEN REG32(EXTI + 0x08U) /*!< rising edge trigger enable register */
|
||||
#define EXTI_FTEN REG32(EXTI + 0x0CU) /*!< falling trigger enable register */
|
||||
#define EXTI_SWIEV REG32(EXTI + 0x10U) /*!< software interrupt event register */
|
||||
#define EXTI_PD REG32(EXTI + 0x14U) /*!< pending register */
|
||||
|
||||
/* bits definitions */
|
||||
/* EXTI_INTEN */
|
||||
#define EXTI_INTEN_INTEN0 BIT(0) /*!< interrupt from line 0 */
|
||||
#define EXTI_INTEN_INTEN1 BIT(1) /*!< interrupt from line 1 */
|
||||
#define EXTI_INTEN_INTEN2 BIT(2) /*!< interrupt from line 2 */
|
||||
#define EXTI_INTEN_INTEN3 BIT(3) /*!< interrupt from line 3 */
|
||||
#define EXTI_INTEN_INTEN4 BIT(4) /*!< interrupt from line 4 */
|
||||
#define EXTI_INTEN_INTEN5 BIT(5) /*!< interrupt from line 5 */
|
||||
#define EXTI_INTEN_INTEN6 BIT(6) /*!< interrupt from line 6 */
|
||||
#define EXTI_INTEN_INTEN7 BIT(7) /*!< interrupt from line 7 */
|
||||
#define EXTI_INTEN_INTEN8 BIT(8) /*!< interrupt from line 8 */
|
||||
#define EXTI_INTEN_INTEN9 BIT(9) /*!< interrupt from line 9 */
|
||||
#define EXTI_INTEN_INTEN10 BIT(10) /*!< interrupt from line 10 */
|
||||
#define EXTI_INTEN_INTEN11 BIT(11) /*!< interrupt from line 11 */
|
||||
#define EXTI_INTEN_INTEN12 BIT(12) /*!< interrupt from line 12 */
|
||||
#define EXTI_INTEN_INTEN13 BIT(13) /*!< interrupt from line 13 */
|
||||
#define EXTI_INTEN_INTEN14 BIT(14) /*!< interrupt from line 14 */
|
||||
#define EXTI_INTEN_INTEN15 BIT(15) /*!< interrupt from line 15 */
|
||||
#define EXTI_INTEN_INTEN16 BIT(16) /*!< interrupt from line 16 */
|
||||
#define EXTI_INTEN_INTEN17 BIT(17) /*!< interrupt from line 17 */
|
||||
#define EXTI_INTEN_INTEN18 BIT(18) /*!< interrupt from line 18 */
|
||||
#define EXTI_INTEN_INTEN19 BIT(19) /*!< interrupt from line 19 */
|
||||
|
||||
/* EXTI_EVEN */
|
||||
#define EXTI_EVEN_EVEN0 BIT(0) /*!< event from line 0 */
|
||||
#define EXTI_EVEN_EVEN1 BIT(1) /*!< event from line 1 */
|
||||
#define EXTI_EVEN_EVEN2 BIT(2) /*!< event from line 2 */
|
||||
#define EXTI_EVEN_EVEN3 BIT(3) /*!< event from line 3 */
|
||||
#define EXTI_EVEN_EVEN4 BIT(4) /*!< event from line 4 */
|
||||
#define EXTI_EVEN_EVEN5 BIT(5) /*!< event from line 5 */
|
||||
#define EXTI_EVEN_EVEN6 BIT(6) /*!< event from line 6 */
|
||||
#define EXTI_EVEN_EVEN7 BIT(7) /*!< event from line 7 */
|
||||
#define EXTI_EVEN_EVEN8 BIT(8) /*!< event from line 8 */
|
||||
#define EXTI_EVEN_EVEN9 BIT(9) /*!< event from line 9 */
|
||||
#define EXTI_EVEN_EVEN10 BIT(10) /*!< event from line 10 */
|
||||
#define EXTI_EVEN_EVEN11 BIT(11) /*!< event from line 11 */
|
||||
#define EXTI_EVEN_EVEN12 BIT(12) /*!< event from line 12 */
|
||||
#define EXTI_EVEN_EVEN13 BIT(13) /*!< event from line 13 */
|
||||
#define EXTI_EVEN_EVEN14 BIT(14) /*!< event from line 14 */
|
||||
#define EXTI_EVEN_EVEN15 BIT(15) /*!< event from line 15 */
|
||||
#define EXTI_EVEN_EVEN16 BIT(16) /*!< event from line 16 */
|
||||
#define EXTI_EVEN_EVEN17 BIT(17) /*!< event from line 17 */
|
||||
#define EXTI_EVEN_EVEN18 BIT(18) /*!< event from line 18 */
|
||||
#define EXTI_EVEN_EVEN19 BIT(19) /*!< event from line 19 */
|
||||
|
||||
/* EXTI_RTEN */
|
||||
#define EXTI_RTEN_RTEN0 BIT(0) /*!< rising edge from line 0 */
|
||||
#define EXTI_RTEN_RTEN1 BIT(1) /*!< rising edge from line 1 */
|
||||
#define EXTI_RTEN_RTEN2 BIT(2) /*!< rising edge from line 2 */
|
||||
#define EXTI_RTEN_RTEN3 BIT(3) /*!< rising edge from line 3 */
|
||||
#define EXTI_RTEN_RTEN4 BIT(4) /*!< rising edge from line 4 */
|
||||
#define EXTI_RTEN_RTEN5 BIT(5) /*!< rising edge from line 5 */
|
||||
#define EXTI_RTEN_RTEN6 BIT(6) /*!< rising edge from line 6 */
|
||||
#define EXTI_RTEN_RTEN7 BIT(7) /*!< rising edge from line 7 */
|
||||
#define EXTI_RTEN_RTEN8 BIT(8) /*!< rising edge from line 8 */
|
||||
#define EXTI_RTEN_RTEN9 BIT(9) /*!< rising edge from line 9 */
|
||||
#define EXTI_RTEN_RTEN10 BIT(10) /*!< rising edge from line 10 */
|
||||
#define EXTI_RTEN_RTEN11 BIT(11) /*!< rising edge from line 11 */
|
||||
#define EXTI_RTEN_RTEN12 BIT(12) /*!< rising edge from line 12 */
|
||||
#define EXTI_RTEN_RTEN13 BIT(13) /*!< rising edge from line 13 */
|
||||
#define EXTI_RTEN_RTEN14 BIT(14) /*!< rising edge from line 14 */
|
||||
#define EXTI_RTEN_RTEN15 BIT(15) /*!< rising edge from line 15 */
|
||||
#define EXTI_RTEN_RTEN16 BIT(16) /*!< rising edge from line 16 */
|
||||
#define EXTI_RTEN_RTEN17 BIT(17) /*!< rising edge from line 17 */
|
||||
#define EXTI_RTEN_RTEN18 BIT(18) /*!< rising edge from line 18 */
|
||||
#define EXTI_RTEN_RTEN19 BIT(19) /*!< rising edge from line 19 */
|
||||
|
||||
/* EXTI_FTEN */
|
||||
#define EXTI_FTEN_FTEN0 BIT(0) /*!< falling edge from line 0 */
|
||||
#define EXTI_FTEN_FTEN1 BIT(1) /*!< falling edge from line 1 */
|
||||
#define EXTI_FTEN_FTEN2 BIT(2) /*!< falling edge from line 2 */
|
||||
#define EXTI_FTEN_FTEN3 BIT(3) /*!< falling edge from line 3 */
|
||||
#define EXTI_FTEN_FTEN4 BIT(4) /*!< falling edge from line 4 */
|
||||
#define EXTI_FTEN_FTEN5 BIT(5) /*!< falling edge from line 5 */
|
||||
#define EXTI_FTEN_FTEN6 BIT(6) /*!< falling edge from line 6 */
|
||||
#define EXTI_FTEN_FTEN7 BIT(7) /*!< falling edge from line 7 */
|
||||
#define EXTI_FTEN_FTEN8 BIT(8) /*!< falling edge from line 8 */
|
||||
#define EXTI_FTEN_FTEN9 BIT(9) /*!< falling edge from line 9 */
|
||||
#define EXTI_FTEN_FTEN10 BIT(10) /*!< falling edge from line 10 */
|
||||
#define EXTI_FTEN_FTEN11 BIT(11) /*!< falling edge from line 11 */
|
||||
#define EXTI_FTEN_FTEN12 BIT(12) /*!< falling edge from line 12 */
|
||||
#define EXTI_FTEN_FTEN13 BIT(13) /*!< falling edge from line 13 */
|
||||
#define EXTI_FTEN_FTEN14 BIT(14) /*!< falling edge from line 14 */
|
||||
#define EXTI_FTEN_FTEN15 BIT(15) /*!< falling edge from line 15 */
|
||||
#define EXTI_FTEN_FTEN16 BIT(16) /*!< falling edge from line 16 */
|
||||
#define EXTI_FTEN_FTEN17 BIT(17) /*!< falling edge from line 17 */
|
||||
#define EXTI_FTEN_FTEN18 BIT(18) /*!< falling edge from line 18 */
|
||||
#define EXTI_FTEN_FTEN19 BIT(19) /*!< falling edge from line 19 */
|
||||
|
||||
/* EXTI_SWIEV */
|
||||
#define EXTI_SWIEV_SWIEV0 BIT(0) /*!< software interrupt/event request from line 0 */
|
||||
#define EXTI_SWIEV_SWIEV1 BIT(1) /*!< software interrupt/event request from line 1 */
|
||||
#define EXTI_SWIEV_SWIEV2 BIT(2) /*!< software interrupt/event request from line 2 */
|
||||
#define EXTI_SWIEV_SWIEV3 BIT(3) /*!< software interrupt/event request from line 3 */
|
||||
#define EXTI_SWIEV_SWIEV4 BIT(4) /*!< software interrupt/event request from line 4 */
|
||||
#define EXTI_SWIEV_SWIEV5 BIT(5) /*!< software interrupt/event request from line 5 */
|
||||
#define EXTI_SWIEV_SWIEV6 BIT(6) /*!< software interrupt/event request from line 6 */
|
||||
#define EXTI_SWIEV_SWIEV7 BIT(7) /*!< software interrupt/event request from line 7 */
|
||||
#define EXTI_SWIEV_SWIEV8 BIT(8) /*!< software interrupt/event request from line 8 */
|
||||
#define EXTI_SWIEV_SWIEV9 BIT(9) /*!< software interrupt/event request from line 9 */
|
||||
#define EXTI_SWIEV_SWIEV10 BIT(10) /*!< software interrupt/event request from line 10 */
|
||||
#define EXTI_SWIEV_SWIEV11 BIT(11) /*!< software interrupt/event request from line 11 */
|
||||
#define EXTI_SWIEV_SWIEV12 BIT(12) /*!< software interrupt/event request from line 12 */
|
||||
#define EXTI_SWIEV_SWIEV13 BIT(13) /*!< software interrupt/event request from line 13 */
|
||||
#define EXTI_SWIEV_SWIEV14 BIT(14) /*!< software interrupt/event request from line 14 */
|
||||
#define EXTI_SWIEV_SWIEV15 BIT(15) /*!< software interrupt/event request from line 15 */
|
||||
#define EXTI_SWIEV_SWIEV16 BIT(16) /*!< software interrupt/event request from line 16 */
|
||||
#define EXTI_SWIEV_SWIEV17 BIT(17) /*!< software interrupt/event request from line 17 */
|
||||
#define EXTI_SWIEV_SWIEV18 BIT(18) /*!< software interrupt/event request from line 18 */
|
||||
#define EXTI_SWIEV_SWIEV19 BIT(19) /*!< software interrupt/event request from line 19 */
|
||||
|
||||
/* EXTI_PD */
|
||||
#define EXTI_PD_PD0 BIT(0) /*!< interrupt pending status from line 0 */
|
||||
#define EXTI_PD_PD1 BIT(1) /*!< interrupt pending status from line 1 */
|
||||
#define EXTI_PD_PD2 BIT(2) /*!< interrupt pending status from line 2 */
|
||||
#define EXTI_PD_PD3 BIT(3) /*!< interrupt pending status from line 3 */
|
||||
#define EXTI_PD_PD4 BIT(4) /*!< interrupt pending status from line 4 */
|
||||
#define EXTI_PD_PD5 BIT(5) /*!< interrupt pending status from line 5 */
|
||||
#define EXTI_PD_PD6 BIT(6) /*!< interrupt pending status from line 6 */
|
||||
#define EXTI_PD_PD7 BIT(7) /*!< interrupt pending status from line 7 */
|
||||
#define EXTI_PD_PD8 BIT(8) /*!< interrupt pending status from line 8 */
|
||||
#define EXTI_PD_PD9 BIT(9) /*!< interrupt pending status from line 9 */
|
||||
#define EXTI_PD_PD10 BIT(10) /*!< interrupt pending status from line 10 */
|
||||
#define EXTI_PD_PD11 BIT(11) /*!< interrupt pending status from line 11 */
|
||||
#define EXTI_PD_PD12 BIT(12) /*!< interrupt pending status from line 12 */
|
||||
#define EXTI_PD_PD13 BIT(13) /*!< interrupt pending status from line 13 */
|
||||
#define EXTI_PD_PD14 BIT(14) /*!< interrupt pending status from line 14 */
|
||||
#define EXTI_PD_PD15 BIT(15) /*!< interrupt pending status from line 15 */
|
||||
#define EXTI_PD_PD16 BIT(16) /*!< interrupt pending status from line 16 */
|
||||
#define EXTI_PD_PD17 BIT(17) /*!< interrupt pending status from line 17 */
|
||||
#define EXTI_PD_PD18 BIT(18) /*!< interrupt pending status from line 18 */
|
||||
#define EXTI_PD_PD19 BIT(19) /*!< interrupt pending status from line 19 */
|
||||
|
||||
/* constants definitions */
|
||||
/* EXTI line number */
|
||||
typedef enum
|
||||
{
|
||||
EXTI_0 = BIT(0), /*!< EXTI line 0 */
|
||||
EXTI_1 = BIT(1), /*!< EXTI line 1 */
|
||||
EXTI_2 = BIT(2), /*!< EXTI line 2 */
|
||||
EXTI_3 = BIT(3), /*!< EXTI line 3 */
|
||||
EXTI_4 = BIT(4), /*!< EXTI line 4 */
|
||||
EXTI_5 = BIT(5), /*!< EXTI line 5 */
|
||||
EXTI_6 = BIT(6), /*!< EXTI line 6 */
|
||||
EXTI_7 = BIT(7), /*!< EXTI line 7 */
|
||||
EXTI_8 = BIT(8), /*!< EXTI line 8 */
|
||||
EXTI_9 = BIT(9), /*!< EXTI line 9 */
|
||||
EXTI_10 = BIT(10), /*!< EXTI line 10 */
|
||||
EXTI_11 = BIT(11), /*!< EXTI line 11 */
|
||||
EXTI_12 = BIT(12), /*!< EXTI line 12 */
|
||||
EXTI_13 = BIT(13), /*!< EXTI line 13 */
|
||||
EXTI_14 = BIT(14), /*!< EXTI line 14 */
|
||||
EXTI_15 = BIT(15), /*!< EXTI line 15 */
|
||||
EXTI_16 = BIT(16), /*!< EXTI line 16 */
|
||||
EXTI_17 = BIT(17), /*!< EXTI line 17 */
|
||||
EXTI_18 = BIT(18), /*!< EXTI line 18 */
|
||||
EXTI_19 = BIT(19) /*!< EXTI line 19 */
|
||||
}exti_line_enum;
|
||||
|
||||
/* external interrupt and event */
|
||||
typedef enum
|
||||
{
|
||||
EXTI_INTERRUPT = 0, /*!< EXTI interrupt mode */
|
||||
EXTI_EVENT /*!< EXTI event mode */
|
||||
}exti_mode_enum;
|
||||
|
||||
/* interrupt trigger mode */
|
||||
typedef enum
|
||||
{
|
||||
EXTI_TRIG_RISING = 0, /*!< EXTI rising edge trigger */
|
||||
EXTI_TRIG_FALLING, /*!< EXTI falling edge trigger */
|
||||
EXTI_TRIG_BOTH, /*!< EXTI rising and falling edge trigger */
|
||||
EXTI_TRIG_NONE /*!< without rising edge or falling edge trigger */
|
||||
}exti_trig_type_enum;
|
||||
|
||||
/* function declarations */
|
||||
/* initialization, EXTI lines configuration functions */
|
||||
/* deinitialize the EXTI */
|
||||
void exti_deinit(void);
|
||||
/* initialize the EXTI line x */
|
||||
void exti_init(exti_line_enum linex, exti_mode_enum mode, exti_trig_type_enum trig_type);
|
||||
/* enable the interrupts from EXTI line x */
|
||||
void exti_interrupt_enable(exti_line_enum linex);
|
||||
/* disable the interrupts from EXTI line x */
|
||||
void exti_interrupt_disable(exti_line_enum linex);
|
||||
/* enable the events from EXTI line x */
|
||||
void exti_event_enable(exti_line_enum linex);
|
||||
/* disable the events from EXTI line x */
|
||||
void exti_event_disable(exti_line_enum linex);
|
||||
/* enable the software interrupt event from EXTI line x */
|
||||
void exti_software_interrupt_enable(exti_line_enum linex);
|
||||
/* disable the software interrupt event from EXTI line x */
|
||||
void exti_software_interrupt_disable(exti_line_enum linex);
|
||||
|
||||
/* interrupt & flag functions */
|
||||
/* get EXTI line x interrupt pending flag */
|
||||
FlagStatus exti_flag_get(exti_line_enum linex);
|
||||
/* clear EXTI line x interrupt pending flag */
|
||||
void exti_flag_clear(exti_line_enum linex);
|
||||
/* get EXTI line x interrupt pending flag */
|
||||
FlagStatus exti_interrupt_flag_get(exti_line_enum linex);
|
||||
/* clear EXTI line x interrupt pending flag */
|
||||
void exti_interrupt_flag_clear(exti_line_enum linex);
|
||||
|
||||
#endif /* GD32F30X_EXTI_H */
|
||||
@@ -0,0 +1,375 @@
|
||||
/*!
|
||||
\file gd32f30x_fmc.h
|
||||
\brief definitions for the FMC
|
||||
|
||||
\version 2017-02-10, V1.0.0, firmware for GD32F30x
|
||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x
|
||||
\version 2018-12-25, V2.0.0, firmware for GD32F30x
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F30x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef GD32F30X_FMC_H
|
||||
#define GD32F30X_FMC_H
|
||||
|
||||
#include "gd32f30x.h"
|
||||
|
||||
/* FMC and option byte definition */
|
||||
#define FMC FMC_BASE /*!< FMC register base address */
|
||||
#define OB OB_BASE /*!< option bytes base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */
|
||||
#define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */
|
||||
#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */
|
||||
#define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */
|
||||
#define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */
|
||||
#define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */
|
||||
#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */
|
||||
#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */
|
||||
#define FMC_KEY1 REG32((FMC) + 0x44U) /*!< FMC unlock key register 1 */
|
||||
#define FMC_STAT1 REG32((FMC) + 0x4CU) /*!< FMC status register 1 */
|
||||
#define FMC_CTL1 REG32((FMC) + 0x50U) /*!< FMC control register 1 */
|
||||
#define FMC_ADDR1 REG32((FMC) + 0x54U) /*!< FMC address register 1 */
|
||||
#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */
|
||||
#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */
|
||||
|
||||
#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */
|
||||
#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/
|
||||
#define OB_DATA1 REG16((OB) + 0x04U) /*!< option byte data1 value*/
|
||||
#define OB_DATA2 REG16((OB) + 0x06U) /*!< option byte data2 value*/
|
||||
#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */
|
||||
#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */
|
||||
#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */
|
||||
#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */
|
||||
|
||||
/* bits definitions */
|
||||
/* FMC_WS */
|
||||
#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */
|
||||
|
||||
/* FMC_KEY0 */
|
||||
#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */
|
||||
|
||||
/* FMC_OBKEY */
|
||||
#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */
|
||||
|
||||
/* FMC_STAT0 */
|
||||
#define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */
|
||||
#define FMC_STAT0_PGERR BIT(2) /*!< flash program error flag bit */
|
||||
#define FMC_STAT0_WPERR BIT(4) /*!< erase/program protection error flag bit */
|
||||
#define FMC_STAT0_ENDF BIT(5) /*!< end of operation flag bit */
|
||||
|
||||
/* FMC_CTL0 */
|
||||
#define FMC_CTL0_PG BIT(0) /*!< main flash program for bank0 command bit */
|
||||
#define FMC_CTL0_PER BIT(1) /*!< main flash page erase for bank0 command bit */
|
||||
#define FMC_CTL0_MER BIT(2) /*!< main flash mass erase for bank0 command bit */
|
||||
#define FMC_CTL0_OBPG BIT(4) /*!< option bytes program command bit */
|
||||
#define FMC_CTL0_OBER BIT(5) /*!< option bytes erase command bit */
|
||||
#define FMC_CTL0_START BIT(6) /*!< send erase command to FMC bit */
|
||||
#define FMC_CTL0_LK BIT(7) /*!< FMC_CTL0 lock bit */
|
||||
#define FMC_CTL0_OBWEN BIT(9) /*!< option bytes erase/program enable bit */
|
||||
#define FMC_CTL0_ERRIE BIT(10) /*!< error interrupt enable bit */
|
||||
#define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
|
||||
|
||||
/* FMC_ADDR0 */
|
||||
#define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */
|
||||
|
||||
/* FMC_OBSTAT */
|
||||
#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */
|
||||
#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */
|
||||
#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */
|
||||
#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */
|
||||
|
||||
/* FMC_WP */
|
||||
#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */
|
||||
|
||||
/* FMC_KEY1 */
|
||||
#define FMC_KEY1_KEY BITS(0,31) /*!< FMC_CTL1 unlock key bits */
|
||||
|
||||
/* FMC_STAT1 */
|
||||
#define FMC_STAT1_BUSY BIT(0) /*!< flash busy flag bit */
|
||||
#define FMC_STAT1_PGERR BIT(2) /*!< flash program error flag bit */
|
||||
#define FMC_STAT1_WPERR BIT(4) /*!< erase/program protection error flag bit */
|
||||
#define FMC_STAT1_ENDF BIT(5) /*!< end of operation flag bit */
|
||||
|
||||
/* FMC_CTL1 */
|
||||
#define FMC_CTL1_PG BIT(0) /*!< main flash program for bank1 command bit */
|
||||
#define FMC_CTL1_PER BIT(1) /*!< main flash page erase for bank1 command bit */
|
||||
#define FMC_CTL1_MER BIT(2) /*!< main flash mass erase for bank1 command bit */
|
||||
#define FMC_CTL1_START BIT(6) /*!< send erase command to FMC bit */
|
||||
#define FMC_CTL1_LK BIT(7) /*!< FMC_CTL1 lock bit */
|
||||
#define FMC_CTL1_ERRIE BIT(10) /*!< error interrupt enable bit */
|
||||
#define FMC_CTL1_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
|
||||
|
||||
/* FMC_ADDR1 */
|
||||
#define FMC_ADDR1_ADDR BITS(0,31) /*!< Flash erase/program command address bits */
|
||||
|
||||
/* FMC_WSEN */
|
||||
#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */
|
||||
#define FMC_WSEN_BPEN BIT(1) /*!< FMC bit program enable bit */
|
||||
|
||||
/* FMC_PID */
|
||||
#define FMC_PID_PID BITS(0,31) /*!< product ID bits */
|
||||
|
||||
/* constants definitions */
|
||||
/* define the FMC bit position and its register index offset */
|
||||
#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
|
||||
#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6)))
|
||||
#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
|
||||
#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
|
||||
#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12)))
|
||||
#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
|
||||
#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
|
||||
#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12)
|
||||
|
||||
/* configuration register */
|
||||
#define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */
|
||||
#define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */
|
||||
#define FMC_STAT1_REG_OFFSET 0x4CU /*!< status register 1 offset */
|
||||
#define FMC_CTL1_REG_OFFSET 0x50U /*!< control register 1 offset */
|
||||
#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */
|
||||
|
||||
/* fmc state */
|
||||
typedef enum
|
||||
{
|
||||
FMC_READY, /*!< the operation has been completed */
|
||||
FMC_BUSY, /*!< the operation is in progress */
|
||||
FMC_PGERR, /*!< program error */
|
||||
FMC_WPERR, /*!< erase/program protection error */
|
||||
FMC_TOERR, /*!< timeout error */
|
||||
}fmc_state_enum;
|
||||
|
||||
/* FMC interrupt enable */
|
||||
typedef enum
|
||||
{
|
||||
FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */
|
||||
FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */
|
||||
FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1 end of program interrupt */
|
||||
FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< enable FMC bank1 error interrupt */
|
||||
}fmc_int_enum;
|
||||
|
||||
/* FMC flags */
|
||||
typedef enum
|
||||
{
|
||||
FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC bank0 busy flag */
|
||||
FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC bank0 operation error flag bit */
|
||||
FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC bank0 erase/program protection error flag bit */
|
||||
FMC_FLAG_BANK0_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC bank0 end of operation flag bit */
|
||||
FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */
|
||||
FMC_FLAG_BANK1_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U), /*!< FMC bank1 busy flag */
|
||||
FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), /*!< FMC bank1 operation error flag bit */
|
||||
FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U), /*!< FMC bank1 erase/program protection error flag bit */
|
||||
FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U), /*!< FMC bank1 end of operation flag bit */
|
||||
}fmc_flag_enum;
|
||||
|
||||
/* FMC interrupt flags */
|
||||
typedef enum
|
||||
{
|
||||
FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC bank0 operation error interrupt flag bit */
|
||||
FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC bank0 erase/program protection error interrupt flag bit */
|
||||
FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC bank0 end of operation interrupt flag bit */
|
||||
FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U), /*!< FMC bank1 operation error interrupt flag bit */
|
||||
FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U), /*!< FMC bank1 erase/program protection error interrupt flag bit */
|
||||
FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U), /*!< FMC bank1 end of operation interrupt flag bit */
|
||||
}fmc_interrupt_flag_enum;
|
||||
|
||||
/* unlock key */
|
||||
#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
|
||||
#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
|
||||
|
||||
/* FMC wait state counter */
|
||||
#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval)))
|
||||
#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */
|
||||
#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */
|
||||
#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */
|
||||
|
||||
/* option bytes software/hardware free watch dog timer */
|
||||
#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */
|
||||
#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */
|
||||
|
||||
/* option bytes reset or not entering deep sleep mode */
|
||||
#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */
|
||||
#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */
|
||||
|
||||
/* option bytes reset or not entering standby mode */
|
||||
#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */
|
||||
#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */
|
||||
|
||||
/* option bytes boot bank value */
|
||||
#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */
|
||||
#define OB_BOOT_B1 ((uint8_t)0x00U) /*!< boot from bank1 */
|
||||
|
||||
#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */
|
||||
|
||||
/* read protect configure */
|
||||
#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */
|
||||
#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */
|
||||
|
||||
/* OB_SPC */
|
||||
#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */
|
||||
#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */
|
||||
|
||||
/* OB_USER */
|
||||
#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */
|
||||
#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */
|
||||
|
||||
/* OB_WP0 */
|
||||
#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */
|
||||
|
||||
/* OB_WP1 */
|
||||
#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */
|
||||
|
||||
/* OB_WP2 */
|
||||
#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */
|
||||
|
||||
/* OB_WP3 */
|
||||
#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */
|
||||
|
||||
/* option bytes write protection */
|
||||
#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */
|
||||
#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */
|
||||
#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */
|
||||
#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */
|
||||
#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */
|
||||
#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */
|
||||
#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */
|
||||
#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */
|
||||
#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */
|
||||
#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */
|
||||
#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */
|
||||
#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */
|
||||
#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */
|
||||
#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */
|
||||
#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */
|
||||
#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */
|
||||
#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */
|
||||
#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */
|
||||
#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */
|
||||
#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */
|
||||
#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */
|
||||
#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */
|
||||
#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */
|
||||
#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */
|
||||
#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */
|
||||
#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */
|
||||
#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */
|
||||
#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */
|
||||
#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */
|
||||
#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */
|
||||
#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */
|
||||
#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */
|
||||
#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */
|
||||
|
||||
/* FMC timeout */
|
||||
#define FMC_TIMEOUT_COUNT ((uint32_t)0x0FFF0000U) /*!< FMC timeout count value */
|
||||
|
||||
/* FMC BANK address */
|
||||
#define FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU) /*!< FMC bank0 end address */
|
||||
#define FMC_BANK0_SIZE ((uint32_t)0x00000200U) /*!< FMC bank0 size */
|
||||
#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */
|
||||
|
||||
/* function declarations */
|
||||
/* FMC main memory programming functions */
|
||||
/* set the FMC wait state counter */
|
||||
void fmc_wscnt_set(uint32_t wscnt);
|
||||
/* unlock the main FMC operation */
|
||||
void fmc_unlock(void);
|
||||
/* unlock the FMC bank0 operation */
|
||||
void fmc_bank0_unlock(void);
|
||||
/* unlock the FMC bank1 operation */
|
||||
void fmc_bank1_unlock(void);
|
||||
/* lock the main FMC operation */
|
||||
void fmc_lock(void);
|
||||
/* lock the bank0 FMC operation */
|
||||
void fmc_bank0_lock(void);
|
||||
/* lock the bank1 FMC operation */
|
||||
void fmc_bank1_lock(void);
|
||||
/* FMC erase page */
|
||||
fmc_state_enum fmc_page_erase(uint32_t page_address);
|
||||
/* FMC erase whole chip */
|
||||
fmc_state_enum fmc_mass_erase(void);
|
||||
/* FMC erase whole bank0 */
|
||||
fmc_state_enum fmc_bank0_erase(void);
|
||||
/* FMC erase whole bank1 */
|
||||
fmc_state_enum fmc_bank1_erase(void);
|
||||
/* FMC program a word at the corresponding address */
|
||||
fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
|
||||
/* FMC program a half word at the corresponding address */
|
||||
fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
|
||||
/* FMC reprogram a word at the corresponding address without erasing */
|
||||
fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data);
|
||||
|
||||
/* FMC option bytes programming functions */
|
||||
/* unlock the option byte operation */
|
||||
void ob_unlock(void);
|
||||
/* lock the option byte operation */
|
||||
void ob_lock(void);
|
||||
/* erase the option byte */
|
||||
fmc_state_enum ob_erase(void);
|
||||
/* enable write protect */
|
||||
fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
|
||||
/* configure the option byte security protection */
|
||||
fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
|
||||
/* write the FMC option byte */
|
||||
fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot);
|
||||
/* program option bytes data */
|
||||
fmc_state_enum ob_data_program(uint32_t address, uint8_t data);
|
||||
/* get the FMC option byte user */
|
||||
uint8_t ob_user_get(void);
|
||||
/* get OB_DATA in register FMC_OBSTAT */
|
||||
uint16_t ob_data_get(void);
|
||||
/* get the FMC option byte write protection */
|
||||
uint32_t ob_write_protection_get(void);
|
||||
/* get option byte security protection code value */
|
||||
FlagStatus ob_spc_get(void);
|
||||
|
||||
/* FMC interrupts and flags management functions */
|
||||
/* enable FMC interrupt */
|
||||
void fmc_interrupt_enable(uint32_t interrupt);
|
||||
/* disable FMC interrupt */
|
||||
void fmc_interrupt_disable(uint32_t interrupt);
|
||||
/* check flag is set or not */
|
||||
FlagStatus fmc_flag_get(uint32_t flag);
|
||||
/* clear the FMC flag */
|
||||
void fmc_flag_clear(uint32_t flag);
|
||||
/* get FMC interrupt flag state */
|
||||
FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag);
|
||||
/* clear FMC interrupt flag state */
|
||||
void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag);
|
||||
/* return the FMC bank0 state */
|
||||
fmc_state_enum fmc_bank0_state_get(void);
|
||||
/* return the FMC bank1 state */
|
||||
fmc_state_enum fmc_bank1_state_get(void);
|
||||
/* check FMC bank0 ready or not */
|
||||
fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout);
|
||||
/* check FMC bank1 ready or not */
|
||||
fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout);
|
||||
|
||||
#endif /* GD32F30X_FMC_H */
|
||||
@@ -0,0 +1,114 @@
|
||||
/*!
|
||||
\file gd32f30x_fwdgt.h
|
||||
\brief definitions for the FWDGT
|
||||
|
||||
\version 2017-02-10, V1.0.0, firmware for GD32F30x
|
||||
\version 2018-10-10, V1.1.0, firmware for GD32F30x
|
||||
\version 2018-12-25, V2.0.0, firmware for GD32F30x
|
||||
\version 2020-09-30, V2.1.0, firmware for GD32F30x
|
||||
*/
|
||||
|
||||
/*
|
||||
Copyright (c) 2020, GigaDevice Semiconductor Inc.
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
1. Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
this list of conditions and the following disclaimer in the documentation
|
||||
and/or other materials provided with the distribution.
|
||||
3. Neither the name of the copyright holder nor the names of its contributors
|
||||
may be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
|
||||
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
|
||||
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
|
||||
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
|
||||
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
||||
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
|
||||
OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#ifndef GD32F30X_FWDGT_H
|
||||
#define GD32F30X_FWDGT_H
|
||||
|
||||
#include "gd32f30x.h"
|
||||
|
||||
/* FWDGT definitions */
|
||||
#define FWDGT FWDGT_BASE /*!< FWDGT base address */
|
||||
|
||||
/* registers definitions */
|
||||
#define FWDGT_CTL REG32((FWDGT) + 0x00U) /*!< FWDGT control register */
|
||||
#define FWDGT_PSC REG32((FWDGT) + 0x04U) /*!< FWDGT prescaler register */
|
||||
#define FWDGT_RLD REG32((FWDGT) + 0x08U) /*!< FWDGT reload register */
|
||||
#define FWDGT_STAT REG32((FWDGT) + 0x0CU) /*!< FWDGT status register */
|
||||
|
||||
/* bits definitions */
|
||||
/* FWDGT_CTL */
|
||||
#define FWDGT_CTL_CMD BITS(0,15) /*!< FWDGT command value */
|
||||
|
||||
/* FWDGT_PSC */
|
||||
#define FWDGT_PSC_PSC BITS(0,2) /*!< FWDGT prescaler divider value */
|
||||
|
||||
/* FWDGT_RLD */
|
||||
#define FWDGT_RLD_RLD BITS(0,11) /*!< FWDGT counter reload value */
|
||||
|
||||
/* FWDGT_STAT */
|
||||
#define FWDGT_STAT_PUD BIT(0) /*!< FWDGT prescaler divider value update */
|
||||
#define FWDGT_STAT_RUD BIT(1) /*!< FWDGT counter reload value update */
|
||||
|
||||
/* constants definitions */
|
||||
/* psc register value */
|
||||
#define PSC_PSC(regval) (BITS(0,2) & ((uint32_t)(regval) << 0))
|
||||
#define FWDGT_PSC_DIV4 ((uint8_t)PSC_PSC(0)) /*!< FWDGT prescaler set to 4 */
|
||||
#define FWDGT_PSC_DIV8 ((uint8_t)PSC_PSC(1)) /*!< FWDGT prescaler set to 8 */
|
||||
#define FWDGT_PSC_DIV16 ((uint8_t)PSC_PSC(2)) /*!< FWDGT prescaler set to 16 */
|
||||
#define FWDGT_PSC_DIV32 ((uint8_t)PSC_PSC(3)) /*!< FWDGT prescaler set to 32 */
|
||||
#define FWDGT_PSC_DIV64 ((uint8_t)PSC_PSC(4)) /*!< FWDGT prescaler set to 64 */
|
||||
#define FWDGT_PSC_DIV128 ((uint8_t)PSC_PSC(5)) /*!< FWDGT prescaler set to 128 */
|
||||
#define FWDGT_PSC_DIV256 ((uint8_t)PSC_PSC(6)) /*!< FWDGT prescaler set to 256 */
|
||||
|
||||
/* control value */
|
||||
#define FWDGT_WRITEACCESS_ENABLE ((uint16_t)0x5555U) /*!< FWDGT_CTL bits write access enable value */
|
||||
#define FWDGT_WRITEACCESS_DISABLE ((uint16_t)0x0000U) /*!< FWDGT_CTL bits write access disable value */
|
||||
#define FWDGT_KEY_RELOAD ((uint16_t)0xAAAAU) /*!< FWDGT_CTL bits fwdgt counter reload value */
|
||||
#define FWDGT_KEY_ENABLE ((uint16_t)0xCCCCU) /*!< FWDGT_CTL bits fwdgt counter enable value */
|
||||
|
||||
/* FWDGT timeout value */
|
||||
#define FWDGT_PSC_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_PSC register write operation state flag timeout */
|
||||
#define FWDGT_RLD_TIMEOUT ((uint32_t)0x000FFFFFU) /*!< FWDGT_RLD register write operation state flag timeout */
|
||||
|
||||
/* FWDGT flag definitions */
|
||||
#define FWDGT_FLAG_PUD FWDGT_STAT_PUD /*!< FWDGT prescaler divider value update flag */
|
||||
#define FWDGT_FLAG_RUD FWDGT_STAT_RUD /*!< FWDGT counter reload value update flag */
|
||||
|
||||
/* write value to FWDGT_RLD_RLD bit field */
|
||||
#define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
|
||||
|
||||
/* function declarations */
|
||||
/* enable write access to FWDGT_PSC and FWDGT_RLD */
|
||||
void fwdgt_write_enable(void);
|
||||
/* disable write access to FWDGT_PSC and FWDGT_RLD */
|
||||
void fwdgt_write_disable(void);
|
||||
/* start the free watchdog timer counter */
|
||||
void fwdgt_enable(void);
|
||||
|
||||
/* configure the free watchdog timer counter prescaler value */
|
||||
ErrStatus fwdgt_prescaler_value_config(uint16_t prescaler_value);
|
||||
/* configure the free watchdog timer counter reload value */
|
||||
ErrStatus fwdgt_reload_value_config(uint16_t reload_value);
|
||||
/* reload the counter of FWDGT */
|
||||
void fwdgt_counter_reload(void);
|
||||
/* configure counter reload value, and prescaler divider value */
|
||||
ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div);
|
||||
|
||||
/* get flag state of FWDGT */
|
||||
FlagStatus fwdgt_flag_get(uint16_t flag);
|
||||
|
||||
#endif /* GD32F30X_FWDGT_H */
|
||||
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Reference in New Issue
Block a user